JPH01280920A - Photoelectric switch - Google Patents

Photoelectric switch

Info

Publication number
JPH01280920A
JPH01280920A JP11116188A JP11116188A JPH01280920A JP H01280920 A JPH01280920 A JP H01280920A JP 11116188 A JP11116188 A JP 11116188A JP 11116188 A JP11116188 A JP 11116188A JP H01280920 A JPH01280920 A JP H01280920A
Authority
JP
Japan
Prior art keywords
light
emitting element
light emitting
receiving element
light receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11116188A
Other languages
Japanese (ja)
Inventor
Kiyoshi Kumada
清 熊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP11116188A priority Critical patent/JPH01280920A/en
Publication of JPH01280920A publication Critical patent/JPH01280920A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent malfunction due to incidence of a disturbance light by making a light projected from the 2nd light emitting element incident on the 1st photodetector and making a light projected from the 1st light emitting element incident on the 2nd photodetector conversely if a passing object exists respectively. CONSTITUTION:If no passing object 11 exists, the light projected from a 1st light emitting element 12 is made incident on a 1st light receiving element 14 and a light projected from the 2nd light emitting element is made incident on the 2nd light receiving element 13 respectively. When the passing object 11 exists, the light projected from the 1st light emitting element 15 is made incident on the 1st light receiving element 14 and a light projected from the 2nd light emitting element 12 is made incident on the 2nd light receiving element 13 respectively conversely. That is, the light projected from any of the light emitting elements 12, 15 is always made incident on both the light receiving element 13, 14 and the light is discriminated depending on the difference from the frequency. Thus, malfunction due to the incident of a disturbance light or the like is prevented to attain sure operation.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、発光素子と受光素子とが互いに対向して配置
され、その間を通過する物体の有無を検知する光電スイ
ッチに関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a photoelectric switch in which a light emitting element and a light receiving element are arranged facing each other and detect the presence or absence of an object passing between them.

〈従来技術〉 従来の光電スイッチは、例えば第8図に示す如く、対向
して配置される一組の発光素子1と受光素子2とで構成
され、その間を物体3が通過すると光路が遮断されて受
光素子2に光が入射しなくなることを利用して通過物体
3の検出を行なっていた。
<Prior Art> A conventional photoelectric switch, as shown in FIG. 8, for example, is composed of a pair of light emitting element 1 and light receiving element 2 that are arranged opposite each other, and when an object 3 passes between them, the optical path is interrupted. The passing object 3 is detected by utilizing the fact that no light is incident on the light receiving element 2.

また、第9図に示す如く、発光素子と受光素子が複数組
設けられ、通過物体3に対し一側に発光素子群4が、他
側に受光素子群5が配列されたものもある。
Further, as shown in FIG. 9, there is also one in which a plurality of sets of light-emitting elements and light-receiving elements are provided, and a light-emitting element group 4 is arranged on one side of the passing object 3, and a light-receiving element group 5 is arranged on the other side.

く 発明が解決しようとする問題点 〉上記従来技術に
おいて、受光素子には、発光素子からの光の池に、外乱
光が入射する場合がある。
Problems to be Solved by the Invention In the above-mentioned prior art, ambient light may enter the light receiving element into the light pool from the light emitting element.

この場合、通過物体が通過して発光素子からの光が遮断
されても、受光素子には外乱光が入射しており、通過物
体の通過を検出できないといっな問題点がある。
In this case, even if the passing object passes and the light from the light emitting element is blocked, disturbance light is incident on the light receiving element, and there is a problem that the passage of the passing object cannot be detected.

そこで、本発明は、外乱光の入射による誤動作を防止で
き、確実な動作が行なわれる光電スイッチの提供を目的
とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a photoelectric switch that can prevent malfunctions caused by the incidence of ambient light and that can operate reliably.

〈 問題点を解決するための手段 〉 本発明による問題点解決手段は、第1図〜第4図の如く
、発光素子と受光素子とが互いに対向して配置され、そ
の間を通過する物体の有無を検知する光電スイッチにお
いて、通過物体11に対し一側に第一発光素子12およ
び第二受光素子13が配設され、通過物体11に対し他
側に第一受光素子14および第二発光素子15が配設さ
れ、前記第一、第二発光素子12.15および第一、第
二受光素子13,14は、通過物体11が存在しない場
合、第一発光素子12から投射された光は第一受光素子
14に、第二発光素子15から投射された光は第二受光
素子13に夫々入射し、通過物体11が存在する場合、
第一発光素子12から投射された光は第二受光素子13
に、第二発光素子15から投射された光は第一受光素子
14に夫々入射するよう配列されたものである。
<Means for Solving the Problems> The means for solving the problems according to the present invention is as shown in FIGS. In a photoelectric switch for detecting a passing object 11, a first light emitting element 12 and a second light receiving element 13 are arranged on one side of the passing object 11, and a first light receiving element 14 and a second light emitting element 15 are arranged on the other side of the passing object 11. are arranged, and the first and second light emitting elements 12.15 and the first and second light receiving elements 13, 14 are arranged such that when there is no passing object 11, the light projected from the first light emitting element 12 is The light projected from the second light emitting element 15 to the light receiving element 14 enters the second light receiving element 13, and when there is a passing object 11,
The light projected from the first light emitting element 12 is transmitted to the second light receiving element 13.
Furthermore, the lights projected from the second light emitting elements 15 are arranged so as to be incident on the first light receiving elements 14, respectively.

〈作用〉 上記問題点解決手段において、通過物体11が存在しな
い場合、第一受光素子14には第一発光素子12から投
射された光が、第二受光素子13には第二発光素子15
から投射された光が夫々入射する。また、通過物体11
が存在する場合、逆に、第一受光素子14には第二発光
素子15から投射された光が、第二受光素子13には第
一発光素子12から投射された光が夫々入射する。
<Operation> In the problem solving means described above, when there is no passing object 11, the light projected from the first light emitting element 12 is transmitted to the first light receiving element 14, and the light projected from the second light emitting element 15 is transmitted to the second light receiving element 13.
The light projected from the two is incident on each of them. In addition, the passing object 11
, conversely, the light projected from the second light emitting element 15 enters the first light receiving element 14, and the light projected from the first light emitting element 12 enters the second light receiving element 13.

すなわち、両受光素子13.14には、常にどちらかの
発光素子12.15から投射された光が入射しており、
これらの光は周波数の違い等で判別されるため、外乱光
等の入射による誤動作を防止でき、確実な動作が行なわ
れる。
That is, the light projected from either light emitting element 12.15 is always incident on both light receiving elements 13.14,
Since these lights are discriminated based on differences in frequency, etc., it is possible to prevent malfunctions due to the incidence of disturbance light, etc., and ensure reliable operation.

〈実施例〉 以下、本発明の第一実施例を第1図〜第4図に基づいて
説明する。第1図は本発明の第一実施例における光電ス
イッチを示す発光素子および受光素子の配置図、第2図
は同じく制御回路のブロック図、第3図は同じくパルス
周期検出回路の電気回路図、第4図は同じく信号処理回
路の電気回路図、第5図は同じくタイミング発生回路の
発生するパルス信号のタイミングチャートである。
<Example> Hereinafter, a first example of the present invention will be described based on FIGS. 1 to 4. FIG. 1 is a layout diagram of a light emitting element and a light receiving element showing a photoelectric switch in a first embodiment of the present invention, FIG. 2 is a block diagram of a control circuit, and FIG. 3 is an electric circuit diagram of a pulse period detection circuit. FIG. 4 is an electric circuit diagram of the signal processing circuit, and FIG. 5 is a timing chart of pulse signals generated by the timing generation circuit.

そして、図示の如く、本発明光電スイッチは、発光素子
と受光素子とが互いに対向して配置され、その間を通過
する物体の有無を検知する光電スイッチにおいて、通過
物体11に対し一側に第一発光素子12および第二受光
素子13が配設され、通過物体11に対し他側に第一受
光素子14および第二発光素子15が配設され、前記第
一、第二発光素子12.15および第一、第二受光素子
13.14は、通過物体11が存在しない場合、第一発
光素子12から投射された光は第一受光素子14に、第
二発光素子15から投射された光は第二受光素子13に
夫々入射し、通過物体11が存在する場合、第一発光素
子12から投射された光は餉二受光素子13に、第二発
光素子15がら投射された光は第一受光素子14に夫々
入射するよう配列されたものである。
As shown in the figure, the photoelectric switch of the present invention is a photoelectric switch in which a light emitting element and a light receiving element are arranged facing each other, and detects the presence or absence of an object passing between them. A light emitting element 12 and a second light receiving element 13 are arranged, and a first light receiving element 14 and a second light emitting element 15 are arranged on the other side with respect to the passing object 11. When there is no passing object 11, the first and second light receiving elements 13 and 14 transmit the light projected from the first light emitting element 12 to the first light receiving element 14, and the light projected from the second light emitting element 15 to the first light receiving element 14. When the light is incident on the two light receiving elements 13 and there is a passing object 11, the light projected from the first light emitting element 12 is incident on the second light receiving element 13, and the light projected from the second light emitting element 15 is on the first light receiving element. 14, respectively.

前記発光素子12.15は、一般的な発光ダイオード等
により構成され、前記受光素子13.14は一般的なホ
トトランジスタ等により構成される。
The light emitting elements 12.15 are constituted by general light emitting diodes and the like, and the light receiving elements 13.14 are constituted by general phototransistors and the like.

そして、第1図の如く、通過物体11の進行方向(図に
おいて紙面に垂直方向)と垂直な面上に、前記第一発光
素子12、第一受光素子14、第二発光素子15および
第二受光素子13が配置され、第一発光素子12と第一
受光素子14は、通過物体11の中心を通る直線上に通
過物体11を挟んで対向して配される。また、第二発光
素子15と第二受光素子13は、通過物体11の中心を
通り前記第一発光素子12と第一受光素子14とを結ぶ
直線と鋭角(直角または鈍角でも可)に交差する直線上
に通過物体11を挟んで対向して配される。
As shown in FIG. 1, the first light emitting element 12, the first light receiving element 14, the second light emitting element 15, and the second light emitting element 12, A light-receiving element 13 is arranged, and the first light-emitting element 12 and the first light-receiving element 14 are arranged to face each other with the passing object 11 in between on a straight line passing through the center of the passing object 11 . Further, the second light emitting element 15 and the second light receiving element 13 intersect at an acute angle (a right angle or an obtuse angle) with a straight line passing through the center of the passing object 11 and connecting the first light emitting element 12 and the first light receiving element 14. They are arranged facing each other on a straight line with the passing object 11 in between.

そして、第2図の如く、これらの発光素子12゜15を
駆動し受光素子13.14の出力を検出する制御回路1
6は、互いに整数倍の関係にない二つの異なる周波数[
1,f2のパルス信号を発生するタイミング発生回路1
7と、該タイミング発生回路17の発生する周波数r1
のパルス信号と同期して前記第一発光素子12を駆動す
る第一発光素子駆動回路18と、前記タイミング発生回
路17の発生する周波数f2のパルス信号と同期して前
記第二発光素子15を駆動する第二発光素子駆動回路1
9と、前記第一受光素子14の出力電流を電圧に変換す
る第一電流電圧変換回路20と、前記第二受光素子13
の出力電流を電圧に変換する第二電流電圧変換回路21
と、前記第一電流電圧変換回路20の出力電圧を増幅す
る第一増幅回路22と、前記第二電流電圧変換回路21
の出力電圧を増幅する第二増幅回路23と、前記第一増
幅回路22の出力信号の周波数を検出する第一パルス周
期検出回路24ど、前記第二増幅回路23の出力信号の
周波数を検出する第二パルス周期検出回路25と、前記
第一パルス周期検出回路24および第二パルス周期検出
回路25の検出結果に基づいて検出信号を出力する信号
処理回路26および出力回路27とから成る。そして、
前記タイミング発生回路17の発生するパルス信号は、
例えぼ第5図の如く、周波数r1のパルス信号が、′H
”レベルの時間が6マイクロ秒、“L″レベル時間が0
.1ミlj秒の信号とされ、周波数r2のパルス信号が
、′H”レベルの時間は同+、”L″レベル時間が約3
分の2の信号とされる。
As shown in FIG. 2, a control circuit 1 drives these light emitting elements 12 and 15 and detects the outputs of the light receiving elements 13 and 14.
6 is two different frequencies that are not integral multiples of each other [
Timing generation circuit 1 that generates pulse signals of 1 and f2
7 and the frequency r1 generated by the timing generation circuit 17.
a first light emitting element driving circuit 18 that drives the first light emitting element 12 in synchronization with a pulse signal of; and a first light emitting element driving circuit 18 that drives the second light emitting element 15 in synchronization with a pulse signal of frequency f2 generated by the timing generation circuit 17. Second light emitting element drive circuit 1
9, a first current-voltage conversion circuit 20 that converts the output current of the first light receiving element 14 into voltage, and the second light receiving element 13.
a second current-voltage conversion circuit 21 that converts the output current of
, a first amplification circuit 22 that amplifies the output voltage of the first current-voltage conversion circuit 20, and a second current-voltage conversion circuit 21.
a second amplification circuit 23 that amplifies the output voltage of the first amplification circuit 22; a first pulse period detection circuit 24 that detects the frequency of the output signal of the first amplification circuit 22; It consists of a second pulse period detection circuit 25, and a signal processing circuit 26 and an output circuit 27 that output a detection signal based on the detection results of the first pulse period detection circuit 24 and the second pulse period detection circuit 25. and,
The pulse signal generated by the timing generation circuit 17 is
For example, as shown in Fig. 5, the pulse signal of frequency r1 is 'H
” level time is 6 microseconds, “L” level time is 0
.. The pulse signal of frequency r2 is a signal of 1 milliseconds, and the time of 'H' level is the same +, and the time of 'L' level is about 3
It is considered to be a signal of 2 times.

そして、前記第一パルス周期検出回路24は、第3図の
如く、−側の入力端子に前記第一増幅回路22の出力信
号が入力され池側の入力端子にサンプリング信号r3が
入力されるアンドデートにより構成されるサンプリング
デート28と、データ入力端子が前記サンプリングゲー
ト28の出力端子に接続されクロック入力端子に前記タ
イミング発生回路17の発生する周波数f1のパルス信
号から“H”レベルの時間の2分の1(3マイクロ秒)
だけ遅れた同一波形のパルス信号が入力されるD−7リ
ツプ70ツブにより構成される第一同期検出回路29と
、データ入力端子が前記サンプリングデート28の出力
端子に接続されタロツク入力端子に前記タイミング発生
回路17の発生する周波数12のパルス信号から“H″
レベル時間の2分の1(3マイクロ秒)だけ遅れた同一
波形のパルス信号が入力されるD−7リツプ70ツブに
より構成される第二同期検出回路30と、データ入力端
子が前記第一同期検出回路2つの出力端子に接続されク
ロック入力端子に前記タイミング発生回路17の発生す
る周波数11のパルス信号が入力される少なくとも三段
の第一シ7トレジスタ31と、データ入力端子が前記第
二同期検出回路30の出力端子に接続されクロック入力
端子に前記タイミング発生回路17の発生する周波数f
2のパル又信号が入力される少なくとも三段の第ニジ7
トレジスタ32と、前記第一シ7トレジスタ31の出力
端子の少なくとも三本の論理積をとるアンドゲートによ
り構成される第−周波数一致検出回路33と、前記第ニ
ジ7トレノスタ32の出力端子の少なくとも三本の論理
積をとるアンドデートにより構成される第二周波数−数
構出回路34とから成る。また、前記第二パルス周期検
出回路25も同様の構成である。そして、前記サンプリ
ング信号f3は、第5図の如く、周波数r1のパルス信
号と周波数r2のパルス信号との論理和をとって得られ
る。
As shown in FIG. 3, the first pulse period detection circuit 24 has an AND input terminal in which the output signal of the first amplification circuit 22 is input to the input terminal on the negative side, and a sampling signal r3 is input to the input terminal on the positive side. The data input terminal is connected to the output terminal of the sampling gate 28, and the data input terminal is connected to the output terminal of the sampling gate 28. 1 minute (3 microseconds)
A first synchronization detection circuit 29 is composed of 70 D-7 rip circuits to which pulse signals of the same waveform delayed by a certain amount of time are input, and a data input terminal is connected to the output terminal of the sampling date 28, and a taro clock input terminal is connected to the timing detection circuit 29. "H" from the pulse signal of frequency 12 generated by the generation circuit 17
A second synchronization detection circuit 30 constituted by a D-7 lip 70 to which a pulse signal of the same waveform delayed by one-half (3 microseconds) of the level time is input, and a data input terminal connected to the first synchronization At least three stages of first registers 31 connected to the two output terminals of the detection circuit and having a clock input terminal inputted with a pulse signal of frequency 11 generated by the timing generation circuit 17, and a data input terminal connected to the second synchronization The frequency f generated by the timing generation circuit 17 is connected to the output terminal of the detection circuit 30 and is connected to the clock input terminal.
At least three stages of Ni 7 to which the pulse or signal of No. 2 is input.
a third frequency coincidence detection circuit 33 constituted by an AND gate that takes the AND gate of at least three of the output terminals of the first seventh register 31; and at least three of the output terminals of the second seventh register 32; and a second frequency-number construction circuit 34 configured by AND-DATE, which performs the logical product of books. Further, the second pulse period detection circuit 25 also has a similar configuration. As shown in FIG. 5, the sampling signal f3 is obtained by ORing the pulse signal of frequency r1 and the pulse signal of frequency r2.

そして、前記信号処理回路26は、第4図の如く、前記
第一パルス周期検出回路24の第−周波数一致検出回路
33の出力信号A1、第一パルス周期検出回路24の第
二周波数−数構出回路34の出力信号B1、第二パルス
周期検出回路25の第−周波数一致検出回路(図示せず
)の出力信号A2および第二パルス周期検出回路25の
第二周波数−数構出回路(図示せず)の出力信号B2が
入力される入力デート回路35と、該入力デート回路3
5の出力端子に接続されるRSラッチ回路36とから成
る。そして、前記入力デート回路35は、第一の入力端
子が出力信号A1に、第二の入力端子がインバータ37
を介して出力信号Bitこ、第三の入力端子がインバー
タ38を介して出力信号A2に、第四の入力端子が出力
信号B2に夫々接続される四入力端子型の第一アンドデ
ート39と、第一の入力端子がインバータ40を介して
出力信号A1に、第二の入力端子が出力信号B1(こ、
第三の入力端子が出力信号A2に、第四の入力端子がイ
ンバータ41を介して出力信号B2に夫々接続される四
入力端子型の第二アンドデート42とから成る。また、
前記RSラッチ回路36のセット入力端子には前記第一
アンドデート39の出力端子が接続され、リセット入力
端子には前記第二アンドデート42の出力端子が夫々接
続される。
As shown in FIG. The output signal B1 of the output circuit 34, the output signal A2 of the second frequency coincidence detection circuit (not shown) of the second pulse period detection circuit 25, and the second frequency-number configuration circuit (not shown) of the second pulse period detection circuit 25 an input date circuit 35 to which the output signal B2 (not shown) is input, and the input date circuit 3
and an RS latch circuit 36 connected to the output terminal of No. 5. The input date circuit 35 has a first input terminal connected to the output signal A1, and a second input terminal connected to the inverter 37.
a four-input terminal type first AND date 39 whose third input terminal is connected to the output signal A2 via the inverter 38, and whose fourth input terminal is connected to the output signal B2 through the inverter 38; The first input terminal receives the output signal A1 via the inverter 40, and the second input terminal receives the output signal B1 (this,
It consists of a four-input terminal type second AND date 42 whose third input terminal is connected to the output signal A2 and whose fourth input terminal is connected to the output signal B2 via an inverter 41. Also,
The set input terminal of the RS latch circuit 36 is connected to the output terminal of the first AND date 39, and the reset input terminal is connected to the output terminal of the second AND date 42, respectively.

上記構成において、通過物体11が存在しない場合、第
1図中に実線で示される如く、第一発光素子12から投
射された光は直進して第一受光素子14に入射し、第二
発光素子15から投射された光は直進して第二受光素子
13に入射する。
In the above configuration, when there is no passing object 11, the light projected from the first light emitting element 12 travels straight and enters the first light receiving element 14, as shown by the solid line in FIG. The light projected from the light receiving element 15 travels straight and enters the second light receiving element 13.

また、通過物体11が存在する場合、第1図中に二点鎖
線で示される如く、第一発光素子12から投射された光
は通過物体11に反射して第二受光素子13に入射し、
第二発光素子15から投射された光は通過物体11に反
射して第一受光素子14に入射する。
Furthermore, when there is a passing object 11, the light projected from the first light emitting element 12 is reflected by the passing object 11 and enters the second light receiving element 13, as shown by the two-dot chain line in FIG.
The light projected from the second light emitting element 15 is reflected by the passing object 11 and enters the first light receiving element 14.

すなわち、通過物体11が存在しない場合には、第一受
光素子14に周波数f1のパルス光が、第二受光素子1
3に周波数f2のパルス光が夫々入射し、通過物体11
が存在する場合、第一受光素子14に周波数f2のパル
ス光が、第二受光素子13に周波数11のパルス光が入
射する。
That is, when there is no passing object 11, the pulsed light of frequency f1 is transmitted to the first light receiving element 14, and the pulsed light of frequency f1 is transmitted to the second light receiving element 1.
Pulse light of frequency f2 is incident on each of the passing objects 11 and 3.
exists, pulsed light of frequency f2 enters the first light-receiving element 14, and pulsed light of frequency 11 enters the second light-receiving element 13.

そして、この光は各受光素子13.14により電気信号
に交換され、電流電圧変換回路20,21で出力電流が
電圧に変換され、増幅回路22゜23で増幅が行なわれ
た後、パルス周期検出回路24.25に入る。
Then, this light is exchanged into an electric signal by each light receiving element 13, 14, the output current is converted into voltage by current-voltage conversion circuits 20 and 21, and after amplification is performed by amplifier circuits 22 and 23, the pulse period is detected. Enter circuit 24.25.

パルス周期検出回路24.25に入った信号は、その内
部の同期検出回路29.30で周波数fl、f2のパル
ス信号との同期が検出され、シフトレノスタ31.32
に記憶される過去3回の検出結果がすべて“H”レベル
に一致すると、−数構出回路33.34が出力信号を発
生する。
The signal entering the pulse period detection circuit 24.25 is detected to be in synchronization with the pulse signals of frequencies fl and f2 by the internal synchronization detection circuit 29.30, and the signal is sent to the shift reno star 31.32.
When all of the past three detection results stored in the output signal 33 match the "H" level, the minus number output circuits 33 and 34 generate output signals.

すなわち、入力信号の周波数がflと一致しているとき
は第−周波数一致検出回路33の出力端子が“H”レベ
ルとなり、r2と一致しているときは第二周波数−数構
出回路34の出力端子が“H”レベルとなり、どちらと
も一致していないとき(外乱光が入射したとき等)は両
−数構出回路33,34の出力端子が両方とも″L″レ
ベルとなる。
That is, when the frequency of the input signal matches fl, the output terminal of the first frequency match detection circuit 33 goes to "H" level, and when it matches r2, the output terminal of the second frequency match detection circuit 34 goes to "H" level. When the output terminals are at the "H" level, and they do not coincide with each other (such as when disturbance light is incident), the output terminals of the two-number output circuits 33 and 34 are both at the "L" level.

そして、信号処理回路26において、パルス周期検出回
路24.25から正常な出力信号(通過物体11が存在
しない場合、A1=H,B1=L、A2=L、B2=H
となり、通過物体11が存在する場合、A1=L、B1
=H%A2=H,B2=Lとなる)が得られた場合にの
み、RSラッチ回路36の出力を切換え、出力回路27
に出力信号を送る。
Then, in the signal processing circuit 26, the pulse period detection circuit 24.25 outputs a normal output signal (if there is no passing object 11, A1=H, B1=L, A2=L, B2=H
So, if there is a passing object 11, A1=L, B1
=H%A2=H, B2=L), the output of the RS latch circuit 36 is switched, and the output circuit 27 is switched.
send the output signal to.

また、パルス周期検出回路24.25から異常な出力信
号が得られた場合(第一受光素子14および第二受光素
子13に同一のパルス信号が入射した場合や、第一受光
素子14または第二受光素子13に外乱光が常に入射し
ている場合等)、RSラッチ回路36の出力は切換わら
ないため、外乱光その池の影響を受けずに安定した動作
を得ることができる。
In addition, if an abnormal output signal is obtained from the pulse period detection circuit 24 or 25 (if the same pulse signal is incident on the first light receiving element 14 and the second light receiving element 13, or when the same pulse signal is incident on the first light receiving element 14 or the second light receiving element 13, Since the output of the RS latch circuit 36 is not switched when ambient light is always incident on the light receiving element 13, stable operation can be obtained without being affected by the ambient light.

次に、本発明の第二実施例を説明する。Next, a second embodiment of the present invention will be described.

本実施例では、発光素子12.15および受光素子13
.14の配置が第一実施例と異なっている。
In this embodiment, the light emitting element 12.15 and the light receiving element 13
.. 14 is different from the first embodiment.

すなわち、第6図の如く、第一発光素子12と第一受光
素子14とが通過物体11の進行方向と直交する直線上
に対向して配置され、第二発光素子15が第一受光素子
14と隣接して配置され、第二受光素子13が第一発光
素子12と隣接して配置されており、両者の光路は交差
していない。
That is, as shown in FIG. 6, the first light emitting element 12 and the first light receiving element 14 are arranged facing each other on a straight line perpendicular to the traveling direction of the passing object 11, and the second light emitting element 15 is arranged opposite to the first light receiving element 14. The second light receiving element 13 is arranged adjacent to the first light emitting element 12, and their optical paths do not intersect.

そして、通過物体11が存在していない場合は、第6図
中の実線の如く、第一発光素子12がら投射された光は
直進して第一受光素子14に入射し、第二発光素子15
がら投射された光は直進して第二受光素子13に入射す
る。
When there is no passing object 11, the light projected from the first light emitting element 12 travels straight and enters the first light receiving element 14, as shown by the solid line in FIG.
The projected light travels straight and enters the second light receiving element 13.

また、通過物体11が存在している場合は、第6図中の
二点鎖線の如く、第一発光素子12から投射された光は
通過物体11に乱反射して第二受光素子13に入射し、
第二発光素子15がら投射された光は通過物体11に乱
反射して第一受光素子14に入射する。
Furthermore, when there is a passing object 11, the light projected from the first light emitting element 12 is diffusely reflected by the passing object 11 and enters the second light receiving element 13, as shown by the two-dot chain line in FIG. ,
The light projected from the second light emitting element 15 is diffusely reflected by the passing object 11 and enters the first light receiving element 14 .

このとき、通過物体11が鏡の如く光を正反射するもの
であれば、発光素子12.15および受光素子13.1
4としてやや広角の指向特性を持つものを使用するとよ
い。
At this time, if the passing object 11 specularly reflects light like a mirror, the light emitting element 12.15 and the light receiving element 13.1
It is preferable to use one with slightly wide-angle directional characteristics as No. 4.

次に、本発明の第三実施例を説明する。Next, a third embodiment of the present invention will be described.

本実施例によると、第一発光素子12と第二発光素子1
5は交互に発光しており、制御回路16の構成が簡単に
なるとともに、異常$態が発生したことを検出すること
ができる。
According to this embodiment, the first light emitting element 12 and the second light emitting element 1
5 alternately emit light, which simplifies the configuration of the control circuit 16 and makes it possible to detect the occurrence of an abnormal $ state.

そして、本実施例において、発光素子12.15および
受光素子13.14は、第一実施例または第二実施例の
どちらの配列でもよく、さらに別の配列でもよい。
In this embodiment, the light emitting elements 12.15 and the light receiving elements 13.14 may be arranged in either the first embodiment or the second embodiment, or in another arrangement.

そして、その制御回路16は、第7図の如く、デユーテ
ィ比が50パーセントの周波数14のパルス信号を発生
するタイミング発生回路17と、該パルス信号に同期し
て第一発光素子12を駆動する第一発光素子駆動回路1
8と、前記パルス信号をインバータ(反転回路)43に
より反転した信号と同期して第二発光素子15を駆動す
る第二発光素子駆動回路19と、第一実施例と同様の第
一電流電圧変換回路20、第二電流電圧変換回路21、
第一増幅回路22および第二増幅回路23と、−側の入
力端子が前記第一増幅回路22の出力端子に接続され他
側の入力端子に前記タイミング発生回路17の発生する
周波数f4のパルス信号が入力される第一エクスクル−
シブオアデート44(EX−ORデート)と、−側の入
力端子が前記第二増幅回路23の出力端子に接続され他
側の入力端子に前記タイミング発生回路17の発生する
周波数「4のパルス信号が入力される第二EX−○Rデ
ート45と、前記第−EX−ORデート44の出力端子
に接続される比較的小さい時定数を有する第一積分回路
46と、前記第二EX−ORゲート45の出力端子に接
続される比較的小さい時定数を有する第二積分回路47
と、リセット入力端子が前記第一積分回路46に接続さ
れセット入力端子が前記第二積分回路47に接続される
RSラッチ回路48と、−側の入力端子が前記第−EX
−ORデート44の出力端子に他側の入力端子が前記第
二EX−ORデート45の出力端子に夫々接続される第
三EX−ORデート49と、該第三EX−ORデート4
9の出力端子に接続される第三積分回路50とから成る
。そして、前記第一積分回路46は抵抗51とコンデン
サ52とから成り、前記第二積分回路47は、同様に抵
抗53とコンデンサ54とから成る。また、前記第三積
分回路50は、ダイオード55、抵抗S 6,57、コ
ンデンサ58およびバッファデート59から成り、該バ
ッファデート59の出力端子が異常報知出力端子となる
As shown in FIG. 7, the control circuit 16 includes a timing generation circuit 17 that generates a pulse signal of a frequency 14 with a duty ratio of 50%, and a timing generation circuit 17 that drives the first light emitting element 12 in synchronization with the pulse signal. One light emitting element drive circuit 1
8, a second light emitting element drive circuit 19 that drives the second light emitting element 15 in synchronization with a signal obtained by inverting the pulse signal by an inverter (inversion circuit) 43, and a first current-voltage conversion circuit similar to the first embodiment. circuit 20, second current-voltage conversion circuit 21,
The first amplifier circuit 22 and the second amplifier circuit 23 have a negative input terminal connected to the output terminal of the first amplifier circuit 22, and a pulse signal of frequency f4 generated by the timing generation circuit 17 at the other input terminal. The first exclude to be entered is
The input terminal on the negative side of the positive or date 44 (EX-OR date) is connected to the output terminal of the second amplifier circuit 23, and the pulse signal of frequency "4" generated by the timing generation circuit 17 is input to the input terminal on the other side. a second EX-OR date 45 which is connected to the output terminal of the -EX-OR date 44; a second integration circuit 47 with a relatively small time constant connected to the output terminal;
and an RS latch circuit 48 whose reset input terminal is connected to the first integrating circuit 46 and whose set input terminal is connected to the second integrating circuit 47, and whose negative input terminal is connected to the -EX
- a third EX-OR date 49 whose input terminal on the other side is connected to the output terminal of the OR date 44 and the output terminal of the second EX-OR date 45; and the third EX-OR date 49;
and a third integrating circuit 50 connected to the output terminal of 9. The first integrating circuit 46 includes a resistor 51 and a capacitor 52, and the second integrating circuit 47 similarly includes a resistor 53 and a capacitor 54. Further, the third integrating circuit 50 includes a diode 55, resistors S6, 57, a capacitor 58, and a buffer date 59, and the output terminal of the buffer date 59 serves as an abnormality notification output terminal.

そして、通過物体11が存在していない場合、第−EX
−ORデート44の面入力端子は常に一致するため、そ
の出力端子は継続的に“L”レベルを出力し、第二EX
−ORデート45の面入力端子は常に一致しないため、
その出力端子は継続的に“H″レベル出力する。
If the passing object 11 does not exist, the -EX
- Since the plane input terminals of OR date 44 always match, its output terminal continuously outputs "L" level, and the second EX
- Since the surface input terminals of OR date 45 do not always match,
The output terminal continuously outputs the "H" level.

また、通過物体11が存在する場合は、その逆に、第−
EX−ORデート44の出力端子は継続的に“H”レベ
ルを出力し、第二EX−○Rデート45の出力端子は継
続的に“L”レベルを出力する。
In addition, if there is a passing object 11, conversely, the -th
The output terminal of the EX-OR date 44 continuously outputs the "H" level, and the output terminal of the second EX-OR date 45 continuously outputs the "L" level.

ユニで、第一積分回路46は、第−EX−ORデート4
4の面入力端子に加わる信号の伝達時間のわずかな差に
より、その出力端子から発生する極めて細いパルス信号
を除去するものである。第二積分回路47も同様の機能
を有する。
In Uni, the first integrating circuit 46 is the -EX-OR date 4
Due to the slight difference in transmission time of the signals applied to the surface input terminals No. 4, extremely thin pulse signals generated from the output terminals are removed. The second integrating circuit 47 also has a similar function.

この出力信号によりRSラッチ回路48の出力が切換わ
り、動作信号を得ることができる。
The output of the RS latch circuit 48 is switched by this output signal, and an operating signal can be obtained.

そして、上記正常動作時は、第−EX−ORゲート44
の出力端子と第二EX−ORゲート45の出力端子とは
常に相反しているため、第三EX−ORゲート49の出
力端子は継続的に“L”レベルを保つ。
During the normal operation, the -EX-OR gate 44
Since the output terminal of the third EX-OR gate 49 and the output terminal of the second EX-OR gate 45 are always opposite to each other, the output terminal of the third EX-OR gate 49 continuously maintains the "L" level.

しかし、何らかの異常動作が発生すると、第三EX−O
Rゲート49の出力端子が継続的に“H”レベルとなっ
たり(両方の受光素子13.14に同一の光が入射した
場合等)、周波数「4のパルス信号を出力(片方のみの
受光素子に継続した光が入射した場合等)する。この信
号は、異常報知信号として用いられ、使用者に異常を報
知することができる。
However, if some abnormal operation occurs, the third EX-O
If the output terminal of the R gate 49 remains at "H" level continuously (such as when the same light is incident on both light receiving elements 13 and 14), a pulse signal with a frequency of "4" is output (when only one light receiving element (e.g. when continuous light is incident).This signal is used as an abnormality notification signal and can notify the user of the abnormality.

なお、本実施例の制御回路16では、一方の受光素子に
継続した光が入射し、能力の受光素子に全く光が入射し
なくなった場合に異常報知信号を出力しないが、この場
合にはRSラッチ回路48の出力が異常に早く(周波数
f4と同じ周波数)切換わることから、異常動作である
ことが検知できる。
Note that the control circuit 16 of this embodiment does not output an abnormality notification signal when light continues to enter one of the light receiving elements and no light enters the other light receiving element; however, in this case, the RS An abnormal operation can be detected because the output of the latch circuit 48 switches abnormally quickly (same frequency as frequency f4).

このように本実施例によると、制御回路16の構成が簡
単になるとともに、異常事態が発生したことを検出する
ことができる。
As described above, according to this embodiment, the configuration of the control circuit 16 is simplified, and the occurrence of an abnormal situation can be detected.

なお、本発明は、上記実施例に限定されるものではなく
、本発明の範囲内で上記実施例に多くの修正および変更
を加え得ることは勿論である。
It should be noted that the present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.

例えば、二組以上の発光素子と受光素子を設けてもよく
、また、発光素子を夫々異なった色で発光させる等の方
法でどちらの発光素子から投射された光が受光素子に入
射したか判別してもよい。
For example, two or more sets of light-emitting elements and light-receiving elements may be provided, and it can be determined which light-emitting element the light projected from has entered the light-receiving element by a method such as making each light-emitting element emit light in a different color. You may.

〈発明の効果〉 以上の説明から明らかな通り、本発明によると、通過物
体に対し一側に第一発光素子および第二受光素子が配設
され、通過物体に対し他側に第一受光素子および第二発
光素子が配設され、前記第一、第二発光素子および第一
、第二受光素子は、通過物体が存在しない場合、第一受
光素子には第一発光素子から投射された光が、第二受光
素子には第二発光素子から投射された光が夫々入射し、
通過物体が存在する場合、逆に、第一受光素子には第二
発光素子から投射された光が、第二受光素子には第一発
光素子から投射された光が夫々入射するよう配列されて
おり、両受光素子には、常にどちらかの発光素子から投
射された光が入射し、これらの光は周波数の違い等によ
り判別されるため、外乱光の入射による誤動作を防止で
き、確実な動作が行なわれるといった優れた効果がある
<Effects of the Invention> As is clear from the above description, according to the present invention, the first light emitting element and the second light receiving element are arranged on one side with respect to the passing object, and the first light receiving element is arranged on the other side with respect to the passing object. and a second light emitting element are disposed, and the first and second light emitting elements and the first and second light receiving elements are arranged so that when there is no passing object, the first light receiving element receives the light projected from the first light emitting element. However, the light projected from the second light emitting element enters the second light receiving element, respectively,
Conversely, when there is a passing object, the arrangement is such that the light projected from the second light emitting element enters the first light receiving element, and the light projected from the first light emitting element enters the second light receiving element. The light emitted from either light emitting element always enters both light receiving elements, and these lights are discriminated based on differences in frequency, etc., which prevents malfunctions due to the incidence of external light and ensures reliable operation. It has excellent effects such as:

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第一実施例における光電スイッチを示
す発光素子および受光素子の配置図、第2図は同じく制
御回路のブロック図、第3図は同じくパルス周期検出回
路の電気回路図、第4図は同じく信号処理回路の電気回
路図、第5図は同じくタイミング発生回路の発生するパ
ルス信号のタイミングチャート、第6図は本発明の第二
実施例における光電スイッチを示す発光素子および受光
素子の配置図、第7図は本発明の第三実施例における制
御回路のブロック図、第8図および第9図は従来の光電
スイッチを示す発光素子および受光素子の配置図である
。 11:通過物体、12:第一発光素子、13:第二受光
素子、14:第一受光素子、15:第二発光素子、16
二制御回路、17:タイミング発生回路、18.19:
発光素子駆動回路、20.21:電流電圧変換回路、2
2,23:増幅回路、24,25:パルス周期検出回路
、26:信号処理回路、27:出力回路。 出 願 人  シャープ株式会社
FIG. 1 is a layout diagram of a light emitting element and a light receiving element showing a photoelectric switch in a first embodiment of the present invention, FIG. 2 is a block diagram of a control circuit, and FIG. 3 is an electric circuit diagram of a pulse period detection circuit. FIG. 4 is an electrical circuit diagram of the signal processing circuit, FIG. 5 is a timing chart of pulse signals generated by the timing generation circuit, and FIG. 6 is a light emitting element and light receiving device showing a photoelectric switch in a second embodiment of the present invention. FIG. 7 is a block diagram of a control circuit in a third embodiment of the present invention, and FIGS. 8 and 9 are layout diagrams of a light emitting element and a light receiving element showing a conventional photoelectric switch. 11: Passing object, 12: First light emitting element, 13: Second light receiving element, 14: First light receiving element, 15: Second light emitting element, 16
2. Control circuit, 17: Timing generation circuit, 18.19:
Light emitting element drive circuit, 20.21: Current voltage conversion circuit, 2
2, 23: amplifier circuit, 24, 25: pulse period detection circuit, 26: signal processing circuit, 27: output circuit. Applicant Sharp Corporation

Claims (1)

【特許請求の範囲】[Claims] 発光素子と受光素子とが互いに対向して配置され、その
間を通過する物体の有無を検知する光電スイッチにおい
て、通過物体に対し一側に第一発光素子および第二受光
素子が配設され、通過物体に対し他側に第一受光素子お
よび第二発光素子が配設され、前記第一、第二発光素子
および第一、第二受光素子は、通過物体が存在しない場
合、第一発光素子から投射された光は第一受光素子に、
第二発光素子から投射された光は第二受光素子に夫々入
射し、通過物体が存在する場合、第一発光素子から投射
された光は第二受光素子に、第二発光素子から投射され
た光は第一受光素子に夫々入射するよう配列されたこと
を特徴とする光電スイッチ。
In a photoelectric switch in which a light emitting element and a light receiving element are arranged facing each other and detecting the presence or absence of an object passing between them, the first light emitting element and the second light receiving element are arranged on one side with respect to the passing object, and the first light emitting element and the second light receiving element are arranged on one side with respect to the passing object. A first light-receiving element and a second light-emitting element are arranged on the other side with respect to the object, and the first and second light-emitting elements and the first and second light-receiving elements are arranged so that when there is no passing object, the first light-receiving element and the second light-emitting element The projected light is directed to the first light receiving element,
The light projected from the second light emitting element enters the second light receiving element, and when there is a passing object, the light projected from the first light emitting element enters the second light receiving element. A photoelectric switch characterized in that the light is arranged so that the light is incident on each of the first light receiving elements.
JP11116188A 1988-05-07 1988-05-07 Photoelectric switch Pending JPH01280920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11116188A JPH01280920A (en) 1988-05-07 1988-05-07 Photoelectric switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11116188A JPH01280920A (en) 1988-05-07 1988-05-07 Photoelectric switch

Publications (1)

Publication Number Publication Date
JPH01280920A true JPH01280920A (en) 1989-11-13

Family

ID=14554023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11116188A Pending JPH01280920A (en) 1988-05-07 1988-05-07 Photoelectric switch

Country Status (1)

Country Link
JP (1) JPH01280920A (en)

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