JPH01280347A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01280347A JPH01280347A JP63110992A JP11099288A JPH01280347A JP H01280347 A JPH01280347 A JP H01280347A JP 63110992 A JP63110992 A JP 63110992A JP 11099288 A JP11099288 A JP 11099288A JP H01280347 A JPH01280347 A JP H01280347A
- Authority
- JP
- Japan
- Prior art keywords
- metal oxide
- oxide film
- film
- electrode
- conductive metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 53
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 abstract description 13
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000007704 transition Effects 0.000 abstract description 10
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910002113 barium titanate Inorganic materials 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 abstract 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 abstract 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 239000013543 active substance Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
ダイナミック・ランダム・アクセス・メモリの如く構成
要素として容量を具備した半導体装置に於ては、容量部
の面積を極力小さくすることが上記半導体装置の高密度
化を進める上で重要である。In a semiconductor device including a capacitor as a component, such as a dynamic random access memory, it is important to reduce the area of the capacitor part as much as possible in order to increase the density of the semiconductor device.
容量部の占める面積を小さくするためには、従来のＳｉ
Ｏ□やＳｉ３Ｎ４よりも大きな誘電率を持つ誘電体材料
を用いるのが有利であり、このためＴａ酸化物、Ｔｉ酸
化物、 Ｚｒ酸化物、 Ｉｆ酸化物などからなる金属酸
化膜、さらにはＢａＴｉＯ３の如き強誘電体材料からな
る膜を用いることが試みられている。これら誘電体膜を
形成する方法としては、
（１）Ｔａ、Ｔｉ、Ｚｒ、Ｈｆなどの金属材料をターゲ
ットとしてスパッタ蒸着法により基板表面に金属膜を形
成した後にこれを酸化する方法、
（２）スパッタ蒸着を酸素雰囲気中で行い、基板上に金
属酸化物として堆積する手法、
（３）ＣＶＤ法により基板上に金属酸化膜を堆積する方
法、
などが用いられる。In order to reduce the area occupied by the capacitive part, conventional Si
It is advantageous to use a dielectric material with a larger dielectric constant than O□ or Si3N4, and for this reason metal oxide films made of Ta oxide, Ti oxide, Zr oxide, If oxide, etc., and even BaTiO3 Attempts have been made to use films made of ferroelectric materials such as ferroelectric materials. Methods for forming these dielectric films include: (1) a method of forming a metal film on the substrate surface by sputter deposition using a metal material such as Ta, Ti, Zr, Hf, etc. as a target, and then oxidizing it; (3) A method in which a metal oxide film is deposited on a substrate by sputter deposition in an oxygen atmosphere, and (3) a method in which a metal oxide film is deposited on a substrate by a CVD method.
Ｔａ酸化物、Ｔｉ酸化物などの金属酸化物からなる膜を
単結晶シリコン上あるいは多結晶シリコンの電極上に形
成すると、本来得られるべき高い容量値が低下してしま
うという欠点がある。この現象は、特に金属酸化膜の膜
厚が薄いはど順著となる。この原因は、金属酸化膜とシ
リコンまたは多結晶シリコン電極との間に５ｉｎ）＜の
如き誘電率の低い遷移層（比誘電率４程度）が形成され
ることによる。即ち、観察される容量値は金属酸化膜の
容量と遷移層の容量との直列接続された値になり、金属
酸化膜の膜厚が薄く等該膜の容量が大きい場合には、観
察される容量値は容量の小さな遷移層の容量に大きく支
配されるからである。When a film made of a metal oxide such as Ta oxide or Ti oxide is formed on a single crystal silicon or polycrystalline silicon electrode, there is a drawback that the high capacitance that should originally be obtained is reduced. This phenomenon is particularly noticeable when the metal oxide film is thin. This is due to the formation of a low dielectric constant transition layer (relative dielectric constant of about 4) between the metal oxide film and the silicon or polycrystalline silicon electrode. In other words, the observed capacitance value is the series connection of the capacitance of the metal oxide film and the capacitance of the transition layer, and when the capacitance of the metal oxide film is large, such as when the thickness of the metal oxide film is thin, This is because the capacitance value is largely controlled by the capacitance of the transition layer, which has a small capacitance.
シリコンと金属酸化膜との界面に遷移層が形成される理
由は、金属酸化膜が酸素を放出し易い（還元され易い）
性質を持ち、シリコンの如き酸化され易い活性な物質に
接すると酸素を放出する結果、界面に５ｉｎ）（層が形
成されるものである。この遷移層の膜厚は、透過型電子
頂微鏡による高解像度の断面観察によれば、２０〜３５
人と極めて薄い。しかし、例えば、比誘電率２５、膜厚
１００人の金属酸化膜を形成した場合には、観察される
容量値は遷移層の無い場合に比べ４５％以下になってし
まう。従って、シリコン上に金属酸化膜を形成した場合
には、金属酸化膜が本来有する誘電率の高い膜としての
性質を生ずことは出来ないという問題がある。The reason why a transition layer is formed at the interface between silicon and metal oxide film is that metal oxide film easily releases oxygen (easily reduced).
When it comes into contact with an active substance that is easily oxidized, such as silicon, it releases oxygen, resulting in the formation of a layer of 5 inches at the interface.The thickness of this transition layer is According to high-resolution cross-sectional observation by
Extremely thin compared to people. However, for example, if a metal oxide film with a dielectric constant of 25 and a thickness of 100% is formed, the observed capacitance value will be 45% or less compared to the case without a transition layer. Therefore, when a metal oxide film is formed on silicon, there is a problem in that the properties of a film with a high dielectric constant, which a metal oxide film originally has, cannot be achieved.
上記した遷移層の問題を改善する一つの手段として、酸
化され易いシリコンの代りに活性度のより低い電極材料
膜の上に金属酸化膜を設けることが行われている。即ち
、シリコン基板上に一旦ＷＳｉ２．ＭｏＳｉ２．ＴｉＳ
ｉ２の如き金属珪化物膜を設けた後に、金属酸化膜を形
成するものである。しかし、金属珪化物は組成としてシ
リコンが含まれるため、金属酸化膜との反応を防止する
ためには膜形成後のプロセスを３５０℃以下の温度に抑
える必要がある。このような限定された条件では、半導
体装置を作る上で制約が大きく、応用が限定されてしま
う欠点を持っていた。As one means to improve the above-mentioned problem of the transition layer, a metal oxide film is provided on an electrode material film with lower activity in place of silicon, which is easily oxidized. That is, WSi2. MoSi2. TiS
After a metal silicide film such as i2 is provided, a metal oxide film is formed. However, since metal silicide contains silicon as a composition, it is necessary to suppress the temperature of the process after film formation to 350° C. or lower in order to prevent reaction with the metal oxide film. Such limited conditions have the drawback of severely restricting the fabrication of semiconductor devices and limiting their applications.
本発明の半導体装置は、シリコン層上または金属珪化物
から成る電極層上に設けられた導電性金属酸化膜と、該
導電性金属酸化膜上に設けられた絶縁性金属酸化物から
成る誘電体膜と、該誘電体膜上に設けられた電極とで構
成される容量を含んで構成される。The semiconductor device of the present invention includes a conductive metal oxide film provided on a silicon layer or an electrode layer made of metal silicide, and a dielectric material made of an insulating metal oxide provided on the conductive metal oxide film. It is configured to include a capacitor composed of a film and an electrode provided on the dielectric film.
第１図は本発明の第１の実施例の断面図である。 FIG. 1 is a sectional view of a first embodiment of the invention.
シリコン基板１の表面に周知の技術を用いて選択的に絶
縁膜２を設け、次に熱拡散またはイオン打込みの技術を
用いて高濃度不純物領域３を形成する。次に、ＴｉＯ２
膜またはＴｉＯ□と５ｎ０２の混合膜などの導電性を有
する金属酸化膜４を、スパッタ蒸着法あるいは気相成長
法などの手法を用いて形成する。この導電性金属酸化膜
４の好ましい膜厚は２０〜１１００ｎである０次に、周
知の技術を用いて導電性金属酸化膜４を選択的にエツチ
ングし、所望の領域に膜を残す。次に、Ｔａ２０ｑ、Ｚ
ｒＯ□。An insulating film 2 is selectively provided on the surface of a silicon substrate 1 using a well-known technique, and then a high concentration impurity region 3 is formed using a thermal diffusion or ion implantation technique. Next, TiO2
A conductive metal oxide film 4 such as a film or a mixed film of TiO□ and 5n02 is formed using a technique such as sputter deposition or vapor phase growth. The preferred thickness of the conductive metal oxide film 4 is 20 to 1100 nm.Next, the conductive metal oxide film 4 is selectively etched using a well-known technique, leaving the film in desired areas. Next, Ta20q, Z
rO□.
）ｉｆ０２またはＢａＴｉＯ３の如き絶縁性を有する金
属酸化膜５をスパッタ蒸着法あるいは気相成長法などの
手法を用いて形成する。次に、電極６を所望の領域に形
成し、本発明になる容量が形成される。) A metal oxide film 5 having insulating properties such as if02 or BaTiO3 is formed using a method such as a sputter deposition method or a vapor phase growth method. Next, the electrode 6 is formed in a desired region, and the capacitor according to the present invention is formed.
なお、上記した構造の容量において、高濃度不純物領域
３の導電型はシリコン基板１と逆型であっても、あるい
は同型であっても良く、その選択は自由である。さらに
、高濃度不純物領域３を設けずに、直接シリコン基板１
に接触せしめても良い。In the capacitance of the above-described structure, the conductivity type of the high concentration impurity region 3 may be the opposite type to the silicon substrate 1 or the same type, and the selection thereof is free. Furthermore, without providing the high concentration impurity region 3, directly on the silicon substrate 1.
may be brought into contact with.
第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
第１の実施例では、導電性金属酸化膜４を高濃度不純物
領域３の表面及び絶縁膜２の表面の一部に設けたが、第
２の実施例では高濃度不純物領域３の表面にのみ設けた
。このようにしても、シリコン基板との間に遷移層を形
成しないという点で第１の実施例と同じである。In the first embodiment, the conductive metal oxide film 4 was provided on the surface of the high concentration impurity region 3 and a part of the surface of the insulating film 2, but in the second embodiment, the conductive metal oxide film 4 was provided only on the surface of the high concentration impurity region 3. Established. Even in this case, it is the same as the first embodiment in that no transition layer is formed between the silicon substrate and the silicon substrate.
第３図は本発明の第３の実施例の断面図である。FIG. 3 is a sectional view of a third embodiment of the invention.
この実施例は、高濃度不純物領域３と絶縁膜２の一部の
上に多結晶シリコンの電極７を設け、その上に導電性金
属酸化膜４、絶縁性金属酸化膜５、電極６を設けたもの
である。In this embodiment, a polycrystalline silicon electrode 7 is provided on a high concentration impurity region 3 and a part of an insulating film 2, and a conductive metal oxide film 4, an insulating metal oxide film 5, and an electrode 6 are provided thereon. It is something that
導電性金属酸化膜４は多結晶シリコンの電極７に接触し
ているため、電極７に印加された電圧が導電性酸化膜４
にそのまま印加される。Since the conductive metal oxide film 4 is in contact with the polycrystalline silicon electrode 7, the voltage applied to the electrode 7 is applied to the conductive metal oxide film 4.
is applied as is.
第４図は本発明の第４の実施例の断面図である。FIG. 4 is a sectional view of a fourth embodiment of the present invention.
この実施例は本発明をＤ ＲＡ Ｍ （Ｄｙｎａｍｉｃ
ＲａｎｄｏｔｒｃＡｃｃｅｓｓ Ｍｅｍｏｒｙ）に適
用した例である。This embodiment demonstrates the present invention in a DRAM (Dynamic
This is an example applied to (RandotrcAccess Memory).
高濃度不純物領域３ａ、３ｂをソース・ドレイン領域、
ワード線１０をゲート電極とするＦＥＴに本発明にかか
る容量が接続される。容量は、導電性金属酸化膜４と絶
縁性金属酸化膜５と電極７とで構成される。導電性金属
酸化膜４は高濃度不純物領域３ｂに接しているので、高
濃度不純物領域３ｂに印加された電圧は導電性金属酸化
膜にそのまま印加される。High concentration impurity regions 3a and 3b are source/drain regions,
A capacitor according to the present invention is connected to a FET having the word line 10 as a gate electrode. The capacitor is composed of a conductive metal oxide film 4, an insulating metal oxide film 5, and an electrode 7. Since the conductive metal oxide film 4 is in contact with the high concentration impurity region 3b, the voltage applied to the high concentration impurity region 3b is directly applied to the conductive metal oxide film.
第５図は本発明の第５の実施例の断面図である。FIG. 5 is a sectional view of a fifth embodiment of the present invention.
この実施例は、ＤＲＡＭと第３の実施例とを組合せたも
ので、高濃度不純物領域３ｂと導電性金属酸化膜４との
間に多結晶シリコンの電８ｉ！７を設けている。それ以
外は第４の実施例と同じである。This embodiment is a combination of a DRAM and the third embodiment, and has a polycrystalline silicon electrode 8i! between a high concentration impurity region 3b and a conductive metal oxide film 4. 7 is provided. The rest is the same as the fourth embodiment.
第６図は本発明の第６の実施例の断面図である。FIG. 6 is a sectional view of a sixth embodiment of the present invention.
この実施例は、容量値を大きくするために溝を堀ってそ
こに容量を設けたＤＲＡＭに本発明を適用した例である
。溝の内壁に沿って高濃度不純物３ｃが形成され、その
上に導電性金属酸化膜４、絶縁性金属酸化膜５、電極６
が形成されて容量を構成する。それ以外は第４の実施例
と同じである。This embodiment is an example in which the present invention is applied to a DRAM in which a groove is dug and a capacitance is provided therein in order to increase the capacitance value. A high concentration impurity 3c is formed along the inner wall of the groove, and a conductive metal oxide film 4, an insulating metal oxide film 5, and an electrode 6 are formed on it.
is formed and constitutes a capacity. The rest is the same as the fourth embodiment.
以上説明したように本発明は、酸°素に対して活性なシ
リコン基板、多結晶シリコンの電極及び珪化物の電極の
表面に一旦導電性を有する金属酸化膜を設けた後に絶縁
性を有する金属酸化膜を設ける構造にしたので、５ｉｎ
Ｘの如き遷移層の形成による容量の低下が防止できる効
果がある。また、本発明にかかる容量は、誘電体として
の金属酸化膜および導電性を有する金属酸化膜とも酸化
物であるため、耐熱性にも優れており、６００”Ｃでも
電気特性に変化は見られないという信頼性向上の効果も
ある。As explained above, in the present invention, a conductive metal oxide film is once provided on the surface of a silicon substrate active against oxygen, a polycrystalline silicon electrode, and a silicide electrode, and then an insulating metal Since the structure is provided with an oxide film, the 5-in.
This has the effect of preventing a decrease in capacity due to the formation of a transition layer such as X. In addition, the capacitor according to the present invention has excellent heat resistance because both the metal oxide film as a dielectric material and the metal oxide film with conductivity are oxides, and there is no change in electrical characteristics even at 60"C. There is also the effect of improving reliability.
第１図乃至第６図はそれぞれ本発明の第１乃至第６の実
施例の断面図である。
１・・・シリコン基板、２・・・絶縁膜、３．３ａ。
３ｂ、３ｃ・・・高濃度不純物領域、４・・・導電性金
属酸化膜、５・・・絶縁性金属酸化膜、６川電極、７・
・・電極、８・・・ゲート絶縁膜、９・・・絶縁膜、１
ｏ・・・ワード線、１］・・・ビット線。
代理人 弁理士 内 原 音
第乙図1 to 6 are sectional views of first to sixth embodiments of the present invention, respectively. 1... Silicon substrate, 2... Insulating film, 3.3a. 3b, 3c... High concentration impurity region, 4... Conductive metal oxide film, 5... Insulating metal oxide film, 6 River electrode, 7...
... Electrode, 8... Gate insulating film, 9... Insulating film, 1
o...word line, 1]...bit line. Agent Patent Attorney Uchihara Otoichi
Claims (1)
られた導電性金属酸化膜と、該導電性金属酸化膜上に設
けられた絶縁性金属酸化物から成る誘電体膜と、該誘電
体膜上に設けられた電極とで構成される容量を含むこと
を特徴とする半導体装置。A conductive metal oxide film provided on a silicon layer or an electrode layer made of metal silicide, a dielectric film made of an insulating metal oxide provided on the conductive metal oxide film, and the dielectric film What is claimed is: 1. A semiconductor device comprising a capacitor configured with an electrode provided above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63110992A JPH01280347A (en) | 1988-05-06 | 1988-05-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63110992A JPH01280347A (en) | 1988-05-06 | 1988-05-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01280347A true JPH01280347A (en) | 1989-11-10 |
Family
ID=14549655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63110992A Pending JPH01280347A (en) | 1988-05-06 | 1988-05-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01280347A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5192871A (en) * | 1991-10-15 | 1993-03-09 | Motorola, Inc. | Voltage variable capacitor having amorphous dielectric film |
| JPH0766300A (en) * | 1993-08-09 | 1995-03-10 | Internatl Business Mach Corp <Ibm> | Capacitor and its manufacture |
| KR100390849B1 (en) * | 2001-06-30 | 2003-07-12 | 주식회사 하이닉스반도체 | Method for fabricating capacitor having hafnium oxide |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01222468A (en) * | 1988-03-02 | 1989-09-05 | Toshiba Corp | Capacitor for semiconductor device |
-
1988
- 1988-05-06 JP JP63110992A patent/JPH01280347A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01222468A (en) * | 1988-03-02 | 1989-09-05 | Toshiba Corp | Capacitor for semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5192871A (en) * | 1991-10-15 | 1993-03-09 | Motorola, Inc. | Voltage variable capacitor having amorphous dielectric film |
| WO1993008610A1 (en) * | 1991-10-15 | 1993-04-29 | Motorola, Inc. | Voltage variable capacitor having amorphous dielectric film |
| JPH0766300A (en) * | 1993-08-09 | 1995-03-10 | Internatl Business Mach Corp <Ibm> | Capacitor and its manufacture |
| KR100390849B1 (en) * | 2001-06-30 | 2003-07-12 | 주식회사 하이닉스반도체 | Method for fabricating capacitor having hafnium oxide |
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