JPH01278366A - Printing data control circuit - Google Patents

Abstract

PURPOSE:To generate a printing dot image at high speed to enhance a printing speed, by a method wherein, synthetic data is operated by a printing data control circuit to be written to a dot line memory based on a start instruction from a microprocessor. CONSTITUTION:For example, if a character code for an alphabet 'A' is transmitted, a microprocessor 13 receives this code and stores the same in a main memory 15 which is a memory for an operation of its own. Then, the microprocessor 13 reads the character code for 'A' from the main memory 15, calculates an address in a character pattern generator 16 storing therein a character pattern corresponding to the character code, reads a dot pattern for the character 'A', and writes the dot pattern for the character 'A' into a dot line memory 20. An address signal (a) and a data signal (c) are respectively sent from the microprocessor 13 through a printing address control circuit 17 and a printing data control circuit 18 to the dot line memory 20. The pattern data is synthesized by the printing data control circuit 18 based on a write start instruction to the dot line memory 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control circuit for a dot matrix printer, and more particularly to a print data control circuit that is a control circuit for data signals to a dot line memory that temporarily stores printed dot images. .

[Conventional technology]

Conventionally, in this type of dot matrix printer, print data was controlled by a microprocessor. , second
Consider the case of writing a character dot pattern as shown in Figure (b).

In other words, this is a case where the half-width characters shown in FIG. 4B are inserted into the frame shown in FIG.

The data signals of microprocessors currently in general use can usually only have a specific number of bits, such as 4 bits, 8 bits, or 16 bits.

Therefore, in a circuit configured with a microprocessor, the memory connected to the microprocessor is configured so that a specific number of bits, such as 4 bits, 8 bits, or 16 bits, can be accessed in one read or write operation. For example, if a microprocessor has a 16-bit data signal, both the character pattern generator and the dot line memory are usually configured so that the data signal is 16 bits.

will be accomplished.

However, since the size of the dot pattern of the printed character is not specified, it may be 8 dots horizontally by 16 bits vertically, such as the half-width alphabet "A" shown in FIG. 2(b). In this case, when reading data from the character pattern generator, only 8 bits out of 16 bits are significant signals, and the other 8 bits are meaningless. Therefore,
If the 16-bit data read from this character pattern generator is written directly to the dot line memory, meaningless data will also be written, so the dot image on the dot line memory will not be as shown in Figure 2 (C). It won't happen.

Therefore, the microprocessor performs the operation shown in FIG. 2(D). First, the dot pattern shown in (B) in the same figure is read from the character pattern generator ((D)
Reference) This data and “FF0O (hexadecimal representation of binary number)
” is performed and the meaningless part of the data is made zero (see (D) in the same figure) 0 Next, significant data is shifted to the write position (see (D) in the same figure) (Refer to (2)) In the figure, the case of 4-bit shift is taken as an example.

Next, read the data in the dot line memory in (A) of the same figure (see (D) (■) in the same figure), and combine the read data with the "FO"
OF (hexadecimal representation of a binary number)" is performed (see (D) ■ in the same figure). Finally, a logical OR operation is performed between the character generator data ■ and the dot line memory data ■. The data is written to the dot line memory.

As a result, 8 bits of the 16-bit data read from the dot line memory are replaced with an 8 bit character dot pattern and stored in the dot line memory again.

[Problem to be solved by the invention]

As described above, in the conventional print data control system, the dot pattern read from the character pattern generator is manipulated by the calculations of the microprocessor.

For this reason, the time required for microprocessor calculations accounts for a large proportion of the time required to transfer character dot patterns from the character pattern generator to the dot line memory, which limits the performance of printing dot image generation. This in turn causes a decrease in printing speed.

[Purpose of the invention]

The present invention has been made in view of these points, and an object of the present invention is to provide a print data control circuit that can generate print dot images at high speed and improve printing speed. be.

[Means to solve the problem]

The present invention combines first pattern data stored in a dot line memory and second pattern data generated from a character pattern generator based on instructions from a microprocessor to generate a printed dot image. In the print data control circuit obtained, a position data storage means temporarily stores data indicating position information at the time of combining the first and second pattern data, and a first position data storage means stores the first and second pattern data, respectively. and second pattern data storage means. Furthermore, in the present invention, the second pattern data generated from the character pattern generator based on commands for character pattern generation and write activation by the microprocessor is stored in the second pattern data storage means, and the position data storage means , arithmetic processing means for calculating a printed dot image using the data stored in the first, -, and second pattern data storage means and storing it in the dot line memory. . This aims to achieve the above objective.

[For production]

According to this invention, the printing dot image composition calculation is performed as follows:
This is performed by the arithmetic processing means of the print data control circuit.

At this time, the microprocessor only generates second pattern data from the character pattern generator and starts writing the combined printed dot image into the dot line memory, but does not perform any arithmetic processing on the combined image.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

First, an example of a control circuit for a dot or matrix printer to which the embodiment is applied will be described with reference to FIG. In FIG. 4, the control circuits include a microprocessor 139, a communication control circuit 14, a main memory 151, a character pattern generator 16. Print address control circuit 17. Print data control circuit 18, timing control circuit 19. Dot line memory 20. and a shift register 21. and an address signal a which is an output signal of the microprocessor 13 and gives the address of the memory and register to be read and written.

A control signal C that provides identification and timing for reading and writing, a data signal C that provides data to the memory and registers during writing, and a data signal C that provides data from the memory and registers during reading, are connected so that they are exchanged between each circuit. A microprocessor 13 performs overall control.

In the above-mentioned device, the communication control circuit 14 functions as an interface with a higher-level device, and from the higher-level device, print data mainly expressed in character codes, for example, as shown in FIG. 2(B), is transmitted. In case, the letter “A”
The character code will be sent.

The microprocessor 13 receives this and stores it in its own working memory, the main memory 15. Next, the microprocessor 12 reads the character code of "A" from the main memory 15, calculates the address of the character pattern generator 16 where the character pattern corresponding to the character code is stored, and calculates the address of the character pattern generator 16 where the character pattern corresponding to the character code is stored. Lead the dot pattern. Thereafter, microprocessor 13 writes the dot pattern of the letter "A" into dot line memory 20.

The address signal a of the microprocessor 13 is sent to the print address control circuit 17. Data signal C is print data control circuit 1
8 to the dot line memory 20, respectively.

In this case, the synthesis of pattern data as shown in FIG.
This is performed by the print data control circuit 18 based on the start of writing to the dot line memory by No. 3.

Control signals necessary for reading and writing the dot line memory 20 are generated by the timing control circuit 19. The shift register 21 converts read data from the dot line memory 20 into a serial signal suitable for transmission to the printing mechanism section 22.

In the printing mechanism section 22, a print head (not shown) is driven based on the input serial signal, and printing as shown in FIG. 2(C) is performed.

Next, the configuration of an embodiment of the print data control circuit 18 described above will be described with reference to FIG.

In the figure, an address signal a and a control signal S of a microprocessor 13 are input to a decoder circuit 1, and the first register 2 and the second register are controlled by these address signal a and control signal S. Latch pulse signals d and e for the register 3 and an activation pulse signal r for triggering dot line memory access in the timing control circuit 12 are generated.

The first register 2 and the second register 3 to which the first data signal C, which is the data signal of the microprocessor 13, are input each receive a latch pulse signal d.

It has a function of latching the data of the first data signal C at the time when e occurs.

The output signal g of the first register 2 is input to a shift circuit 4 and a logic operation circuit 5, respectively. The output signal g input to the shift circuit 4 is a signal for setting the shift number of the output signal relative to the input signal C in the shift circuit 4, and the signal g in the logic operation circuit 5 is a signal for selecting the type of logic operation. It is.

In this way, the shift circuit 4 is a circuit that shifts input data according to the set number of shifts and outputs the shifted data. In this case, the output signal of the shift circuit 4 is input to one input terminal of the logic operation circuit 5.

The output signal i of the second register 3 is transmitted to the first AND circuit 6
One input side of the logic inverter 7 and the logical negation circuit 7 are respectively powered manually. The output signal j of this logical NOT circuit 7 is input to one input side of the second AND circuit 8.

The other input signal of the first AND circuit 6 is the output signal of the logic operation circuit 5. In this first AND circuit 6,
Data set in second register 3 and logic operation circuit 5
The output signal of is subjected to logic with the above data.

Next, the third register 8 contains a dot line memory 20.
A second data signal 1, which is a data signal of
The timing control circuit 12 latches in response to a latch pulse signal m generated in synchronization with reading of the dot line memory 20. The output signal n of the third register 9 is output to one input side of the logic operation circuit 5 and one input side of the second AND circuit 8, respectively.

Next, the output signal 0 of the first AND circuit 6 and the output signal p of the second AND circuit 8 are connected to be input to an OR circuit 10, respectively. The output signal q of the OR circuit 10 is input to the buffer circuit 11, and the output signal of the buffer circuit 11 is the second data/evening signal! It becomes. The buffer circuit 11 is a timing control circuit 12.
has a function of passing the input signal q as the output signal 1 by the buffer enable signal r generated in synchronization with the writing of the dot line memory 20.

Next, the timing control circuit 12 controls the dot line memory 2 by the activation pulse signal f generated by the decoder circuit 1.
It starts reading or writing data to 0, and generates a latch pulse signal m, a buffer enable signal r, and a control signal S for the dot line memory 20, respectively.

Next, the overall operation of the above embodiment will be explained with reference to FIGS. 3 and 5. Note that FIG. 3 shows the logical operation process, and FIG. 5 shows the flowchart of the operation. Also, here, the microprocessor 13
The input/output data signal of the character pattern generator 16° dot line memory 20 is also 18 bits.
Assume that it is 6 bits. Furthermore, a character pattern generator 16
Of the part of the dot pattern of the character read from (one word here), the significant patterns are 15 to 12 bits and 11 to 8 bits, and 7 to 0 bits are meaningless. Hereinafter, these will be referred to as AI and A2°C, respectively (see FIG. 3).

First, the shift number corresponding to the address or location to be written is set in the first register 2 (see step SA in FIG. 5). For example, if the write location is from the 4th pit, the shift number is set to 4 in the first register 2.
(The binary number is set.

Similarly, position designation data corresponding to the location to be written is set in the second register 3 (step SB
reference). For example, in the example shown in Figure 2, the data to be written is 8 bits from the 4th bit, so "0FFO (hexadecimal representation of binary number)" is set in the second register 3 (the hexadecimal representation of a binary number). (See Figure 3).

Therefore, the input terminal of the first AND circuit 6 has “0FFO(
"FOOF (hexadecimal representation of a binary number)" appears at the input terminal of the second AND circuit 8 (see FIG. 3).

Next, the microprocessor 13 activates the timing control circuit 12 and reads the corresponding dot pattern data from the dot line memory 20 (
(See step SC in Figure 5).

These dot pattern data are then sequentially divided into 4 bits each starting from the 15th bit: B1, B2, . They will be referred to as B3°B4 (see Figure 3). The read dot pattern data (B1.B2.B3, B4) is latched into the third register 9 (see step SC in FIG. 5).

As described above, the first step. second and third registers 2,
3.9, the microprocessor 13 outputs the data (At, A2 .
C), the timing control circuit 12 writes to the dot line memory 20 (see step SC in FIG. 5). Then, the shift circuit 4 outputs data shifted by 4 bits (C, AI, A2°C) (
3) is generated, and this is input to the logic operation circuit 5.

On the other hand, since the output signal n of the third register is input to this logic operation circuit 5, the output signal of the logic operation circuit 5 has the operation results of ■ and ■ in FIG. If we make it a logical sum, we get something like ■ in the same figure.

3 appear at the input terminal of the first AND circuit 1 in the next stage, and the output signal 0 becomes as shown in the figure. Also, since ■ and ■ in the figure appear at the input terminal of the second AND circuit 8, the output signal p becomes as shown in ■ in the figure. The respective output signals of the first AND circuit 6 and the second AND circuit 8 are input to the OR circuit 10, so the input terminals of the OR circuit 10 are
appears, and its output signal q becomes like ■ in the same figure (fifth
(see figure step SC).

The data (81, B2VA1° B2VA2.84) obtained in this way passes through the buffer circuit 11 by the buffer enable signal m generated in synchronization with the write timing of the dot line memory 20, and is transferred to the dot line memory 20. 20 (see step SC in FIG. 5).

As described above, according to this embodiment, necessary data is stored in advance in the register of the print data control circuit, and then the print data control circuit calculates the composite data based on the activation command from the microprocessor. , it is decided to write to the dot line memory, so the microprocessor does not need to perform calculations on the composite data.

Therefore, the dot pattern read from the character pattern generator and the dot pattern in the dot line memory are quickly synthesized and written to the dot line memory, and a printed dot image is generated at high speed. , the printing speed will be improved.

It should be noted that the present invention is not limited to the above-mentioned embodiment in any way; for example, the logic operation portion in the print data control circuit shown in FIG. 1 can be modified in various ways to achieve the same effect.

[Effects of the Invention] As explained above, according to the present invention, since the calculation for determining the printed dot image is performed by the print data control circuit, the generation of the printed dot image becomes faster, and the printing speed increases. It is possible to provide a print data control circuit that is unprecedented and excellent in that it is possible to improve the performance of the print data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the print data control circuit of the present invention, Fig. 2 is an explanatory diagram of a conventional print data control method, and Fig. 3 is an explanatory diagram of the operation of the print data control circuit according to the embodiment. , FIG. 4 is a block diagram of the control circuit of the dot matrix printer according to the embodiment, and FIG. 5 is a flowchart showing the operation of the embodiment. DESCRIPTION OF SYMBOLS 1... Decoder circuit, 2... First register, 3...
...Second register, 4...Shift circuit, 5...Logic operation circuit, 6...First AND circuit, 7...Logic NOT circuit. 8... Second AND circuit, 9... Third register,
10... OR circuit, 11... Buffer circuit, 12
... timing control circuit, 13 ... microprocessor, 14 ... communication control circuit, 15 ... main memory,
16... Character generator, 17... Print address control circuit, 18... Print data control circuit. 19... Timing control circuit, 20... Dot line memory, 21... Shift register, 22... Printing mechanism section a... Address signal, b... Control signal, C.
...first data signal, d...latch pulse signal, e
...Latch pulse signal, f...Start pulse signal 9g
...Output signal of the first register, h...Output signal of the shift circuit. i...Output signal of the second register, j...Output signal of the logic NOT circuit, k...Output signal of the logic operation circuit. l...Second data signal 2m...Latch pulse signal n...Output signal of the third register, 0...Output signal of the first AND circuit, p...Second logic Output signal of the product circuit, 0... Output signal of the first AND circuit, p...
Output signal of the second AND circuit, q... Output signal of the OR circuit, r... Buffer enable signal, S... Output signal of the dot line memory. Patent applicant Nippon Electric Co., Ltd. Agent Patent attorney Isamu Takahashi Figure 2 (A) (C) 4th cause

Claims (1)

[Claims] (1) First pattern data stored in the dot line memory based on instructions from the microprocessor;
In a print data control circuit which obtains a print dot image by combining the second pattern data generated from the character pattern generator, data indicating the position information at the time of combining the first and second pattern data is temporarily stored. position data storage means for storing the first and second pattern data, respectively; and position data storage means for storing the first and second pattern data respectively; , second pattern data generated from the character pattern generator is stored in the second pattern data storage means, and is stored in the position data storage means, first and second pattern data storage means, respectively. A print data control circuit comprising: arithmetic processing means for calculating a print dot image using data and storing it in the dot line memory.