JPS6354254A - Printer - Google Patents

Abstract

PURPOSE:To enable high-speed high-density printing to be easily performed and simplify control, by providing an inverting means for converting bit arrangement of data and inverting the ON/OFF states of bits of the converted data, a means for holding parallel printing data and reading the data, and a means for converting the read data into serial data with magnification at a predetermined magnifying power and outputting the serial data. CONSTITUTION:First, set points are loaded into a command register 24. Next, a command for selecting one of latches A-H is given to a latch-controlling circuit 2, and printing data are written into the selected latch. An MSB or LSB inverting processing by an output-inverting circuit 25, a data-inverting processing by a data-inverting circuit 26 or the like is executed according to the set points previously loaded in the command register 24, and the resultant data are written into the latch. After writing the converted data into the latches A-H, an MPU 100 outputs a serial output starting signal from a trigger circuit 3, thereby starting an output-controlling circuit 12. By this, serial outputting is started, and the data outputted to a printing head driving part 600 through a serial buffer 21 with a magnification rate of 2 times.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printing device, and particularly to a printing device that prints out a desired pattern in a dot matrix.

[Prior Art] In recent years, as the functions of printing and recording devices (hereinafter referred to as printers) have improved, there has been a particular trend toward higher speeds and higher resolutions.

Many printers are equipped with a microprocessor unit (hereinafter referred to as
Various controls were carried out using an MPU (called an MPU), and processing of print data was also carried out under arithmetic control using software. Therefore, in order to meet the demands for higher speed and higher resolution, it is necessary to use a high-speed and highly functional MPU.

Under these circumstances, recent dot matrix-type high-speed, high-resolution printers have become popular, with some having two printing modes: a draft printing mode and a fair copy printing mode. In this type of printer, high resolution is not required in the normal draft printing mode, and high speed is primarily required. High resolution is required only in the fair print mode.

In order to support these two printing modes, for example, two character generators that generate two types of printing patterns are provided, one of which is selected depending on the printing mode, and a desired pattern is generated. It is equipped with only a means for generating character data for normal printing (data for fine print), and when in draft print mode, character data for normal printing (fair print-1 data) is processed by a program to generate print data for draft. Either method was used to create it.

[Problem to be Solved by the Invention 1] Among the above two methods, the method including two print pattern generating means requires a complicated configuration, and when only one pattern generating means is provided, pattern conversion is required in the MPU. The processing alone took a lot of time.

Furthermore, in printing processing, data MSB and LSB inversion processing and data "0" and "1" inversion processing may be necessary. Also, when printing dot images, etc.
It may be necessary to convert print data to fit data with different dot densities to the print head.

Since these processes were performed by arithmetic control according to the program, it took a lot of processing time and the MPU
It had to be complicated and expensive to process at high speeds, which was a problem in achieving high-speed printing.

[Means for Solving the Problems] The present invention has been made for the purpose of solving the problems of the above-mentioned prior art, and includes the following configuration as a means for solving the problems.

That is, a conversion means for converting the bit array of print data;
an inverting means for inverting bit on/off of print data;
A holding means for holding parallel print data, a reading means for reading out the parallel print data held by the holding means, and an output for converting the parallel print data read by the reading means into serial data enlarged by a predetermined magnification. and means.

[Operation] In the above configuration, each process is executed in real time,
Converting parallel print data to serial data while enlarging it at a desired enlargement rate and outputting it, converting the bit array and bit conversion as necessary 6 [Embodiment] Hereinafter, the present invention will be described with reference to the drawings. One embodiment will be described in detail.

FIG. 1 is a schematic block diagram of an embodiment according to the present invention, in which reference numeral 100 indicates a central processing unit (100) that controls the entire apparatus according to the control procedure stored in the built-in ROM10I.
(hereinafter referred to as rMPUJ); 200 is a data conversion unit that converts print data and outputs it to print heads 610 to 640 according to output data and control signals from MPU 100;
For example, 00 is an input/output interface that controls an interface with an external device that outputs print data, 400 is a print buffer that holds print data sent from the external device via the input/output interface 30o, and 500 is a conveyor for transporting recording paper. The recording paper transport unit 600 to be controlled moves the print head 610 according to the print data from the data conversion unit 200.
~640 and print heads 610-640.
Print head drive unit that performs 8-shift control, 610°62
0.630,640 are print heads 0-3.

Details of the data converter 200 are shown in FIG. 1 in Figure 2
2 is an input buffer that also serves as an interface for each signal from the MPU 100, 2 is a latch control circuit for distributing the print data placed on Do-D7, which is a data signal from the MPU 100, to latch A4 to latch H1l, and 3 is an output control circuit. Trigger circuit 12 activates the trigger circuit, and latches 4 to 11 latch the parallel print data sent from the manual buffer 1 via the sending inversion circuit 25 and data inversion circuit 26. ~11
), the output circuit control circuit controls the output of the output circuits A-H (13 to 20) that takes in the parallel print data latched to the output circuit and serially outputs it; 13 to 20 are the output circuits A-
H, takes in parallel data from latches A to H (4 to 11), converts it to serial data, and outputs it.

21 is a serial buffer that temporarily holds the serial data from the output circuits A-H (13 to 20); 22 is a serial buffer that takes in the data held in the serial buffer 21 to the mark 11ii1 head drive unit 600 under the control of the output circuit control circuit 12; 23 is a command control circuit that controls the command register 24; 24 is a command register that outputs control commands to the transmission and rotation 2825, the data inversion circuit 26, the variable circuit 27, etc.; 25 is M of the print data sent from the MPU 100 according to the instruction from the command register 24.
A transmission inversion circuit that controls inversion/non-inversion of SB and LSB;
26 is a data inversion circuit that controls inversion/non-inversion of "0" and "1" of print data from the sending inversion circuit 25 according to instructions from the command register 24.

A specific circuit diagram of the data conversion section 200 having the above configuration is shown in FIG. Components corresponding to the block diagram in FIG. 2 are indicated by the same numbers.

In FIG. 3, the latch control circuit 2, trigger circuit 3, command control circuit 23, etc. are, for example, 74LSI3 manufactured by TI.
8, latches A to H (4 to 11) are 74 manufactured by IM.
By LS374, output circuit AN)I(13-20)'
It is preferable to use 74LS151 manufactured by TI.

The output circuit control circuit 12 outputs a serial output enable signal DTE from the output circuits A-H (13 to 20) of the print head drive circuit 600 and a serial output clock signal CKO indicating data capture timing. Also,
A CO flaw signal, which is a timing signal for changing the serial output of output circuits A-H (13 to 20), is output. The CKO signal 2 is detected by the 4-bit binary counter 27 of this CO flaw signal.
As a result, the output circuit ANH
The serial output from (13 to 20) will be enlarged twice and taken into the print head drive section 600.

A detailed circuit diagram of the sending inversion circuit 25 shown in FIGS. 2 and 3 is shown in FIG.

The output inversion signal (CMO in FIG. 3), which is a control signal from the command register 24, outputs the input data signals of IO to 7 as they are as QO to Q7, or inverts the MSB% and LSB of the data. ■0-17 Q7
- You can select whether to convert to QO and output.

A detailed circuit diagram of the data inversion circuit 26 shown in FIGS. 2 and 3 is shown in FIG.

As shown in the figure, the data inversion signal (CMI in FIG. 3), which is a control signal from the command register 24, is the output data signal from the output inversion circuit 25 which is manually input.
Either output 7 as is as QO~Q7, or ■0
You can select whether to output it as ~I7.

The operation of this embodiment having the above configuration will be described below.

Prior to sending out the print data, the MPU 100' receives the CS- signal, AO signal ~A3 via the input buffer 12.
signal, WR-signal, and Do signal which is a data signal ~
The following instruction values are set in the command register 24 by the D signal.

■Setting of MSB and LSB inversion/non-inversion by the sending rotation circuit 25; ■Setting of “0” and “1” inversion/non-inversion by the data inversion circuit 26.

Next, the latch control circuit 2 is instructed to select one of the latches ANH (4 to 11) via the input buffer 1, and print data is output to the data signals DO to D7, and the CS- signal and AO to 3 are output. Write to the selected latch with the WR- and WR- signals. At this time, data signal DO is output from MPLIloo.
The print data outputted to ~D7 is subjected to MSB and LSB inversion processing by the sending inversion circuit 25, data inversion processing by the data inversion circuit 26, etc. according to the setting value set in the command register 24 in advance, and this processed data is It will be written to the latch.

This writing is performed in order from latch A4 to latch B5...latch H1l, and if necessary, write to command register 2.
The setting value for 4 is also changed. In addition, latches A-H (4~
11) can be freely rewritten.

In this embodiment, the latch has four serial output systems as shown in the figure, and each system has a configuration of 8 bits x 2.

After the MPU 100 sequentially writes the converted data to be printed to the latches ANH (4 to 11), the MPU 100 writes each latch A by the CS- signal, AO to A3 signals, and RD- signal.
- Output the print data written to H (4 to 11) to circuit A-
In order to sequentially read data from H (13 to 20), the trigger circuit 3 outputs a serial output start signal, and the output control circuit 12
Start. As a result, the output circuit control circuit 12 performs nine operations after that, and the output circuit control circuit 12 receives the serial output clock signal CKO and the serial output enable signal DTE.
Start outputting. As a result, the image is output to the print head drive unit 600 via the serial buffer 21 at a double magnification rate under the control described above.

When all the print data written to each latch as described above is sent out, the output circuit control circuit 12 outputs each output signal (CKO
, DTE, and SOO~3), and enters a standby state again in preparation for an activation instruction from the trigger circuit 3.

The enlargement process by the variable circuit 27 of this embodiment is, for example, by converting 8 bits x 2 = 16 bits configuration data to 2 times,
Although the data is converted into 2-bit data and output, the number of data to be enlarged and the enlargement magnification are not limited to these.The count-up clock from the counter 27 may be changed.

Further, in this embodiment, the operation is stopped after serial output of all data, but the operation may be stopped in the middle of output. In this embodiment, it is also possible to stop the process midway using the RES signal.

Note that the number and configuration of each signal such as the number of data, number of addresses, etc. in this embodiment is not limited to this explanation.

As explained above, according to this embodiment, conventionally the MPU10
By software calculation based on program control of 0,
Print data MSB, LSB inversion conversion processing, “0”, “
1" inversion processing can now be done entirely with eight-domain hardware, reducing the load on the MPU 100 and significantly shortening processing time, making it possible to handle higher speeds and higher density. .

In addition, the conversion from normal print data to draft print data was done by deleting the print bits that make up the print data, which was very quick, but with the automatic enlargement process, all the bits within the character size are printed out, which is very This makes it easier to see, and this also does not increase the load on the MPU 100 and does not impede higher speed and higher density.

Further, by forming the above configuration into a gate array, it is possible to provide a small and inexpensive device.

[Effects of the Invention] As described above, according to the present invention, high-speed, high-density printing output can be easily performed, and control can also be made simple.

[Brief explanation of the drawing]

1 is a schematic block diagram of an embodiment according to the present invention, FIG. 2 is a detailed block diagram of the data conversion section shown in FIG. 1, and FIG. 3 is a detailed circuit diagram of the data conversion section shown in FIG. 2. 4 is a detailed circuit diagram of the sending inversion circuit shown in FIG. 2, and FIG. 5 is a detailed circuit diagram of the data inversion circuit shown in FIG. 2. In the figure, 1... input buffer, 2... latch control circuit, 3... trigger circuit, 4-11... latch, 12...
...Output circuit control circuit, 13-20...Output circuit, 2
DESCRIPTION OF SYMBOLS 1... Serial buffer, 23... Command control circuit, 24... Command register, 25... Sending inversion circuit, 26... Data inversion circuit, 27... Variable circuit, 100... MPU , 101...ROM, 200...
...Data converter, 300...I/O interface, 400...Print buffer, 500...Recording paper transport section, 600...Print head drive section, 610-640
...Print head.

Claims (2)

[Claims] (1) Conversion means for converting the bit array of print data;
an inverting means for inverting bit on/off of print data;
A holding means for holding parallel print data, a reading means for reading out the parallel print data held by the holding means, and an output for converting the parallel print data read by the reading means into serial data enlarged by a predetermined magnification. A printing device comprising: means. (2) The printing apparatus according to claim 1, wherein the converting means inverts the bit arrangement so that the most significant bit of the print data becomes the least significant bit and the least significant bit becomes the most significant bit.