JPH01278177A - Equipment and method for data re-reading restoration of run-length limiting code - Google Patents

Abstract

PURPOSE: To recover an information pulse with high precision by recovering data by means of a high-resolution channel except for a case when the high resolution channel is inhibited during a transition loss period. CONSTITUTION: An amplifier 10 which waits an input from a converter 12 for reading a magnetic signal recorded in a medium 14 is included, and the amplifier 10 supplies an output to both a low-resolution filter 16 and a high-resolution filter 18, in reponse to the change of the recorded signal. It is detected, here that transition does not occur for a long period by a low-resolution channel, and since the high-resolution channel detects an alias signal so as to correctly inhibit response to it, so that the low-resolution channel can be designed so as to respond to a low-frequency within the frequency range of the data signal. Thus, inaccuracy in a pulse position caused by the low-resolution channel is removed, and also the spurious signal inside the-high resolution channel is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data recovery (regeneration) apparatus, and in particular to a run length limited code recovery (regeneration) apparatus and method.

May 14, 1985 V, B, Hinub
U.S. Pat. The high-resolution signals processed by are characterized by accurate recovery of pulses representing digital information, but are also characterized by a high probability of containing spurious pulses that do not represent digital information.
Spurious pulses can be generated by noise.

A low resolution channel, on the other hand, processes a low resolution signal characterized by a lack of spurious pulses, but which is relatively imprecise as to the location of the pulses representing the data. As described in the aforementioned Patent No. 4.517.61, the recorded signal to be recovered is processed in parallel through the low and high resolution channels, and the results of each Bouyanel are processed logically, Eliminates pulse position uncertainties caused by low resolution channels and eliminates spurious signals in high resolution channels. The result is a high degree of recovery of the information pulse.

In the MFM code, also known as the (1,3) code,
At least one binary zero between consecutive binary ones and a maximum of three
There are two binary zeros. In a (2,7) code, there are a minimum of two binary zeros and a maximum of seven binary zeros between consecutive binary ones.

Since recording transitions occur only for binary ones, MFM
It has been shown that the ratio of "high" to "low" recording frequency elements in the code is on the order of 2:1.
The recording frequency for the lowest number of zeros between two is twice the recording frequency for the highest number of zeros between consecutive ones. (For the 2,7 code, the ratio of "high" to "low" frequencies is on the order of 2.67:1.

<1.7) The run-length limited code has a large detection window (
This is a very important point in readback recovery equipment)
It is extremely popular due to its advantages. H,Coh
U.S. Patent No. 4.337, June 29, 1982, to n.W.
．． See No. 458.

Also, v8゜Hinub entrusted to the same assignee as this application.
No. 116., filed Nov. 5, 1987, by In.
See also No. 989. The (1,7) code is characterized by having a minimum of one binary zero and a maximum of seven binary zeros between consecutive ones. However, (1
,7) code is the fact that the ratio of ``high'' to ``low'' frequencies is on the order of 4:10, which compared to MFM and (2,7) codes Extremely high.

One problem with implementing the dual channel recovery device described in the aforementioned patent No. 4.517.6104 for (1,7) code recovery is that the low-resolution filter does not allow successive recording transitions within the code pattern. It must exhibit very low resolution frequencies separated by seven static clock periods corresponding to the seven zeros of . Low resolution is required to keep the output removed from the zero line. Furthermore, a low-resolution filter must have sufficiently high resolution to produce all true zero crossings for code patterns that have exactly one zero between successive ones. Furthermore, the decomposition must be done with acceptable levels of inter-symbol interference and signal-to-noise ratio. For high-density recording, the conflict between "high- and "low" resolution requirements for low-resolution filters cannot be resolved satisfactorily for (1,7) codes.

Run length tIl with long intervals between consecutive transitions
It is an object of the present invention to provide a technique for the recovery of run-length limited codes, including J-limited codes.

(1, 7) It is an object of the present invention to provide a method and device for code recovery, in which a low resolution filter can be configured with lower resolution. ,be.

According to the invention, the high-resolution channel operates during periods with relatively few consecutive zeros (no transitions) of data to be recovered. The low resolution channel contains a detection device for detecting a fixed number of consecutive M (no transitions occur). The detector operates a latch within the high resolution channel. When the low resolution channel detects a certain number of consecutive zeros, the latches in the high resolution channel are deenergized, thereby preventing spurious pulse recovery. When the low resolution channel again detects a transition (indicating a binary 1), the latch in the high resolution channel is set to 1 by the exact high resolution channel.
Work to make recovery possible.

One feature of the invention is to ensure that an IF transition in the low resolution channel sets a latch in the high resolution channel before the time that the transition triggers an output from the high resolution channel. i for both high and low resolution 1 layer
It's all about making choices.

Another feature of the invention is that data recovery (regeneration) is performed by the high-resolution channel A7, except when the high-resolution channel is disabled during the in-transition deletion period (long string of zeros). There is a particular thing.

Another feature of the invention is that the low-resolution filter can be set so low that the detector detects missing transitions (successive zeros) beyond the step limit;
The purpose is to prohibit the high-resolution Boolean channel from producing outputs based on spurious signals.

These and other features of the invention will be more fully understood from the following detailed description and accompanying drawings.

The drawings, and in particular FIG. 1, depict a dual channel read recovery device consistent with a preferred embodiment of the present invention. This device consists of a transducer 12 (
This includes an amplifier 10 having an input from a magnetic read head (which may be a magnetic read head). Amplifier 10 provides output to both low resolution filter 16 and high resolution filter 18 in response to changes in the recorded signal. The low resolution filter 16 is designed for the low frequency region of the frequency range of the (1.7) code used. The low resolution filter provides an output (waveform C in FIG. 2) to a zero-crossing detector 20,
is output to the edge pulse generator 22 (waveform d in Figure 2)
is supplied. The edge pulse generator 22 includes a delay circuit 24
supply the output to. The delay circuit 24 is connected to the pulse former 22
A total of four clock periods are applied to delay the signals received from the AND gate 26. Aien circuit 24
also provides a delayed signal from the center (waveform e in FIG. 2), which is input from the edge pulse former 22
Only the clock cycle has been delayed. Waveform e of FIG. 2 is provided to the override set input of a D-type flip-flop 28, and the D input of flip-flop 28 is coupled to a low voltage source. The Q output of flip-flop 28 is provided to the second input of AND gate 26. AND
Gate 26 provides a signal output, shown as waveform f in FIG. 2, to the clock input of D-type flip-flop 30. D-type flip-flop 30 has its D input connected to a low voltage source. The set input of flip-flop 3o is connected to receive waveform e shown in FIG. The Q output of flip-flop 30 is shown as waveform q in FIG. 2 and is provided to latch 32.

In the high resolution channel, the output of high resolution filter 18 is shown as the waveform of FIG.
Detector 34 provides an output shown as waveform 1 in FIG. 2 to delay 36.

Delay 36 is connected to waveform i as shown in waveform j of FIG.
Delays the signal shown by three clock cycles.

Latch 32 is responsive to the signals shown in waveforms q and j in FIG. 2 to provide an output shown in waveform 1 in FIG. put out. Latch 32 is conditioned by the high input of waveform q to provide an output of waveform j in response to the edges of the pulses of waveform j.

The operation of the apparatus shown in FIG. 1 will be explained with reference to FIG. Waveform a in FIG. 2 represents a string of binary digits, each pulse representing a binary 1.

Each pulse is shown as having a positive rising edge centered below the clock period. The particular binary pattern shown in waveform a shows both the high frequency (R fractional zeros) and low frequency (maximum number of zeros) of the (1,7> code. Thus, waveform a shows the binary bit 10101010100
Contains 0000010 and is /υ. The waveform shows the signal provided by amplifier 1o, which varies analogously between positive and negative peaks. A low resolution filter 16 responds to the waveform C by providing a signal shown in waveform C, and directly converts the peaks of the waveform C into zero crossings. however,
The zero crossing of waveform C does not perfectly coincide with the peak of waveform A (which indicates the center of transition of waveform a). As you can see, the low-resolution channel is tracking the signal accurately (it's not a bummer. Another thing to note is that waveform C does not contain any spurious signals due to noise, etc.). Detector 20 provides waveform d in response to zero crossings of waveform C, and waveform d is provided to edge pulse former 22, which responds with a short pulse to each edge of waveform d. 22 supplies a pulse signal to the override cell 1-manpower of the flip-flop 28, and the AND gate 26
emasculate. Delay circuit 24 provides a first delayed signal to the clock input of flip-flop 28.

The first delayed signal t, represented by waveform e, is an exact copy of the output of edge pulse former 22, but delayed in time by two clock cycles. Thus, consecutive edges in waveform d become distinct pulses in waveform e. However, due to the spacing, the end of pulse 50 in waveform d does not generate a new pulse in waveform e. Thus, instead of the four pulses corresponding to the four ones shown in waveform a, only three pulses are sent to pulse former 2.
Generated by 2.

Delay circuit 24 operates to set the Q output of 7-rip 70-tube 30 to "high" in two clock cycles 2F following the output of edge pulse former 22, providing a high waveform Q output. At the same time, the pulse on waveform e toggles flip 70 knob 28, forcing the buy output of flip-flop 28 to F high 1, thereby providing an energizing input to AND gate 26. However, if another pulse from pulse edge former 22 is received by the override set input of flip-flop 28, the Q output of normed flop 28 is forced low and the (j Remove input.

However, if the input pulse does not operate to set flip-flop 28, then flip-flop 28
The Q output of is further delayed by two clock cycles, and the second delayed signal output is directly ANDed from the delay circuit 24.
It remains "high" until it is transmitted to gate 26. Now AN
Since the meat input of D goo i~26 is "high", AND gate 26 supplies the pulse shown in waveform f of FIG. Toggle the Tsubu's Q output to 1 low.

Therefore, it is clear that unless the zeros of four consecutive clock cycles occur, the A
2 forms a pulse 54 of waveform f, thereby causing waveform 0
is caused to go "low" as shown at end 56.

The waveform signal from the amplifier 10 is passed through the high-resolution filter 1
8, which is shown by the waveform in FIG. The waveform signal is characterized in that its peak is located at the exact position of the zero crossing of the waveform, but this signal is also characterized in that it contains false signals due to noise and the like. The false signal forms crossovers and peaks like 58 in the waveform. The waveform signal is provided to a zero-crossing detector 34 which forms a pulse edge for each zero crossing of the waveform signal. Thus, the signal of waveform i is characterized by having a pulse edge at the zero crossing of the waveform that coincides with the binary 1 shown in waveform a, and also has another pulse edge formed by the false signal 58 of the waveform. It is also characterized by having a zero crossover 62.

The delay circuit 36 delays the signal of waveform i by a cycle shorter than the entire delay cycle of the delay circuit 24. For present purposes, the delay in delay circuit 36 is preferably such that signal i is delayed by three clock cycles to form a signal of waveform j.

The signal of waveform j is supplied to the latch circuit 32 as an input. Latch 32 is responsive to the pulse edge of the waveform j signal to issue the same pulse edge on the output waveform k when the energization signal of waveform q is "high." As shown at 66 in waveform Q, when the energizing signal of waveform q is [low-1, the latch 32 does not respond to the pulse edge of waveform j.

As a result, the "low" level of waveform q occurs only during long consecutive zero periods, so that a spurious signal is present in the high-resolution channel, whereas the "low" level of waveform 9 is an artifact of waveform j. The signal 64 is masked to create a waveform k. Pulse edge shaper 38 responds to the edges of the pulses in the signal waveform to form the signal in the waveform and reproduce the binary signal of waveform a.

The present invention thus provides a readback recovery system such that when one channel detects that a transition has not occurred for a long time, the other channel is properly inhibited from detecting and responding to the false signal. provide. As a result, the low resolution channel may be designed to be responsive to low frequencies in the frequency range of the data signal.

Although the invention has been described in connection with detecting strings of four or more zeros (no transitions), of course the circuit can be used simply by adjusting the lengths of delays 24 and 36. It can be adjusted to respond to any desired number of zeros. Preferably, the delay of delay circuit 36 is somewhat shorter, such as one clock cycle less than the total delay of delay circuit 24. In this regard, both channels are delayed and the detection circuit latches the two channels. However, for a (1,7) code, false signals typically occupy no more than about 4 clock cycles; In the case of consecutive zeros, it typically begins during the third cycle of consecutive zeros and ends during the sixth cycle of consecutive zeros. Therefore, signal q is It is important that the Utilizing the delay shown in 1m of water results in adequate signal resolution despite normal pulse drift and data recovery inaccuracies as reflected in the waveform signal. Due to the three clock cycle delay in the high resolution channel created by delay circuit 36, false signal 64 typically lasts until approximately five clock cycles (in absolute time) following transition 6o of waveform i or transition 52 of waveform d. does not appear. Since waveform 0 goes "low" about five absolute clocks after such a transition, the spurious signal is effectively canceled by disabling the high resolution channel during this period. In this way, it is possible to recover the signal even for a signal such as a (1,7) code in which no transition occurs for a long time.

The invention is not limited to the embodiments shown in the drawings and described in the specification, which are given by way of example and not by way of limitation and are limited only in accordance with the claims. It is something that

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a dual channel read recovery device according to the presently preferred embodiment of the present invention. FIG. 2 is a waveform diagram at each point in the circuit of FIG. 1, which is useful for explaining the operation of the device shown in FIG. (Explanation of symbols) 16...Low resolution filter, 18...High resolution filter, 20.34...Zero crossing detector, 22.38...
・Edge pulse former, 24.36...Delay circuit, 3
2...Latch.

Claims (14)

[Claims] (1) A device for recovering (reproducing) digital information in a run-length limited code, the device receiving a read signal and generating a high-resolution pulse signal representing the digital information contained in the read signal. a high-resolution recovery device; an output device for generating an output pulse signal representative of digital information contained in the read signal in response to the high-resolution pulse signal; and an output device for receiving the read signal; a low-resolution recovery device for generating a low-resolution pulse signal representative of digital information contained in a read signal; and, in response to said low-resolution pulse signal, detecting a lack of a period of transition in said low-resolution pulse signal. The device as described above, comprising: a detection device for detecting removal; and a de-energizing device for de-energizing the output device in response to the detecting device. 2. The apparatus of claim 1, wherein the detection device includes a delay device for generating a delayed low resolution pulse signal in response to the low resolution recovery device; and a delayed low resolution pulse signal. including a gating device responsive to a pulse signal and an undelayed low resolution pulse signal for generating an ablation signal with the absence of a pulse of said period of time in said low resolution signal; The above device characterized in that: (3) The apparatus according to claim 2, wherein the delay device includes a first delay circuit for delaying the low-resolution pulse signal for a first period corresponding to the certain period; a second delay circuit for delaying said low-resolution pulse signal for a second period shorter than one period;
The device as described above, wherein the gating device includes a latch device for generating a latch signal in response to the second delay circuit and the undelayed low resolution pulse signal. (4) The device according to claim 3, wherein the gate device further includes an AND gate for generating a gate signal in response to the latch device and the first delay circuit; and an energizing device for generating a disenergizing signal in response to the AND gate and generating an energizing signal in response to a low resolution pulse signal from the low resolution recovery device. Said device. (5) The device according to claim 4, wherein the energizing device supplies the high-resolution pulse signal to the output device in response to the energizing signal, and in response to the energizing signal. and a second latching device for blocking said high-resolution pulse signal from being applied to said output device. (6) The device according to claim 5, further comprising a second delay device for delaying the high-resolution pulse signal. (7) The device of claim 2, wherein the gating device provides an energizing signal in response to the low resolution pulse signal and a deenergizing signal in response to the delayed low resolution pulse signal. A device as described above, characterized in that it contains a biasing device for supplying. (8) The device according to claim 7, wherein the energizing device supplies the high-resolution pulse signal to the output device in response to the energizing signal, and in response to the energizing signal. and a second latching device for blocking said high-resolution pulse signal from being applied to said output device. (9) The device according to claim 8, further comprising a second delay device for delaying the high-resolution pulse signal. (10) The device of claim 2, wherein the neutralization device is responsive to the detection device to prevent the high-resolution pulse signal from being supplied to the output device. A device as described above, characterized in that it contains two latching devices. (11) The device according to claim 10, further comprising a second delay device for delaying the high-resolution pulse signal. (12) A method for recovering digital information in a run-length limited code, comprising: generating a high-resolution pulse signal representing said digital information; and recovering digital information from said high-resolution pulse signal. generating a low-resolution pulse signal representing digital information; detecting the absence of a period of transition in said low-resolution pulse signal; and detecting a period height corresponding to the detected period of time. and eliminating recovery of digital information from the resolution pulse signal. (13) The method of claim 12, wherein detecting a lack of a pulse of a certain period in the low-resolution pulse signal comprises:
Delaying the low-resolution pulse signal by a predetermined period of time, and determining from the delayed low-resolution pulse signal and the non-delayed low-resolution pulse signal whether a pulse occurs within the low-resolution pulse signal of the predetermined period. The method as described above, characterized in that it is achieved by. (14) The method according to claim 13, further comprising the step of delaying the high-resolution pulse signal by a second fixed period shorter than the first fixed period.