JPH01277988A - Character recognizing device - Google Patents

Abstract

PURPOSE:To improve the identification(D) ratio of a specific character by selecting a 1st candidate character by rough sort processing when a segmented input character is a normal character, executing fine sort processing, and when the character is a specific character, selecting a 2nd candidate character and executing fine sort processing. CONSTITUTION:When an input character segmented based upon a parameter feature is a normal character, a character segmenting circuit 11A1 in an I/O processing circuit body 11A transfers the image information of the segmented input character to a rough sort processing circuit 12A through an output processing circuit 11B and executes the pipeline processing of the normal character as a character ID part 4. At the time of deciding a specific character code, the circuit 11A reads out the specific character code having the extracted parameter feature from a specific rough sort dictionary 11A2 and transfers the code to the circuit 12A as the input character information through an output circuit 11B. Thus, the ID ratio of the specific character can be improved.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Outline of the invention C. Conventional technology Problems to be solved by the invention 2701 Means for solving the problem (Figs. 10 and 12)
Figures and Figures 13) F action (Figures 1θ, Figures 12 and 13) G embodiment [G1] Principle configuration of character recognition device (Gl-1) Overall configuration (Figures 1 and 2) (Gl-2)
Major classification identification processing (Figs. 1, 3, and 4) (Gl-3) Subclass identification processing (Fig. 1, 5 to 9) [G2] Pipeline, parallel processing (Fig. 1 , FIG. 2, FIG. 8, FIG. 10, and FIG. 11) [G3] Character extraction processing circuit (FIG. 1, FIG. 3, FIG. 4, FIG. 10, FIG. 12, and FIG. 13) (G3-1) Extraction of character parameters (Figures 1, 10, and 12) (G3-2) Selection of special character candidates (Figure 1, Figure 1O,
and Fig. 13) [G4] Major classification processing circuit 12A (Fig. 1, Fig. 3, Fig. 4)
, FIG. 10, FIG. 14 to FIG.
(G5-3) Input cover turnset circuit 13D (Figs. 10, 17 to 20) (G5-4) Stroke extraction circuit 33 (Figs. 7, 19 to 20) 22) (G5-5) Pattern matching circuit section 41 (FIGS. 7, 18, 21, and 23) (G5-6) Residual calculation circuit section 45 (FIGS. 19 and 24)
(G5-7) Effects (Figures 1 to 24) [G6] Other Examples H Effects of the Invention A Industrial Application Field The present invention relates to a character recognition device, particularly when recognizing printed characters. It is suitable for application.

B. Summary of the Invention The present invention allows a character recognition device to select candidate characters based on the parameter characteristics of cut-out input characters, thereby further increasing the recognition rate for special characters.

C. Conventional technology In the past, it has been proposed to digitize and file a large amount of printed documents, or create a database to build an information network that can be used for a variety of purposes. Instead of character information input devices that require input operations, it has been considered to use character recognition devices that do not require manual input operations.

Incidentally, a printed character recognition device optically reads the printed characters on a printed document, digitizes them as two-dimensional image information, extracts the printed characters from the image information, and outputs the corresponding character code. It is made to be.

By encoding image information into character codes in this way, you can search for words using a computer,
It is possible to realize a document processing system that automatically executes decoding processing such as understanding meaning.

In this way, for example, it is possible to compress the data extracted from the image information and use it for decoding processing as necessary, thereby making it possible to improve the document processing speed as necessary.

Problems to be solved by the invention However, the currently used printed kanji recognition devices actually have a recognition rate of about 97 to 99% and a recognition speed of 20 to 99%.
It only has a function of about 30 characters/second, and is still insufficient as an input means for digitizing a large amount of printed documents.

To solve this problem, conventional large classification processing has been used to detect feature amounts based on the characteristics of human characters extracted from image information (for example, peripheral features on four sides) and select candidate characters from a large classification dictionary. The most similar character is determined by executing subclassification processing based on pattern matching on the candidate character. 'R1 method has been proposed (Japanese Unexamined Patent Publication No. 62-186
Publication No. 390).

It has been confirmed that this hierarchical character recognition method has the advantage of further increasing the recognition rate when identifying characters without special features in shape, position, etc. (that is, normal characters).

However, for characters with special characteristics such as horizontally long characters, vertically long characters, small characters, etc. (i.e. special characters) in character position, size, aspect ratio, etc. However, there is a problem that the identification rate cannot be increased as a whole.

The present invention has been made in consideration of the above points, and aims to propose a character recognition device that increases the recognition rate for special characters while effectively utilizing the features of the hierarchical character recognition method. .

E Means for Solving Problems In order to solve these problems, the present invention provides the tenth solution.
As shown in Figures 12 and 13, the image information Ii
! The input character MOJ+ is cut out from INF, and the character parameter D of the cut out human-powered character MOJI. 1
1 to parameter special 1tIlWRT, HCNT, HRT
and extract these parameter features WRT, HCNT, HR
When the human-powered character MOJI cut out based on T is a normal character, after selecting the first candidate character by the major classification process based on the image information ITNF of the cut out input character MOJI, the candidate of the cylinder 1 is selected. Execute subclassification processing for characters and use parameter features WRT, HCNT, H
When an input character MOJI cut out based on RT is a special character, a second candidate character is selected, and a subclassification process is executed for the second candidate character without executing a major classification process.

F-effect vertically long characters, horizontally long characters, small characters, etc. have special features that normal characters do not have in parameters such as position and aspect ratio.

Focusing on this point, in the present invention, by extracting the parameter features WRT, HCNT, and HRT of the input character MOJI, the parameter features WRT, HCNT, and HR
The second candidate character for the special character with T is selected and the subclassification process is immediately started.

By doing so, the identification rate of special characters can be further increased.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

[G1] Principle configuration of character recognition device (Gl-1) Overall configuration In Fig. 2, 1 indicates the character recognition device as a whole,
The image scanner section 2 optically reads the supplied printed document 3 automatically or manually and provides two-dimensional image information INF to the character identification section 4 .

The character identification unit 4 identifies characters included in the image information INF and sends out character identification output data DATA, which is supplied to a host computer of a document processing system, for example, and also supplies display data DIsp to a display device 5. do.

As shown in FIG. 1, the character identification section 4 receives the image information INF supplied from the image scanner section 2, and distinguishes between normal characters of normal size and shape (in contrast, small characters, horizontally long characters, etc.). Characters such as vertically long characters are called special characters)
Selecting similar characters having the same characteristic parts as the input characters as candidate characters from the characters to be identified stored in the major classification dictionary by performing a major classification process on the candidate characters, and then performing a subclassification process on the candidate characters. determines the closest character. Thus, the character identification section 4
Highly accurate character recognition can be achieved by executing hierarchical classification processing consisting of major classification processing and subclassification processing.

That is, the character identification section 4 receives the image information INF at the input/output processing section 11 . The input/output processing section 11 has a central processing unit (CP tJ), cuts out input characters to be subjected to identification processing from the image information INF, and transfers them to the large classification processing circuit 12A of the large classification identification section 12 and the subclassification processing circuit 12A. Part 13
It is sent to the normalization processing circuit 13A.

(Gl-2) Major classification identification process As shown in FIGS. 3 and 4, the major classification identification unit 12 selects the left and right sides (this (referred to as side A and side B)
WAKUA and WAKU.

The first and second peripheral features viewed from the side, the upper side and the upper side (these are referred to as the 0 side and the D side) WAKU,:
Based on the third and fourth peripheral features seen from W A K U o, a feature amount (expressed as a vector amount) DCHll is generated by encoding the character structure created by the black character portion against a white background. And this feature amount D C
Candidate characters consisting of similar characters are selected based on H*.

Note that Japanese Patent Laid-Open Publication No. 186390/1984 describes a method of character recognition based on peripheral characteristics.

The peripheral feature on the A side is the black character part on the left side of the dot line LA when the black character part of the third dot line along the left side MOJIA of the input character MOJI is viewed from the direction indicated by arrow AR8. The lengths ds, ds, dsz of
Forms cH*.

In the case of Fig. 4, the length C of the scanning start part at the upper left corner of the left character part MOJIA (this is called the start corner)
A fairly long 1 can represent that there is no dot in the upper left corner.

On the other hand, since the length C0 of the lower left corner at the end of scanning (this is called the end corner) is short, it can be expressed that there is a dot force at the end corner.

In the case of this example, the length CS of the start corner is as follows: Bo=rlJ (2
), set the data B0 of the Oth bit of 1fifiocH* to logic "1", and when the condition of (1) 2 does not hold, BO=rOJ... (3)
The data B0 of the Oth bit is set to logic "0" as shown in FIG.

Regarding the length C8 of the end corner, when the following condition is satisfied, the data B of the first bit of the characteristic f & fit D cm is expressed as shown in the following equation (5).

is set to logic "1", and when the condition of equation (4) does not hold, B, = rOJ... (6)
Set.

Start corner length C3 and end corner length C0
In the section between, the length of the black character part is ds,,d 5t
=d s, (n-3 in the case of Figure 4) occurs, but when the lengths of each black character ds, , dsz...ds, satisfy the condition ``°'''''' 1 2nd, 3rd... Data Bz, B:+...B IIO+ of the (n+1)th dot is set to logic "0" as in Set logic "1" as if the condition does not hold.

Thus, the characteristics of the start corner and end corner are incorporated into the data B0 and B of one 0th and 1st bit (feature value DC), and the characteristics of the 2nd, 3rd...1R
(n+1) bit data Bt, Bs...B7
．． 1, information representing the arrangement order of dots and segments is taken in as the arrangement state of the black character portion.

In this way, all the features of the black character part on the A side are encoded, and the (n+2)th bit following the last bit is set to logic "1" data as shown in the following equation (10).

In this way, the peripheral feature on the A side is converted to the feature quantity Dell+ coded as a variable length code, where □ represents first-order (i=n+2) vector data, and the following formula % The feature quantity numerical data VAL in decimal number is determined by the conversion formula of the formula %.

, convert to This feature quantity numerical data VALDcm is stored in the standard character feature quantity DcH in the major classification dictionary 12B (Fig. 1).
By storing this as information representing the character MOJI and reading it as necessary and comparing it with the special value numerical data VALocm for the input character MOJI, the candidate character information SCAD representing similar characters is generated by the major classification processing circuit 12A.
The information is sent to the subclassification identification section 13 from there.

In this embodiment, the major classification processing circuit 12A has a special function ff11.
The order i of a 1cm vector is l≧7 (12)
When the upper limit value is 7 or more, as in
By classifying the input characters into numerical data 12B as shown in (13), the input characters are processed as characters belonging to a "complex pattern" (instead of selecting candidate characters for each character).

The major classification dictionary 12B receives input character information SI from the input/output processing unit 11 by reading standard printed characters (normal characters) to be identified character by character using the image scanner unit 2.
After obtaining N, in the major classification processing circuit 12A, (11
) and (13), the feature quantity numerical data V A
LIIcMII is calculated for each side A to D and registered together with the character code.

In this way, for all the characters to be identified (for example, 4000 characters), the standard character codes that have common peripheral features for each side A to D are the feature value numerical data V A L
The information is roughly classified by Dell and stored in advance in the major classification dictionary 13B.

In this state, when the input character information SIN arrives at the major classification processing circuit 12A via the input/output processing section 11 by reading a document with the image scanner section 2, the major classification processing circuit 12A inputs the feature value numerical value of the input character information S0. Obtain the data VALoc, l* and calculate the corresponding feature value numerical data V
The candidate character codes having ALoe□ are extracted from the major classification dictionary 12B for each side A to D, and the standard character codes that have become candidate characters for all sides A to D are set as candidate character information ScAゎ by the subclassification identification unit 13. Send to.

The character information drawn from the major classification dictionary 12B here is
Each side of A to D is a union of characters having the same feature value DC□, and the major classification processing circuit 12A calculates the candidate character code represented by the common term (i.e., the intersection set) of all the unions of the respective sides. is sent as candidate character information ScAゎ.

This means that instead of checking whether all of the features of each side of the input character exactly match the features of the target character, there is a match of one or more peripheral features for each of the four sides. By checking whether the candidate characters are the same or not, candidate characters can be narrowed down with sufficient accuracy for practical use through a relatively simple and short-time broad classification identification operation. According to experiments, on average 24.04 out of 4000 characters
This makes it possible to select candidate characters, thereby making it possible to perform the classification process in the subclassification identification section 13 much more easily and in a shorter time in practical terms.

Incidentally, as actual examples of candidate characters for input characters, the following candidate characters can be selected.

[Example 1] Two candidate characters, ``in-misaki'', were selected for the input character ``in''.

[Example 2] For the input character ``print'', 12 candidate characters, ``Old evil silk tea printing system rule Taibetsume Yorou'' were selected.

[Example 3] For the input character "Bun", 60 candidate characters "Aamei Ei Eno Okuhi Kankan Takamoxibustion Exploration Secrecy dog test ``Zhongzang Food Responsibility First Tai Tai Dai Mu Bi Biao Table of Duty Wu Wenpei Takaya Friendship Roku'' was selected.

[Example 4] 57 candidate characters for the human-powered character ``character'', ``Anyuon Harumaki Yokogyu Kyoukoka Takakosa Zaisakusa Sanshikari City Jiji Temple Kisa Hemorrhoids Kuruma Moriharu Shosho'' I was able to select ``Jinsen graduate, a ruthless Tei-teiku Donneibanbei ≠ Fuben yankou mokumoku yōratsu lengyo''.

(Gl-3) Subclassification Identification Process The subclassification identification unit 13 (FIG. 1) receives input character information S + about normal characters input from the input/output processing unit 11.
N is the candidate character sent out from the major classification identification unit 12.
. By performing a pattern matching process on the candidate character represented by AD, a process is executed to select a candidate character most similar to the input character from among the candidate characters selected in the major classification process.

In this subclassification process, first, the input character information SI is passed from the input/output processing unit 11 to the normalization processing circuit 13A.
N is converted into an input character pattern PT, which is a character pattern composed of 24 x 24 dots, as shown in Fig. 5, and this input character pattern PTIN is similarly converted into 24 x 24 dots, as shown in Fig. 6. Pattern matching is performed by performing matching processing with the standard character pattern PT, which is composed of a 24-dot character pattern.

In the case of this embodiment, input cover pattern data I) pt consists of dot data of an input character pattern normalized by the normalization processing circuit 13A. Input 8 cover turnset circuit 1
Standard pattern data D, which is set to 3D and represents the dot arrangement of the standard character pattern PTsr for the character to be identified. A is stored in advance in the subclassification dictionary 13C, and read out character by character by candidate character information SCAD and set in the standard pattern setting circuit 13B.

The standard pattern and human cover turn data Drtst and D□1N thus set in the standard pattern set circuit 13B and the input cover turns set circuit 13D are processed in the subclassification processing circuit 13E as shown in FIGS. 5 and 6. They are sequentially read out while scanning in the X direction (that is, the horizontal direction), and are processed to align the strokes (consisting of an array of black dots) in the X direction (first alignment process), and the strokes in the Y direction are (that is, in the vertical direction), the strokes are aligned in the Y direction (second alignment process).

For each scanning line in the X direction and the Y direction, for example, as shown in FIG.
7. Input pattern data D with PT 3...
N is set in the input cover turn set circuit 13D, and standard pattern data I) r having a standard character pattern PT, strokes PT, A+, PTsv□ as A)
When tst is set in the standard pattern set circuit 13B, the stroke P TI of the input character pattern PT, .
The starting point coordinate Is and the ending point coordinate Is for N+, P Tiz, PTIH3! , and its width WaS and center coordinate Is.

seek. Along with this, the subclassification processing circuit 13E calculates the strokes PTsv+, PTs of the standard character pattern PTs〒.
Similarly for tz, the stroke start point coordinates RS I
and detect the end point position ja RS t, and its stroke width W. and find the center coordinate R3O.

Based on the calculation results, the subclassification processing circuit 13E classifies each stroke PT'IN+ of the input character pattern PTIN.
, PTIN□, PTIN3 stroke width Wl! and the center value ISo, respectively, are sequentially converted into standard character patterns PT1.
The stroke width WaS and center value R3 of the stroke PTst+ and p'rsa2 are compared, and the deviation thereof is determined to be a predetermined stroke width threshold level W? A matching process is executed in which it is determined that the strokes are matched when the strokes are within the range of M and the center value threshold level CTj1.

In this embodiment, the subclassification processing circuit 13B is configured to perform such matching processing according to the processing procedure shown in FIG.

For example, when the input character information SIN representing the character "book" is input as the human character pattern PTIN, the major classification identification unit 12 selects two characters "" as the candidate character axis 5cAD.
When the standard character patterns PTsta and PTstm representing "book" and "tree" are input, the subclassification processing circuit 13B uses the input character pattern PTIN and the standard character pattern PTs.
After reading ya and PTiym, firstly, a process is performed to match the input character pattern PTIN with reference to the standard character patterns PTitA and PTsrm, and secondly, a process is performed to match the input character pattern PTIN with the input character pattern PT, □. Processing to match patterns PT3TA and PTstm is executed.

That is, first, the subclassification processing circuit 13E determines that strokes that are consistent with the written standard character patterns PTsya and PTsym are input character patterns P T I N
If there is, the data of the matched stroke is deleted from the data of standard character patterns PTsta and PTstm, and the remaining standard character patterns PTs are deleted.
Standard pattern reference X-direction erasure pattern ERIIIA 1ERX1 consisting of the stroke portion of ta, P Tstm
Get 1.

Second, among the human character patterns PT+H taken into the subclassification processing circuit 13H, the standard character pattern P Ts
By erasing strokes that are consistent with tA, P Tstm, an input cover turn reference X-direction erasure pattern ERxtm SERxtm is obtained.

In addition, the subclassification processing circuit 13E similarly converts the input character pattern PTIN into the standard character pattern PT regarding the rotated cover turn PTIMY which is rotated 90'' counterclockwise.
Similarly, two-step matching processing is performed on rotated standard patterns P'rst□ and PTitmv, which are obtained by rotating svA and PTsta by 90' counterclockwise.

In this embodiment, the rotating standard patterns PTstAv and PTstmy are the standard character patterns p'rita and PTstmy.
o, and is stored in advance in the subclassification dictionary 13C.

In this way, in the same way as the alignment process in the X direction, the rotation input cover turn P is
Standard pattern reference X direction erased patterns ERVIA and ERy+++ obtained by erasing T+Ny and input cover turn reference Y direction erased patterns Eryza and ERvtm are obtained by erasing rotation reference patterns PTsta and p73y+y from the rotation input cover turn PTINV.

Thus, the four X-direction erasure patterns E RXIA-E obtained as a result of the matching process in the X-direction and the X-direction
Rx+m 1E Rxta , E Rxzs and Y direction erasure pattern B Rv+a −E Rv+m , E
By calculating the AND with RVtA 1ERytm, the subclassification processing circuit 13E generates four corresponding residual patterns E Rv+a , E Rt+i , E RyzAlE
Find R□.

Here, the X direction erasure patterns E RXIA , E Rx+
m, ERxta, ERxta and Y direction erase pattern ERv+a, ERv+*, ERvtA,, ERvt
Since m represents the stroke portion where alignment could not be achieved when scanning in the X direction and the This represents the part of the stroke that could not be removed, and in the end, the residual pattern E
RTIA, E Rt+++, E Rtza, ERt
zi represents the number and position of dots that do not match between the input character pattern P T + , 4 and the standard character patterns PTSTA and PTsym.

The subclassification processing circuit 13E processes the residual patterns B RT I A and ER□1, E R obtained in this way for the standard character patterns PT, A, and PTSTm, respectively.
t + * and ER? The determination processing unit 14 calculates the sum of the number of dots of 2m and uses the calculation result as residual data Dol+ representing the pattern matching result between the input character pattern PT, , and the standard character patterns PTSTA and PT, □.
(Figure 1).

The determination processing unit 14 uses the residual data D! , the numerical value represented by I,
Evaluate the score obtained for each candidate character as a result of the subclassification process,
The results are ordered from 1st to 5th in descending order and sent as determination result data 5llE3.

In this embodiment, the input/output processing unit 11 displays the judgment result data S*tS for the first recognized character on the display device 5 so that the operator can visually confirm the first recognized character. When the recognized characters are not appropriate,
It is possible to use characters recognized in the second place or lower. In practice, this almost eliminates misrecognition.

By thus obtaining the residual pattern based on the AND result of the erasure patterns in the X direction and the X direction, the input character pattern PT and the standard character Even if there is a phase variation between the pattern PTst or a line width variation between the input character pattern PTIN and the standard character patterns PT and T as shown in FIG. 9(B), Pattern matching processing can be performed with high practical accuracy while absorbing influences.

[G2] Pipeline, parallel processing Based on the above-mentioned principle configuration, the character recognition unit 4 (Fig.
FIG. 2) is from the character extraction process of the input/output processing section
Major classification processing in the major classification identification unit 12, detailed classification identification unit 1
Normalization processing and subclassification processing in 3, determination processing unit 14
The configuration is such that image information INF can be processed at high speed by processing the determination process in a pipeline and parallel processing.

That is, the character identification unit 4 performs character extraction processing, major classification processing, standard pattern set processing, normalization processing, and input cover turns set processing, as shown in FIG. , subclassification processing, and determination processing are configured in a hierarchical structure so that pipeline processing can be performed.

That is, the input/output processing section 11 has an input/output processing circuit main body 11A having a CPU configured as a microcomputer, and by latching the character extraction information 11INX to the output circuits 11B and 11C having a dual port register configuration, the main classification processing circuit 11A has a CPU configured as a microcomputer. 12A and normalization processing circuit 13A.

In this way, as shown in FIG. 11, the input/output processing circuit main body 11A starts the extraction process for the first character at time t1, and then finishes the first character extraction process and generates the character extraction information SIMX. Output circuit 11
At the moment after latching to B and 11C, smell;
Character extraction processing for the second character can be started.

Thereafter, in the same manner, the input/output processing circuit main body 11A is operated at time t3,
In L4..., the previous time points t2 and t3
Each time the character cutting process started in .

In this way, the character cutting information aslNM latched in the output circuits 11B and 11C is transmitted to the major classification processing circuit 12A, respectively.
and the main classification processing circuit body 12A of the normalization processing circuit 13A.
1 and the normalization processing circuit main body 13AI.

The main classification processing circuit main body 12A1 has a CPU configured as a microcomputer, and inputs the character cutting information 5INX stored in the output circuit 11B.
N, execute the major classification process on the input character information SIN, and use the candidate character information data 5CADX obtained as a result as the first-in-first-array 1-
(FIFO) circuit configuration output circuits 12A2 and 12A3
By latching this, it is possible to pass the candidate character information SCAD to the standard pattern set circuit 13B of the subclassification identification section 13.

On the other hand, the normalization processing circuit main body 13A1 has a CPU configured as a microcomputer, and input character information SIN.
is read and normalized, and each input cover pattern data D, ! is obtained as a result. INX is sent to the output circuit 13A2 having a FIFO circuit configuration. Thus, the output circuit 13A
2 receives each input cover turn data Dpt+□ and converts it into input cover turn data DP? It is handed over to the input cover turnset circuit 13D as IN.

In this way, the major classification processing circuit body 12A1 of the major classification processing circuit 12A and the normalization processing circuit body 13A1 of the normalization processing circuit 13A simultaneously execute the major classification processing and the normalization processing independently from each other in parallel. Candidate character information S CAD and input cover turn data D, T, H can be delivered to the standard pattern set circuit 13B and input cover turn set circuit 13D at the same timing.

The processing operations of the major classification processing circuit main body 12A1 and the normalization processing circuit main body 13A1 are similar to those of the input/output processing circuit main body 11A.
In this way, the input/output processing circuit main body 11A executes the next character without waiting for the processing of the character information being processed in the major classification processing circuit main body 12A1 and the normalization processing circuit main body 13A1 to be completed. Execute the extraction process for 2 in parallel and simultaneously.

The standard pattern set circuit 13B and the input cover turns set circuit 13D each have a microcomputer configuration.
It has a PU and is configured to be able to execute processing operations independently and in parallel.

Thus, while the standard pattern set circuit 13B reads out the standard character pattern for the candidate character specified by the candidate character information SCAII and executes the setting process, the input cover turns set circuit 13D simultaneously reads the input cover pattern data. Executes DPTIN set processing.

When the standard pattern set circuit 13B and the input cover turns set circuit 13D start setting input cover pattern data D, ..., N, the subclassification circuit main body 13E1 of the subclassification processing circuit 13E reads this and executes subclassification processing. do. Here, the subclassification circuit main body 13E1 is composed of a dedicated hardware circuit, and thereby the standard pattern set data D,
? . 7 and input cover turn set data D IN! E? is sent out in time series, the FI performs a sequential matching operation.
Standard pattern reference residual patterns ERt+a, ERyes (8th
Figure) data as residual data D. At the same time as closing and sending out,
Similarly, the input pattern reference residual patterns ER□a, ERt*m
The data shown in FIG. 8 is sent as residual data D□.

As a result, the detailed classification circuit main body 13E1 executes the detailed classification operation almost simultaneously with the standard pattern setting operation and the input cover turns setting operation, as shown in FIG.

The determination processing circuit main body 14A of the determination processing circuit 14 has a CPU configured as a microcomputer, and independently of other processing circuits takes in residual data Dfl and executes determination processing.
The determination result data S□ is delivered to the input/output processing circuit main body 11A through the output circuit 14B having a FIFO circuit configuration.

This result determination processing circuit 14, as shown in FIG.
While the subclassification processing circuit 13E is executing the subclassification process, the judgment process is executed at the same time.

In the configuration shown in FIG. 10, the input/output processing unit 11 operates at time 1 in FIG. At time 1t after the processing is completed and the input character information SIN is delivered to the major classification processing circuit 12A and the normalization processing circuit 13A, the extraction processing of the second character is executed. Start the cutting process.

Similarly, time 1. ．． Immediately after finishing the character extraction process currently being executed in 14..., a new character extraction process is started.

In this way, when the first, second, third, old, etc. characters are cut out, the major classification processing circuit 12A and the normalization processing circuit 13A simultaneously perform the major classification processing and normalization processing in parallel. Execute the candidate character information S CAD and input cover turn data I) rt+N to the standard pattern set circuit 1.
3B and input cover turns set circuit 13D, and enters a state of waiting for the arrival of a new input character eraser 18S1.

At this time, the standard pattern set circuit 13 is handed over the candidate character information S CAt1 and the input pattern data D□.
B and the input cover turnset circuit 13D set the standard pattern set data D while executing the pattern setting operation.

, 7 and the input cover turn set data D lN0f are sent to the subclassification processing circuit 13H, and the subclassification processing circuit 13B subdivides them almost in real time to process the residual data D!
, 1 to the determination processing circuit 14. When the processing operation is finished, the standard pattern set circuit 13B
And the input cover turnset circuit 13D erases the new candidate character Il! The process returns to the state where it waits for the generation of 5CAD and input cover turn data DPTIN.

Residual data D. The determination processing circuit 14 that has been handed over the determination processing performs determination processing and outputs the character code for the first extracted character to the input/output processing unit 11 as determination result data 5RE3, and then outputs new residual data D. Returns to the state of waiting for delivery.

In this way, the processing operation for the first character is performed sequentially (input/output processing unit 11) - (major classification processing circuit 12A, normalization processing circuit 13A) - ((standard pattern set circuit 13B,
Input cover turnset circuit 13D) - Detailed classification processing circuit 13
Pipeline processing is performed in the order of E)-(judgment processing circuit 14).

Such pipeline processing is started each time the input/output processing unit 11 extracts a new character, and thus pipeline processing operations for a plurality of characters are executed in parallel and simultaneously.

In this way, according to the configurations of FIGS. 10 and 11,
When data to be processed sequentially is generated, each processing means arranged in a hierarchical structure is processed simultaneously (each performs a different job), thereby increasing the efficiency of the multiple processing means that make up the character recognition device. By being able to operate the character recognition processing operation, the overall speed of the character recognition processing operation can be further increased.

According to experiments, the recognition speed of a printed document, which was previously processed at a speed of several characters/second in a character recognition device configured to perform sequential processing, was increased to around 100 characters/second using the above-described configuration.

In the case of this embodiment, the main classification processing circuit main body 12A1 generates candidate character number information SCA as candidate character data SCADx.
The DN is latched in the output circuit 12A3, and is directly delivered to the judgment processing circuit main body 14A without passing through the standard pattern set circuit 13B and the subclassification processing circuit 13E,
This notifies the determination processing circuit main body 14A of the number of times the determination processing should be repeated.

At the same time, the major classification processing circuit main body 12A1 returns the same candidate character number information S CADN to the input/output processing circuit main body 11A via the output circuit 11B.
1 normalization processing circuit body 13A1 and output circuit 13A2 in order to inform the human cover turns set circuit 13D to supply information for matching the timing with the processing operation of the standard pattern set circuit 13B.

[G3] Character extraction processing circuit (G3-1) Extraction of character parameters In the above description, the case where the input/output processing section 11 extracts normal characters has been described, but in addition to this, the input/output processing section 11 also performs the following:
It is designed to cut out special characters such as vertically long characters, horizontally long characters, and small characters.

That is, the input/output processing circuit main body 11 of the input/output processing section 11
A is the input character M from the image information INF supplied from the image scanner unit 2, as shown in FIG. 12(A).
OJI is cut out using the circumscribing frame WAKU, and character parameters of the cut out input character MOJI are extracted.

Here, the character parameter is the circumscribing frame W of the input character MOJI.
The size and position information of the character cut out based on AKtJ is extracted as 15-byte character parameter data DMOJ+, as shown in FIG. 12(A).

Character parameter data DM. 1, character parameters W and H represent the width and height of the circumscribing frame WAKUO.

Character parameters CNW to DLTH represent threshold data used when extracting feature amounts in the major classification processing circuit 12A, and are each selected to have the following values, for example.

DLTH= □ ・・・・・・
(21) Character parameters W24 and H24 represent unit information when normalizing the input character MOJI in the normalization processing circuit 13A, and are expressed by the following formula % formula % (22) In contrast, the character parameters WRT, HCNT, HRT
is data representing the shape and position of the character, and the character parameter WRT represents the aspect ratio of the input character MOJI as shown in the following formula % formula % (24). Therefore, the character parameter WRT determines whether the input character is horizontally long or not. Or shape information such as whether it is vertically long can be obtained.

In addition, the character parameter HCNT is calculated using the following formula: %formula% represents the center position of the human-powered character MOJI.

Here, Ht represents the distance from the highest height position to the lowest height position of all characters in the line containing the input character MOJI (this is called the maximum length).

Thus, the character parameter HCNT in equation (25) represents the center position of the input character MOJl in the maximum length HL of the line.

The character parameter HRT is the input character MOJI for the maximum length HL, as shown in the following formula.
represents the ratio of the height of the input character MOJI.
It is possible to know whether the height of the object is low or not.

(G3-2) Selection of special character candidates The character cutting circuit 11AI of the input/output processing circuit main body 11A (Fig. 1θ) determines that the input character MOJI has a normal size with respect to the maximum length HL, based on the character parameter data DMOJ+. and a shape (i.e., a normal character) or a character without a normal size and shape (i.e., a special character), and
If JI is a normal character, the cut out character MOJ
Input the image information of l as is and erase the characters 14 S I
The main classification processing circuit 12A is output as N via the output circuit 11B.
hand over to.

Thus, the character identification unit 4 as a whole executes the pipeline processing for the above-mentioned normal characters.

On the other hand, the character cutting circuit 11A1 inputs the input character MOJ.
If it is determined that I is a special character, character parameter data DM. 1. The features of the input character MOJI are extracted using The data is then delivered to the major classification processing circuit 12A.

The characters that are determined to be special characters here are "!", "1"
", "-", "-", "-", ",", ",", "・"
, "'', etc., are vertically long characters, horizontally long characters, and small characters, and in addition to their shape and size, they are also characterized by their position in the height direction and width direction.

Therefore, the character cutting circuit 11AI receives character parameter data D,. Of Jl, character parameter WRT ((24)
(formula), HCNT (formula (25)), HRT ((26)
Using the formula), the following formula WRTX = −□ X32 ・・・・・・(
27) −+y L HCNTX=X32H.

・・・・・・(28) HRTX= −X32 ・・・・・・(29
)H, and using the evaluation data WRTX, WRTX>83...
... When (30), the input character MOJI is evaluated as "a vertically long character", and using evaluation data HCNTX, HCNTX>24 ...... (3
1), it is evaluated as “vertical and left-sided”, and the HC
NTX<12 (32)
When 12≦HCN, it is evaluated as “vertically long and to the right”
When TX≦24 (33), it is evaluated as “vertically long and close to the center”.

Furthermore, based on the evaluation data WRTX, the character cutting circuit 11AI evaluates that the input character MOJI is "a horizontally long character" when the following formula % formula % (34) is satisfied, and using the evaluation data HCNTX, HCNTX>
24 ・・・・・・ (35
), it is evaluated as “horizontal and upward”, and HCNTX<
12 ...... (36), it is evaluated as "horizontal and downward", and 12≦HCNTX≦2
4.When (37) is satisfied, it is evaluated as ``horizontally long and in the center''.

Further, the character extraction circuit 11A1 uses the evaluation data HRTX to evaluate that the input character MOJI is a "small character" when the following formula % formula % (38), and uses the evaluation data HCNTX to determine that HCNTX>24...・・・
...When (39) is evaluated, it is evaluated as "small font and located at the top (left in case of vertical writing)", HCN T X < 14 ...
- (40), it is evaluated as "lower in small letters (to the right in case of '4?i')", and 14≦HCNTX≦24 ・・・・・・(
41), it is evaluated as "small letters in the center".

The character cutting circuit 11AI selects a corresponding character code from the special major classification dictionary 11A2 based on the determination result.

The special major classification dictionary 11A2 classifies standard special characters based on the evaluation criteria of formulas (30) to (41) and stores them in advance with unique character codes.
For the input character MOJI from 1AI, equation (30) ~ (4
1) When the evaluation result of the expression is obtained, the standard special character code corresponding to the evaluation result is delivered to the character extraction circuit 11A1.

Here, as shown in FIG. 13, the character cutting circuit 11AI inputs the vertically written character MOJI as the image information INF, and replaces it with the evaluation data described above for equations (28) and (29) by using the following equation -+ y L ...... (42) is used.

According to the character extraction circuit 1 lAI described above, character parameters of the input character MOJI are extracted when the input character MOJI is extracted from the image information INF, and special candidate characters are selected based on these character parameters. , it is possible to further improve the identification accuracy of special characters.

Incidentally, it may be possible to perform hierarchical processing of major classification processing and subclassification processing for special characters as well, but since it is easier to understand the characteristics of special characters with parameter features than with vertical features, It is thought that the identification accuracy will be higher if the major classification process is not used.

[G4] Major classification processing circuit 12A As shown in FIG. 12, the major classification processing circuit 12A includes a peripheral feature detection circuit 21A and a candidate character search circuit 21B.
It has a configuration in which a CPU 21C having a microcomputer configuration executes a major classification process according to a program in a program memory 21D.

That is, when the input character information SIN is latched in the output circuit 11B of the input/output processing section 11, the CPU 21C takes in the data via the bus 21E and the data buffer circuit 21F, and also takes in the data via the address buffer circuit 21G and the control buffer circuit 21H. and controls the program memory 21D and address recorder 211.

In the case of this embodiment, the peripheral feature detection circuit 21A extracts the feature quantity DCIII (fourth
It has a hardware configuration including a conversion ROM for generating input characters MOJI (Fig. 3), a left side character portion MOJIA, a right side character portion MOJ1. ．． Feature value numerical data V A that captures the upper character part MOJIC1 and the lower character part MOJIo and represents the feature value DCHI.
It is configured such that the feature value numerical data V A L 11CMIk can be converted into Locwa (Equations (11) and (13)) and sent to the bus 21H at high speed.

The candidate character search circuit 21B sequentially searches A side, B side, 0 side,
When the feature value numerical data V A L DCHII of side D is sent, it is taken in and candidate characters having the relevant feature value numerical data V A L ocm for each side are retrieved from the major classification dictionary 12B (Fig. 10). search for.

In FIG. 15, candidate character search circuit 21B has candidate memory 23A.

As shown in FIG. 16, the candidate memory 23A stores candidate character codes assigned to all recognition target characters (in this embodiment, numerical values from "0" to r4095J are assigned as candidate character codes). It has a 4-bit memory area used as an address.

The first and second configuring the memory area of each candidate character code.
, the memory areas of the third and fourth bits are A side, B side, 0
The 1-bit candidate display data CAD for sides and D sides is stored, and the input character erase nS+N for one character is delivered from the input/output processing section 11 (FIG. 14) to the major classification processing circuit 12A. When there is a character with the same characteristic ff1ffi as the feature quantity that the peripheral feature detection circuit 21A was able to find for the A side or the D side, the logic rlJ is stored in the memory area of the candidate character code assigned to the character. Candidate display data CAD is written.

In this way, if there is a memory area for candidate character codes in which the candidate display data CAD on sides A to D are all logic "1", it can be determined that the character with the candidate character code is similar to the human-powered character. is being done.

The major classification dictionary 12B is major classification dictionary data I) ctAs, which is used when determining in which memory area of the candidate memory 23A the candidate display data CAD should be written from the input character information SIN. ) is the A side or D side storage area part MI corresponding to the A side or D side.
It is stored in A or MID.

Major classification dictionary data D CLA□ is header data (D
HD A T) A and character code part data (DICDA
T) A, and the header data (DHDAT) a is
All recognition target characters (candidate character code "0" ~ r 4
095 J is assigned) has feature quantity numerical data VALocm (formula (11) and formula (13))
"8"...r128 For each J, the number of characters (
In other words, candidate number data D2 representing the number of candidates) and dictionary address data D3 representing the start address of character code part data (DICDAT) A in which character addresses for the candidate number data D2 are stored for each feature code DI. to 1
Stored in pairs, special@, quantity numerical data V A L
When DCMR is detected in the peripheral feature detection circuit 21A, the feature quantity numerical data VALDCHII
The address where the feature code Di is stored can be directly accessed by the user, and the number of candidates data D2 and dictionary address data D3 that are combined with the feature code D1 can be read out.

Character code part data (D [CD A T) A is 409 with candidate character code "0" to r 4095 J
The six characters are grouped into groups of characters that share the feature code D1 among the A-side peripheral features, and are stored in a memory area assigned a series of addresses "0" to r4095J.

In this way, the candidate character code Do stored in the character code section data (DICDAT) A is feature quantity numerical data that represents the feature quantity DCMI possessed by the A-side peripheral feature among the characters to which the candidate character code is assigned. VALDCMII as peripheral feature detection circuit 21
It can be read by inputting from A to the candidate character search circuit 21B.

For example, the candidate character search circuit 2 uses the feature value numerical data VALDCHII representing the first feature code Di (=r8J).
1B, the candidate character search circuit 21B searches the candidate number data D2 (=r143) from the start address "0" specified by the dictionary address data D3 (=rOj) as the character code section data (DICDAT)a.
It is possible to access the candidate character codes Do in the memory area in which J) candidate character codes DO are stored, that is, the memory area up to the end address r142J.

The processing procedure for writing the candidate display data CAD corresponding to the characteristics represented by the characters of the input character information SIN into the candidate memory 23A in this way is as shown in FIG. Special @ quantity numerical data obtained for the sides (V A Loco *)
A~(V A L DCHR) Header part data (D HD
A T)A~(DHDAT). By accessing feature value numerical data (V A Loco *) A
～(V A L oco *) Feature code D corresponding to o
I, number of candidates data D2, and dictionary address data D3 can be specified.

Thus, this header data (D HD AT )
Character code part data (DI
By accessing CDAT)A to (DICDAT)o, all candidate character codes DO assigned to characters having the same characteristics as those of the input character information SIN are stored in the major classification dictionary data DcLAs! It is possible to read each side from A to D.

The candidate character code DO read in this way is used as address information for the candidate memory 23A, and is used as address information for the candidate memory 23A.
3A, candidate display data CAD of logic "1" can be written in the memory area having the accessed candidate character code DO for each side A to D.

Such a function can be realized by the candidate character search circuit 21B having the configuration shown in FIG.

In FIG. 15, the major classification dictionary 12B has a candidate character code classification storage area M1, a work area M2, a candidate character reading rear address storage area M3, and a special character code storage area M4.

The candidate character code classification storage area M1 is a storage area section MIA, M that stores the major classification dictionary data I) cLAss described above with reference to FIG. 17 for the A side, B side, 0 side, and D side.
IBSMIC, MID, and by specifying a side representing a peripheral feature and a feature code D1, the corresponding candidate character code DO can be sent to the candidate memory 23A as data DATA2.

That is, as shown in FIG. 17 for example from the peripheral feature detection circuit 21A, when the A-side feature detection data DATA1 representing the feature code "8" arrives, this is sent to the address data ADD via the address buffer circuit 23B.
By importing it as R1, the first set of feature codes of the feature codes D1 of the header data (D HD A T) A stored in the storage area section MIA on side A of the candidate character code classification storage area M1. Di(=r8J
) is accessed.

At this time, the major classification dictionary 12B stores the first set of candidate number data D2 (=r143 J) and dictionary address data D3 (=rOJ) as output data DATA via the address buffer circuit 23C into an operation count register. 23D and first 7 address registers 23B
write to.

At this time, the candidate number data D2 (= r143 J) is set in the operation number count register 23D, so the control circuit 2
3F sends out a control signal S1 based on the output of the timing generation circuit 23G, so that the candidate character search circuit 21
The search operation of B is started as a whole.

At this time, the storage contents of the head address register 23H, that is, the dictionary address data D3 (=rOJ) are stored at the 0th address of the character code part data (D I CDAT) a of the A side storage area MIA of the candidate character code classification storage area M1. Access memory area.

Here, the memory area at address 0 contains the candidate character code DO.
(-r67J) (FIG. 17) is stored, this is sent to the candidate memory 23A as access data DATA2, and thus the state is reached in which address "67" of the candidate memory 23A (FIG. 16) is accessed.

However, since a search operation is currently being performed regarding the peripheral characteristics of side A, the control circuit 23F sends out a signal specifying side A as the side selection signal HEN included in the control signal Sl, and this is sent to the gate circuit 23H1 bus buffer circuit. 231, the A-side memory area of the candidate memory 23A is specified, so that the candidate memory 2
Logic "1" is written in the memory area of side A of address "67" of 3A.
The candidate display data CAD will be written.

When this operation is completed, the operation count register 2
3D performs decrement operation and the count content is r143
J, the start address register 23E increments, and the first address of character code part data (DICD A T) a is read as address data ADDR4.
The state changes to access the memory area at the address.

　　　.

At this time, the candidate character code Do (= r241 J) stored in the memory area at the first address of the character code part data (DI CDAT) A is the access data D.
It is sent to the candidate memory 23A as ATA2, and by accessing the memory area at the 241st address and side A of the candidate memory 23A, candidate display data CAD of logic "1" is written in the memory area.

When the write operation is completed, the operation count register 23D decrements and the start address register 23E increments at the same time as in the case described above, so that the next character code part data (
The control state is changed to access the memory area at address 3 of D I CDAT)A.

Thereafter, in the same manner, among the character code part data (DICDAT) A stored in the A-side storage area MLA of the candidate character code classification storage area M1, the 143 candidate character codes DO included in the first IJ1 are sequentially read. The data is output and used as access data DATA2 for the candidate memory 23A.

Eventually, when all the access operations for the 143 candidate character codes DO included in the first set of character code part data (DICDAT) A are completed, the count content of the operation count register 23D becomes 0, and the corresponding process is terminated. This means that the operation has ended, and at this time, the control circuit 23F puts the candidate character search circuit 21B as a whole into a state of waiting for the arrival of the next data DATAI.

In addition to this, the major classification processing circuit 12A subsequently processes the B side, 0
Every time the feature quantity numerical data V A LnHc* representing the peripheral characteristics for the side and D side arrives as data DATA1, the major classification dictionary 12B takes it in as address data ADDR1 via the address buffer circuit 23B. Major classification dictionary data DcLA! stored in side, 0 side, D side storage area section MIB, MIClMLD! , the candidate character code DO of candidate memo IJ 23 A is set in the header part data (DHDAT) s.
, (DHDAT) (D HD AT) n character code part data (DICDAT) (DICDA
By reading out (DICDAT)o and giving it as address data to the candidate memory 23A, logic "" is written in the memory areas corresponding to the B side, 0 side, and D side.
An operation such as writing the candidate display data CAD of ``1'' is returned.

When this operation is completed, all candidate characters with peripheral characteristics for the four sides of one character have been searched for each side, and candidate display data for all sides A to D has been searched. This means that the written character with the candidate character code DO is determined to be a candidate character for all four sides, and therefore the candidate display data CAD of logic "1" is displayed for all memory areas on sides A to D. The candidate character search circuit 21B performs operations such as reading from the candidate memory 23A and writing into the work area M2 of the major classification dictionary 12B.

That is, in the reading mode, the major classification dictionary 12
Among the reading read addresses stored in the candidate character reading read address storage area M3 of B, the last address of the candidate memory 23A (in this case, address 4095) + 1 (=409
6) is set in the operation count register 23D, and the start address of the candidate character reading address storage area M3 is set in the start address register 23E.

At this time, the control circuit 23F starts the reading operation of the candidate character search circuit 21B as a whole, and uses the address data ADD sent from the first top address register 23E.
Rl sends out the 71st pulse data at the start address of the candidate character reading address storage area M3 (in this case, address O) as access data DATA2 to the candidate memory 23A.

At this time, the candidate memory 23A reads out the candidate display data CAD written in the memory area at the 0th address on the A side as read data DATA4, temporarily stores it in the flip-flop circuit 23J, and all the output data are "
1” to the detection circuit 23K.
It is detected whether all of the edge data is logical rlJ.

The output data of the flip-flop circuit 23J is held by being fed back to the input side of the flip-flop circuit 23J via the gate circuit 23H and the pass buffer circuit 23+.

Here, when the all r l J detection circuit 23K obtains a detection signal S3 of logic "1" indicating that the 4-bit candidate display data on the A side to the D side are all 1, the control circuit 23F outputs the access data. DATA2 is latched into the latch circuit 23L, and the latch output DA
TA5 is written to the start address of the work area M2, the operation count register 23D is decremented, and the candidate count register 23M is incremented.

In contrast, the detection signal S to the all rlJ detection circuit 23
When the control circuit 23F enters a state indicating that 3 is not all "1" (ie, logic "0"), the control circuit 23F proceeds to the next step without reading the access data DATA2 into the work area M2.

When the read operation of the first address of the candidate memory 23A is thus completed, the operation count register 23D decrements and the first address register 23E increments, so that the read address is stored at the next address in the candidate character read address storage area M3. The read address (i.e., the first address) is sent to the candidate memory 23A as access data DATA2, and all "1" is detected in the candidate display data CAD of the person passing or D side written in the first address of the candidate memory 23A. It is read out to the circuit 23K.

At this time, when detecting that the detection signal S3 is all "1", the control circuit 23F outputs the access data DA.
TA2 is written to the memory area at the next address of the work area M2 via the latch circuit 23L, the operation number register 23D is decremented, and the candidate number count register 23M is incremented.

Thereafter, the above-described operation is repeated in the same manner until the count content of the operation count register 23D becomes 0.
As a result, the candidate display data CAD written in all the addresses of the candidate memory 23A are sequentially read out to the all rlJ detection circuit 23K, and when all rlJ detection circuits 23K are all "1", the current access data (therefore, the candidate character code Do) is read out as the workpiece. It is read into area M2.

When the reading operation of candidate display data has been completed for all addresses in the candidate memory 23A in this way, the work area M2 is filled with addresses where candidate display data CAD has been written for all sides A to D (therefore, candidate characters At the same time that the code DO) is stored, data representing the number of candidate characters is held in the candidate number count register 23M.

In this way, the major classification process for one input character is completed, and the candidate character codes Do read into the work area M2 of the major classification dictionary 12B are sequentially read out to the output circuit 12A2 and are standardized as candidate character information S CAl1. The information is passed to the pattern set circuit 13B (FIG. 10), and the count contents of the candidate number count register 23M are candidate character number information S. , and is delivered to the determination processing circuit main body 14A (FIG. 10) via the output circuit 12A3.

In this state, the major classification processing circuit 12A as a whole is in a state of waiting for the arrival of the next manual character erasure 11IN, and when new input character information SIN arrives, it is classified into the same major classification as in the above case. Processing is performed immediately and independently of other circuit parts.

According to the large classification processing circuit 12A having the above configuration, the candidate display data CAD representing the peripheral characteristics of the traffic side or the D side is written for each side using the candidate memory 23A, and all of the A side or the D side are written. The address assigned to the memory area where the candidate display data was obtained is the candidate character code DO.
By reading the data as follows, it is possible to realize a large classification processing circuit that can perform large classification processing at high speed while combining hardware configurations with high operating speeds.

In this way, the major classification dictionary 12B is converted into header data (
DHDAT)A~(DHDAT), and character code part data (DICDAT)A~(DIC
DAT). The feature quantity numerical data VALIIM representing the peripheral characteristics is structured so as to be divided into two. Directly header part data (D, HD AT) A ~ (D HD AT)
By using this as the specification data for the feature code D1 of o, a plurality of candidate character codes Do can be easily read out with a simple data structure.

Also, candidate number data D2 of candidate characters having a common feature code DI and character code part data (DICDAT) A
~ (D I CD A T) Dictionary address data D3 representing the start address of
T)A~(D HD A T)D is used to read out the candidate character codes DO of the character code section data, thereby reliably reading out a large number of candidate character codes Do one by one with a relatively simple configuration. Can be sent.

[G5] Subdivision slope identification unit 13 (G5-1) Overall configuration The subdivision identification unit 13 receives the candidate character JI\! from the major classification processing circuit 12A as shown in FIG. When the standard pattern set circuit 13B receives the information S CAl1, the detailed classification dictionary 13
The X-direction and Y-direction standard character patterns designated by the candidate character information SCAD are sequentially read out in that order from the X-direction dictionary section 13c1 and Y-direction dictionary section 13C2 of C, and set in the standard pattern setting circuit 13B.

The standard character pattern consists of dot information for 24 lines x 24 dots, and the dot information for two lines, that is, the even number line and the odd number line, are stored in the even number line and odd number line stroke extraction circuit parts 33A and 33B of the stroke extraction circuit part 33, respectively. It is taken into stroke detection circuits 33AO and 33BO provided in the.

Corresponding to this, the subclassification identification unit 13 converts the dot information of the even and odd lines of the input cover pattern data DP7IN, which has been normalized to 24 lines x 24 dots in the normalization processing circuit 13A, into even and odd line strokes. Stroke detection circuit 3 of extraction circuit parts 33A and 33B
Import into 3A1 and 33B1.

The even line stroke detection circuits 33AO and 33A1 extract the strokes included in the corresponding even lines of the standard character pattern and the input character pattern, respectively, and are provided in the even line pattern matching circuit section 41A of the pattern matching circuit section 41. Stroke center coordinates and stroke width are detected in stroke center coordinate and stroke width detection circuit units 41AIO and 41A20,
Stroke center coordinate and stroke width coincidence detection circuit section 4
A match is detected for the standard character pattern and the input character pattern in 1AOR and 41AOI.

Odd line stroke detection circuits 33BO and 33B1 similarly extract strokes included in odd lines,
Stroke center coordinates and stroke width detection circuit section 41B
If the stroke center coordinates and stroke widths detected in 10 and 41B20 match, the match detection circuit unit 41BI
Detected in R and 41BII.

The match detection outputs of the even-numbered lines and odd-numbered lines are used in the standard character pattern residual calculation circuit section 45R to erase patterns based on the standard character pattern, and the human-powered character pattern residual calculation circuit section 45■ is used to erase the pattern based on the standard character pattern. Used to erase the reference pattern.

In this way, the residual data DEL1 obtained from the standard character and input character pattern residual calculation circuit sections 45R and 451 is delivered from the output circuits 13E'2 and 13E3 to the determination processing circuit main body 14A.

(G5-2) Standard pattern set circuit 13B As shown in FIG. 19, the standard pattern set circuit 13B has a CPU 31A configured as a microcomputer, and controls a program memory 31C and an address decoder 31D by a control buffer circuit 31B. Data processing is executed by supplying address data to the program memory 31C and address decoder 31D through the address buffer circuit 31E.

That is, the CPU 31A is the control buffer circuit 31.
By controlling the output circuit 12A2 and flag register 31F of the major classification processing circuit 12A through the bus 31G and the flag register 31F, candidate character information SCAD latched from the major classification processing circuit main body 12A1 to the output circuit 12A2 is transferred to the bus 31G and the data buffer circuit 31J. At the same time, it is taken into the address counter 3 through the control buffer circuit 31B.
X-direction and Y-direction standard pattern dictionary section 13C stored in the subdivision dictionary 13C by controlling the
The standard pattern data D, T, and D are read out from 1 and 13C2 and written into the shift register 311 as dot information for even and odd lines. It is designed so that it can be sent as line data information QRDO consisting of 23 line parallel data.

(C, 5-3') Input cover turns set circuit 13D As shown in FIG. 20, the input cover turns set circuit 13D reads out the subdivision dictionary 13C by comparing with the standard pattern set circuit 13B of FIG. 19. Address counter 31 for
It has almost the same configuration as the standard pattern set circuit 13B except that H is not provided.

Therefore, in FIG. 18, parts corresponding to those in FIG. 17 are shown with the same letters of the alphabet.

(G5-4) Shift registers 311 (Fig. 19) and 321 (second
Line data QRDO and QID set in Figure 0)
O is taken in one line at a time to the even line and odd line stroke extraction circuit sections 33A and 33B of the stroke extraction circuit section 33 of the subclassification processing circuit main body 13E1 shown in FIG.

Even number line and odd number line stroke extraction circuit section 33A
and 33B have the same circuit configuration, so the second
In FIG. 1, even number line stroke extraction circuit section 33
The detailed configuration of A is shown below.

The even line stroke extraction circuit 33A is shown in FIG.
) and (B), based on the circuit clock CLOCK, the line data is taken in and processed in coordination with the shift register 311 of the standard pattern set circuit 13B and the shift register 321 of the input cover turns set circuit 130. , the length of the stroke of black characters included in each line (i.e. the length of consecutive dots)
Standard pattern coordinate data RA that extracts and represents its coordinates
DDQ and input pattern coordinate data 5ADDo are formed.

Shift register 311 of standard pattern set circuit 13B
are load signals RLDOO and RLDOI (second
When Figure 2 (A) and (B)) occur, the load signal R
The upper 16 bits of the dot data of 2 and 4 dots are loaded into the shift register 311 by LDOO, and the lower 8 bits of load data are loaded into the shift register 311 by the subsequently generated load signal RLDO1.

This load signal tile τ]""drunk and 1st time]""is the enable flag circuit 34A of the stroke extraction circuit 33A (
(consisting of a flip-flop circuit) as a set signal, thereby causing the enable flag circuit 34A to
The enable flag signal HDENR, which rises to the logic rHJ level, is sent out on the condition that the load signal RLDO1 of the rear cylinder 2 is generated when the load signal RLDOO is generated.

The enable flag circuit 34A is reset by receiving as a reset signal the line data capture end signal LEND generated when the stroke extraction circuit section 33 finishes its stroke extraction operation.

This enable flag signal HDENR is supplied to the AND circuit 34.
B, and the shift control signal CIRO (FIG. 22(A)
) and (B)) to the logic rHJ level.

This shift control signal CIRO of logic rH" level is given to the shift register 311 of the standard pattern set circuit 13B as a shift permission signal, and at this time, the shift register 311 transfers dot data by 1 in each cycle according to the circuit clock CLOCK. Line data QR dot by dot
It is sent as a DO (Fig. 20 (A) and (B)).

This line data QRDO is given as a set signal to a cooperative operation circuit 34C having a flip-flop circuit configuration.

The cooperative operation circuit 34C is configured so that the line data QRDO is logical.
It is configured to perform a set operation when it transitions from the logic "1" level to the logic "0" level, and at this time, the logic "1" is output to the output terminal.
The cooperative operation signal RDSR (FIGS. 22(A) and 22(B)) rising to the ``level'' is sent out.

The cooperative operation signal RDSR is inverted by the inverter 34D and supplied to the AND circuit 34B, and after the enable flag signal HDENR rises to the logic "1" level, the line data QRDO changes from the logic "1" level dot to the logic "1" level. Since the cooperative operation signal RDSR is at the logic "0" level until it moves to the "0" level dot, the shift control signal CIRO is maintained at the logic "1 level", and thus the line data QRDO is transferred from the shift register 311. Keep sending.

In contrast, the line data QRDO dot data
Shift when falling from A r I J level to logic r OJ level) 1ill < B signal CIRO to logic "
0” level, shift register 3
The shift operation of No. 11 is stopped.

Thus, at time t0 the load signal RLD.

At the time t when the enable flag signal HDENR rises to the logic "1" level after the occurrence of (2), the shift register 311 performs a shift operation, and after the line data QRDO, which is sequentially fetched, once transitions to the logic rlJ (first (represents the point in time when the dots in the character section are scanned)
The shift operation of the shift register 311 is stopped at the point when the signal falls to the logic "0" level (meaning the end point of the character section).

In this embodiment, the standard pattern set circuit 13B outputs data between the 2nd bit to the 4th bit, between the 7th bit, and between the 9th bit to the 11th bit, etc., as shown in the following formula. Data with black character strokes is input,
Therefore, at time 1 in FIG. 22(A). When the shift register 311 starts the shift operation, the line is shifted at the timing when the 0th bit data "0" is sent out by the first circuit clock CLOCK and then the 1st bit shifts to the 2nd bit. Data QRDO rises from logic "O" to logic rlJ, falls from logic "1" to logic "0" when moving from the 4th bit to the 5th bit, and becomes logic "0" when moving from the 6th bit to the 7th bit.
It rises to a logic "1" from the 7th bit and falls from a logic "1" to a logic "0" when moving from the 7th bit to the 8th bit.
When moving from the 8th bit to the 9th bit, it rises from logic "0" to logic "1", and when moving from the 11th bit to the 12th bit, it falls from logic "1" to logic "0"...
By exhibiting changes in the logical level such as...
The timing at which logic rlJ rises from logic "0" to logic rlJ represents the start point of the stroke, and the timing at which logic rlJ subsequently falls to logic "0" represents the end point of the stroke.

The start point and end point of this stroke are detected by the standard pattern start point and end point detection circuit section 33D.

The standard pattern start/end point detection circuit section 33D has a stroke detection circuit 37A having a flip-flop circuit configuration, and when the data rises from logic "0" to logic "1" in response to line data QRDO, the circuit clock CLOCK is output.
The set operation is performed at the timing of , and then the line data QR
When DO falls from logic "1" to logic "0", a reset operation is performed at the timing of the circuit clock CLOCK.

Thus, the output terminal of the stall detection circuit 37A has the second
As shown in Figure 2 (A) and (B), the line data QR
Time t when DO rises from logic "0" to logic "1"
At timing 2, the stroke detection signal REF which rises to "1" from the logic rOJ is sent out. This stroke detection signal REF then falls from the logic rlJ to "0" at the timing t when the line data QRDO falls from the logic "L" to "0".

Thus, the stroke of the first character portion can be represented by the stroke detection signal REF which rises to logic "1" during time ttxt.

The stroke detection signal REF is applied together with line data QRDO to a start point detection circuit 37B and an end point detection circuit 37C, each of which is composed of a flip-flop circuit. logic r during the clock period
Generates a start point detection signal RRGτTT that rises to lJ,
Further, at the time t when the stroke detection signal REF falls to logic "0", the end point detection signal -RR rises to logic "1" for one clock cycle from the end point detection circuit 37C.
Send ]- in GL.

The shift control signal CIRO is given to the standard pattern address counter 34D, and the shift control signal CIRO is set to logic r.
1J, the standard pattern address counter 34D outputs the circuit clock CLOCK in synchronization with the shift register 311 sending out the line data QRDO one bit at a time.
By counting , standard pattern coordinate data RADDO representing the bit address of the sent standard pattern data (therefore, the position coordinates of 24 dots included in one line) is sent out.

Standard pattern coordinate data RADDI is similarly sent out from the odd line stroke extraction circuit section 33B.

The input cover turn line stroke extraction circuit section 33Al is
It has a processing system similar to that of the line data QRDO for the standard pattern, and as shown by attaching the same alphabetic characters to corresponding parts, the load signal ILDO
0 and 1] Y "Enable flag circuit 35 that receives
The enable flag signal HDENI obtained from A is sent to the input cover turn shift register 321 and the input cover turn address counter 35D via the AND circuit 35B as the shift control ll signal Cll0, and the ta signal is sent to the input cover turn shift register 321 and the input cover turn address counter 35D via the AND circuit 35B. A cooperative operation signal ID5R obtained from the adjustment circuit 35C is applied to the AND circuit 35B via an inverter 35B.

Thus, from the input cover turnset circuit 13D to FIG.
As shown in A) and (B5), when line data QIDO with a bit arrangement like the following formula % is sent from the shift register 32!
and (B), the load signal used in the standard pattern data processing] The load signal ILD shown in correspondence with the adjustment signal RDSR. ILDO
Shift register 321 by O and -'I]y]-
Processing is executed based on one line of line data QIDO set to QIDO.

The standard pattern side cooperative operation signal RDSR and the input pattern side cooperative operation signal IDSR are applied to an AND circuit 36A, and the AND output thereof is applied to a reset pulse generation circuit 36B.

When the AND output of the AND circuit 36A becomes logic "1", the reset pulse generating circuit 36B generates the signal as shown in FIG. 22(A).
And as shown in (B), after the delay time DL has elapsed, a reset pulse QDSR that falls to the logic rLJ level by a predetermined time width DLR is generated, and this is sent to the standard pattern side and input cover turn side cooperative operation circuits 34C and 35C. By applying this as a reset signal to QDSR, the cooperative operation circuits 34C and 35C are reset at the timing when the reset signal QDSR rises to the logic rlJ level.

Thus, when the cooperative operation circuits 34C and 35C perform a reset operation, the cooperative operation signals RDSR and ID5R fall to the logic rLJ level at the same time, and this fall causes the shift control signal CIRO to become the logic rHJ level via the inverter 34E and the AND circuit 34B. By raising the shift register 311 and the standard pattern address counter 34D to the logic "1" level, the shift register 311 and the standard pattern address counter 34D are shifted and counted, and at the same time, by raising the shift control signal Cll0 to the logic "1" level via the inverter 35E and the AND circuit 35B, the shift register 311 and the standard pattern address counter 34D are shifted and counted. The register 321 and the input cover turn address counter 35D are started to shift and count.

Thus, the standard pattern data processing system and the input cover pattern data processing system of the even line stroke extraction circuit section 33A simultaneously begin the stroke extraction operation for the next character section.

In addition to this configuration, the reset pulse signal QDSR is applied to the even line data capture end signal generation circuit 36C. Even line data capture end signal generation circuit 36C
22 (A) and (A) when the stroke detection operation for the even-numbered line is completed (that is, when the address becomes "24") together with the standard pattern coordinate data RADDO and the incoming pattern coordinate data IADDO.
As shown in B), an even line data capture end signal CHAEND rising to the logic rHJ level is generated and sent to the line data capture end signal generation circuit section 33C.

The line data capture end signal generation circuit section 33C waits for the odd line data capture end signal CHBEND (FIG. 22 (A) and (B)) to be given from the odd line stroke extraction circuit section 33B, and then Line data capture end signal CHAEND and CH
When both BENDs are obtained, Fig. 22 (A) and (B
), a line data acquisition end signal LEND that falls to the logic rLJ level during a predetermined period is generated.

This line data capture end signal LEND is transmitted to the standard pattern side cooperative operation circuit 34C and the enable flag circuit 3.
4A, input cover turn side cooperative operation circuit 35C and enable flag circuit 35A as a reset signal,
As a result, the even-numbered line stroke extraction circuit section 33A as a whole enters a standby state in which it takes in the line data of the next line.

Stroke center point comparison outputs IER and R are sent from the pattern matching circuit section 41 to the cooperative operation circuits 34C and 35C.
ER is provided to enable the pattern matching operation described above with respect to FIG.

The incoming cover turn start and end point detection circuit section 33E has the same configuration as the standard pattern start and end point detection circuit section 33D, and generates a stroke detection signal IEF in the stroke detection circuit 38A based on the line data QIDO and outputs a start point start signal. IRGLOO and end detection signal IRGLO
Generate I.

In this way, the end point detection signals RRGLOO, IRGLOO and the end point detection signals ■100τ TT, I100τ, which are formed in the standard pattern and the input cover turn start and end point detection circuit parts 33D and 33E, respectively correspond to the pattern pine shown in FIG. The signal is given to the matching circuit section 41 as a pattern matching operation control signal.

(G5-5) Pattern Matching Circuit Section 41 As shown in FIG. 23, the pattern matching circuit section 41 includes an even line pattern matching circuit section 41A that receives standard pattern coordinate data RADDO and input pattern coordinate data I ADDO, respectively. Standard pattern coordinate data RAD
D1 and an odd line pattern matching circuit section 41B that receives input cover pattern coordinate data IADDI (FIG. 18). In FIG. 21, the odd line pattern matching circuit section 41B has the same configuration as the even line pattern matching circuit section 41A, so illustration and description thereof will be omitted.

The standard pattern coordinate data RADDO is given to the starting point address register 42A and the ending point address register 42B, and the standard pattern starting point and ending point detection circuit section 33D (FIG. 21)
When receiving the start point detection signal RRGLOO and the end point detection signal RRGLOI obtained from the start point address register 42A and the end point address register 42B,
write to.

Note that in FIGS. 22(A) and (B), the rising point of the start point detection signal RRGLOO and the end point detection signal RRGLO
Although the timing is shown such that the rising point of I rises at the last point of the clock period of the address data when the logic level of the line data QRDO switches, in reality, the standard pattern address counter 3
Since the switching of address data in 4B is delayed,
The start point address register 42A and the end point address register 42B can latch the determined address data in the start point address register 42A and the end point address register 42B when a change occurs in the line data.

The start point address and end point address latched in the start point address register 42A and the end point address register 42B are given to a stroke center coordinate detection circuit 42C and a stroke width detection circuit 42D.

The stroke center coordinate detection circuit 42C and the stroke width detection circuit 42D are each composed of a conversion ROM, and their conversion outputs DI+ and Dl! to the stroke center coordinate comparison circuit 43A and the stroke width comparison circuit 43B, respectively.
is given as a comparison input.

On the other hand, the input cover turn coordinate data IADDO is similarly generated by the start point address register 44A and the end point address register 44B by the input cover turn start point and end point detection circuit section 33E.
Starting point detection signals IRGLOO and IRGLO obtained from
I is latched by I, and the latch output is the conversion ROM
Stroke center coordinate data DH and stroke width data D in the stroke center coordinate detection circuit 44C and stroke width detection circuit 44D of the configuration are transferred to the stroke center coordinate comparison circuit 43A and the stroke width comparison circuit 43B.
is given as a comparison input.

When the stroke center coordinate data D11 on the standard pattern side and the stroke center coordinate data D21 on the input cover turn side match, the stroke center coordinate comparison circuit 43A generates a match horizontal output signal EQLC of logic "1" level and outputs the AND circuit 43C. Send to.

In this embodiment, the stroke center coordinate comparison circuit 43A determines whether the difference in input data falls within a predetermined threshold level, and sends out a coincidence detection signal EQLC when a positive result is obtained.

The stroke width comparison circuit 43B outputs the standard pattern side stroke width data [)+1 and the input cover turn side stroke width data D! ! When there is a match, a match detection signal EQLW that rises to the logic "1" level is generated, and this is sent to the AND circuit 4.
Give to 3C.

In this embodiment, the stroke width comparison circuit 43B determines whether the difference in input data falls within a predetermined threshold range, and when a positive result is obtained, obtains a coincidence detection signal EQLW.

When the AND output of the AND circuit 43C becomes the logic "1" level, it is applied as the erase control signal 5ERA to the standard character pattern stroke erasing circuit 43D and the input character pattern stroke erasing circuit 43.

The standard character pattern stroke erase circuit 43D receives as input data the start point address data latched in the start point address register 42A and the end point address data latched in the end point address register 42B, and is given an erase control signal 5ERA of logic "L" level. When the timing is between the start point address and the end point address, the logic becomes “0”.
In response to this, the erase control signal 5ER is sent out.
When A is at the logic "0" level, logic "1" data is output at the timing of the start point address and the end point address.

Thus, when the input character pattern has a stroke having a position and width that match the input character pattern with reference to the stroke of the standard character, the stroke of the standard character pattern can be erased by the stroke of the input character pattern.

On the other hand, if the input character pattern does not include strokes that do not match in either position or width, the standard character pattern stroke deletion circuit 43D converts the stroke data corresponding to the input data into standard character deletion pattern data. The standard character erasing pattern data REFA is sent from the circuit 43F.

The input character pattern stroke deletion circuit 43E is similar to the standard character pattern stroke deletion circuit 43D, except that the strokes to be deleted are the start point address data and end point address data latched in the start point address register 44A and the end point address register 44B. The input character erasing pattern data INA can thus be obtained from the input character erasing pattern data forming circuit 43G.

In this embodiment, the standard character erasing pattern data forming circuit 43F has a register circuit 43F1 that dynamically stores the addition output by feeding it back to the input terminal, and when receiving erasing data from the standard character pattern stroke erasing circuit 43D, After rewriting the data of the corresponding coordinates, the result is sent out as standard character erasing pattern data REFA and is also dynamically stored.

In this way, when a plurality of strokes occur in one line of data in the start point address register 42A and the end point address register 42H, unerased stroke data is generated at the coordinate position of the stroke.

The input character erasing pattern data forming circuit 43G also has a similar register circuit 43G1.

In addition to the above configuration, the pattern matching circuit section 41 is provided with a comparison circuit 43H that receives the sending outputs of stroke center coordinate detection circuits 42C and 44C and D□ as comparative human power A and B, and when A>B, When the strokes do not match, the comparison output IER is obtained at the logic "1" level, the comparison output RER is obtained at the logic "1" level when A<B, and the comparison outputs IER and RER are given to the cooperative operation circuits 35C and 34C. By temporarily stopping the shifting of the dot data with larger center coordinates, all the strokes included in the input character pattern are combined with all the strokes included in the standard character pattern, as described above with reference to FIG. Matching processing can be performed.

Here, if the center coordinates of the strokes of the standard pattern and the input pattern match, the stroke center coordinate comparison circuit 43A
When the comparison output EQLC becomes logic "1", the outputs RDSR and T DSR of the cooperative operation circuits 34C and 35C
If both become logic "1", it means that matching has been achieved. At this time, by outputting the reset signal QDSR, the operations of the address counters 34D and 35D1 shift registers 311 and 321 are restarted.

In addition, the start and end points of the standard pattern and the character part of the input pattern are detected, and the outputs RDSR and ID5R of the cooperative operation circuits 34C and 35C are RDSR= rlJ and ID
When 5R=rlJ, if the output EQLC of the stroke center coordinate comparison circuit 43A is logic "0", it means that matching has not been achieved.

In this state, when the center position of the stroke of the standard pattern is larger than the center position of the stroke of the input pattern, that is, when RADDC>IADDC, the comparison output IER becomes logic "1", and the stroke extraction circuit section 33 (21st The cooperative operation circuit 35C on the input cover turn side shown in the figure is reset and starts the operation of the shift register 321 and address counter 35D. On the other hand, the cooperative operation circuit 34C on the standard pattern side maintains an unreset state.

When the center position of the stroke is reversed, the cooperative operation circuit 34
The operation of C and 35C is reversed.

In this way, all the strokes that are practically necessary for the input pattern can be matched with all the strokes of the standard pattern.

In the case of this embodiment, gate circuits 431 and 43J are provided at the input ends of the standard character and input character deletion pattern data forming circuits 43F and 43G for the pull input signal QDSR, and a comparison circuit 43H is provided as the opening/closing control signal. Comparison outputs RER and IER are provided, and when there is a mismatch, the gate is opened and the residual error is written.

(G5-6) Residual calculation circuit section 45 As shown in FIG. 24, the residual calculation circuit section 45 converts the standard character erasure pattern data REFA sent from the pattern matching circuit section 41 into a standard character erasure pattern matrix conversion circuit 46A is manned.

This standard character erasing pattern matrix conversion circuit 46A scans the standard character erasing pattern data obtained in the pattern matching circuit section 41 in the X direction for all odd lines and even lines with respect to the standard character pattern obtained based on the X direction scanning. After writing the standard character erasing pattern for one character by writing in order,
By reading out the standard character erasure pattern for one character in the order of the Y scanning direction, the X direction erasure pattern is
Standard character rotation deletion pattern data R similar to rotated
FQ is output and latched one bit at a time in a latch circuit 46B having a flip-flop circuit configuration.

By the way, as described above with reference to FIG. 19, the standard pattern set circuit 13B is connected to the
After reading out the X-direction standard pattern data from the Y-direction standard pattern dictionary section 13C2, the Y-direction standard pattern data is read out from the Y-direction standard pattern dictionary section 13C2. The pattern data REFA arrives in the order of the X-direction standard character erasing pattern data and the X-direction standard character erasing pattern data.

Therefore, at the timing when the first data of the X-direction standard character erasing pattern data arrives as the standard character erasing pattern data REFA, after the X-direction standard character erasing pattern data has been written in the standard character erasing pattern matrix conversion circuit 46A without excess or deficiency. , it is the timing to read the first data.

Using this relationship, standard character erasing pattern data RE
The FA is latched one bit at a time in a latch circuit 46C having a flip-flop circuit configuration.

The latch output data of the latch circuits 46B and 46C is applied to an AND circuit 46D, and the AND output is latched into a latch circuit 46E having a flip-flop circuit configuration.

In this way, the X-direction standard character erasing pattern data at the same coordinate position as the coordinate position of each bit of the X-direction standard character erasing pattern data that is sequentially arriving as the standard character erasing pattern data REFA is read from the standard character erasing pattern matrix conversion circuit 46A. By outputting the data and performing an AND operation in the AND circuit 46D, the X-direction standard character erasing pattern and the Y-direction standard character erasing pattern are finally determined.
When there are strokes remaining at the same coordinates that are not erased,
The logic “1” data for the bit concerned is the latch circuit 46.
It will be latched to E.

The erasure pattern data for one line of 24 bits latched by the latch circuit 46E in this way is given to the residual data calculation circuit 46F having a conversion ROM configuration, and is applied to the remaining strokes of the erasure pattern for one line. The data is converted into included dot number data and input to the standard character total residual data forming circuit 46G.

This standard character total residual data forming circuit 46G is composed of an addition circuit that dynamically stores the addition result by feeding back the addition output to the addition input terminal.
Thus, when residual data for 24 lines (that is, one character) is sent out from the residual data calculation circuit 46F, the total number of residual bits is calculated and sent out as standard character total residual data Z N RD.

The above configuration is a processing circuit for the standard character erasing pattern data REFA, but the input character erasing pattern data I
Similarly, an input character erasing pattern matrix conversion circuit 47A is prepared for NA, and latches the manually-powered character rotation erasing pattern data INQ in the latch circuit 47B, and also inputs the manually-powered character erasing pattern data INA representing the Y-direction input character erasing pattern. is latched into the latch circuit 47C,
The logical product data is obtained in a logical product circuit 47D and is supplied to an input character total residual data forming circuit 47G via a latch circuit 47E and a residual data calculation circuit 47F.

In this way, the input character total residual data ZNID can be obtained from the input character total residual data forming circuit 47G.

(G5-7) Effect In the above configuration, the subclassification identification unit 13 forms line data by executing software calculation processing using the CPU in the standard pattern set circuit 13B and the input cover turns set circuit 13D. are a stroke extraction operation in the stroke extraction circuit section 33, a pattern matching process in the pattern matching circuit section 41,
Since the residual calculation in the residual calculation circuit section 45 can be processed by hardware by providing a unique data processing circuit, the data processing time required for subclassification processing can be reduced overall by software. Compared to the case where the calculation process is performed manually, the time can be significantly shortened.

Accordingly, in the stroke extraction circuit section 33,
By coordinating the input operations of the character part of the standard pattern and the input cover pattern, the 1547 minutes of pattern data set in the shift registers 31° and 321 of the standard pattern set circuit 13B and the input cover turns set circuit 13D are made to cooperate. The data processing operation in the data processing circuit at the subsequent stage that processes the stroke extraction result data can be executed on a stroke-by-stroke basis, thereby making it easier and faster.

In addition, in the pattern matching circuit section 41, when a match is obtained in the standard character pattern stroke deletion circuit 43D and the input character pattern stroke deletion circuit 43H based on the width of the stroke and the position coordinates of the center,
By not sending the boar stroke data to the subsequent stage, it is easy to realize a circuit configuration that can erase matching strokes from the standard character pattern and the input character pattern within a short processing time using a simple configuration. It is possible.

Furthermore, by using the standard character erasure pattern matrix conversion circuit 46A and the input character erasure pattern matrix conversion circuit 47 as the residual calculation circuit section 45, residual data is generated from the erasure pattern scanned in the X direction and the erasure pattern erased in the X direction. When obtaining the result, it is possible to easily realize a residual arithmetic circuit that can perform an AND operation with a relatively simple configuration and can significantly shorten the processing time.

[G6] Other embodiments (1) In the above embodiment, when performing matching processing between an input character pattern and a standard character pattern in subclassification processing, two lines of pattern data, that is, an even number line and an odd number line, are used. Although we have described the case where the matching process is performed using pattern data as a unit, the unit amount of pattern data during the matching process is not limited to this, and can be selected to various values, for example, 3.
Lines up to 24 lines can be selected as required.

Increasing the number of processing units in this manner inevitably increases the burden on the hardware configuration for processing them, but it is possible to further reduce the processing time for pattern matching.

(2) In the above embodiment, the case where one normalized character has the number of dots of 24 lines x 24 dots was described, but the size of the character is not limited to this, and the present invention can be widely used in various cases. applicable.

(3) In the above embodiment, a case has been described in which peripheral features are used as features to be used when broadly classifying input character information, but other features such as parameter features may also be used. Even in this case, the same effect as in the above case can be obtained.

(4) In the above embodiment, the major classification dictionary 12B
Header part data (DHDAT) A~(DHDAT
) Although the starting address of the memory area storing the candidate character code DO of the same feature quantity is used as the dictionary address data D3 of o, a predetermined address other than the starting address may be used.

(5) In the above-mentioned embodiment, the center positions of the strokes are compared in order to detect stroke coincidence, but instead of this, the stroke position may be selected at a position other than the center position. good.

H Effects of the Invention As described above, according to the present invention, for special characters whose parameters have special characteristics, candidate characters are selected based on the parameter characteristics, thereby further increasing the identification rate of the special characters. be able to.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the character recognition section, Fig. 2 is a block diagram showing the overall structure of the character recognition device, Fig. 3 is a plan view showing an example of input characters, and Fig. 4 is a block diagram showing the structure of the character recognition device. Figures 5 and 6 are route maps for explaining the feature quantities of edges, Figures 5 and 6 are route maps for explaining scanning of input character patterns and standard character patterns, Figure 7 is a route map for explaining the principle of pattern matching; Figure 8 is a route map showing the erasure processing procedure used in pattern matching, Figure 9 is a route map explaining the causes of variation in character patterns, Figure 10 is a block diagram showing the specific configuration of the character identification section, Figure 11 is a route map for explaining pipeline processing, Figure 12 is a route map showing parameters for special characters, Figure 13 is a route map showing vertical characters, and Figure 14 is a diagram showing the configuration of a major classification processing circuit. A block diagram, FIG. 15 is a pro-rough diagram showing the configuration of the candidate character search circuit, FIG. 16 is a route map for explaining the procedure for selecting candidate character codes, and FIG. 17 is a route map showing the data structure of the major classification dictionary. , FIG. 18 is a block diagram showing the configuration of the subclassification identification section, FIG. 19 is a block diagram showing the configuration of the standard pattern set circuit, FIG. 20 is a block diagram showing the configuration of the input cover turns set circuit, and FIG. 21 22(A) and CB) are signal waveform diagrams for explaining the classification processing operation. FIG. 23 is a block diagram showing the configuration of the pattern matching circuit. FIG. 24 is a block diagram showing the configuration of the residual calculation circuit section. 1...Character recognition device, 2. ...Image scanner section, 3...Print document, 4...
・Character identification unit, 5...Display device, 11...
...Input/output processing section, 12...Major classification identification section, L
2A...Major classification processing circuit, 12B...
Major classification dictionary, 13... Subdivision identification section, 13A.
... Normalization processing circuit, 13B ... Standard pattern set circuit, 13C ... Subdivision dictionary, 1
3D...Input cover turnset circuit, 13E...
. . . Detailed classification processing circuit, 14 . . . Determination processing section.

Claims (1)

[Claims] An input character is cut out from image information, and parameter features are extracted from character parameters of the cut out input character, and when the cut out input character is a normal character based on the parameter feature, the cut out input character is a normal character. After selecting a first candidate character through a major classification process based on the image information of the cut out input character, a subclassification process is performed on the first candidate character, and the first candidate character is selected based on the parameter characteristics. A character recognition device characterized in that when an input character is a special character, a second candidate character is selected, and the subclassification process is performed on the second candidate character without performing the major classification process.