JPH01277987A - Character recognizing device - Google Patents

Abstract

PURPOSE:To increase the reading speed of a candidate character and to increase the identification(ID) speed of a character recognizing device by including the feature variable of input character information as header data part of a rough sort dictionary. CONSTITUTION:A character recognizing part 4 extracts a feature variable from an input character information and reads out a candidate character code having the feature variable from the rough sort dictionary 12B to execute recognition processing. The rough sort dictionary 12B is provided with a header part data capable of reading out the candidate character codes of plural candidate characters having the same feature variables as the extracted feature variable by accessing a feature code indication the feature variable as an address. Thus, the feature variable of the input character dictionary can be directly used as the reading information of the rough sort dictionary 12B without converting any feature variable of the input character information and the ID speed of the character recognizing device by increasing the reading speed of the candidate character.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology G. Examples [G1] Principle structure of character recognition device (Gl-1) Overall structure (Fig. 1, Fig. 2) (Gl-2)
Major classification identification processing (Figs. 1, 3, and 4) (Gl-3) Subclass identification processing (Fig. 1, 5 to 9) [G2] Pipeline, parallel processing (Fig. 1 , FIG. 2, FIG. 8, FIG. 10, and FIG. 11) [G3] Character extraction processing circuit (FIG. 1, FIG. 3, FIG. 4, FIG. 10, FIG. 12, and FIG. 13) (G3-1) Extraction of character parameters (Figures 1, 10, and 12) (G3-2) Selection of special character candidates (Figures 1, 10, and 12)
and Fig. 13) [G4] Major classification processing circuit 12A (Fig. 1, Fig. 3, Fig. 4)
(Fig. 10, Fig. 14 to Fig. 17) [G5] Subclassification identification section 13 (G5-1) Overall configuration (Fig. 18) (G5-2) Standard pattern set circuit 13B (Fig. 10 and (Fig. 19) (G5-3) Input cover turnset circuit 13D (Fig. 1O, Figs. 17 to 20) (G5-4) Stroke extraction circuit section 33 (Fig. 7, Figs. 19 to 22) ) (G5-5) Pattern matching circuit section 41 (FIGS. 7, 18, 21, and 23) (G5-6) Residual calculation circuit section 45 (FIGS. 19 and 24)
(G5-7) Effects (Figures 1 to 24) [G6] Other Examples H Effects of the Invention A Industrial Application Field The present invention relates to a character recognition device, particularly when recognizing printed characters. It is commonly used and suitable.

B. Summary of the Invention The present invention enables a character recognition device to read out candidate character codes by accessing the header section using feature quantities, thereby easily and quickly reading out candidate characters for input character information. I can do it.

C. Conventional technology In the past, it has been proposed to digitize and file a large amount of printed documents, or create a database to build an information network that can be used for a variety of purposes. In place of character information input devices that require input operations, character recognition y that does not require manual input operations! a
It is considered to use a device.

In general, a printed character recognition device optically reads printed characters on a printed document, digitizes them as two-dimensional image information, extracts the printed characters from the image information, and outputs the corresponding character code. is being done.

By encoding image information into character codes in this way, you can search for words using a computer,
It is possible to realize a document processing system that automatically executes decoding processing such as understanding meaning.

In this way, for example, it is possible to compress the data extracted from the image information and use it for decoding processing as necessary, thereby making it possible to improve the document processing speed as necessary.

Problems to be solved by the invention However, the currently used printed kanji recognition devices actually have a recognition rate of about 97 to 99% and a recognition speed of 20 to 99%.
It only has a function of about 30 characters/second, and is still insufficient as an input means for digitizing a large amount of printed documents.

In order to solve this problem, conventional features of input characters (for example, peripheral characteristics on four sides) were extracted from image information.
), the most similar characters are selected by performing major classification processing to select candidate characters from the major classification dictionary by detecting feature amounts based on A character recognition method has been proposed that determines the
Publication No.).

The present invention has been made in consideration of the above points, and by devising a method for reading out a major classification dictionary, it is possible to further speed up the reading of candidate character codes.

Means for Solving Problem E To solve this problem, in the first invention, the feature amount is calculated from the input character information SIN, □ is extracted, and candidate character codes DO having this feature amount DcH are roughly classified. Dictionary 12
In a character recognition device configured to read from B (
Figure 1, Figure 3, Figure 4, Figure 17), major classification dictionary 12
By accessing the feature code Dl representing the feature amount Dcn* as an address, B can obtain ffilDcm at that time.
Candidate character codes D of multiple candidate characters having the same feature amount as
Header data (DHDAT) A~(
DHDAT) o.

Further, in the second invention, in addition to the above-mentioned configuration, header part data (DHDAT)A~(DHDATT)
In addition to the feature code DI representing the feature IDC□, o is
Character code section data including candidate character code data (D
Dictionary address data D3 representing the address of ICDAT)A to CDICDAT)o, feature quantity, and HR
and candidate number data D2 of candidate characters having the same feature amount.

The feature quantity D CMII that the input character information SIN has through the F-action major classification process is transferred to the header part data (DHDAT) a to (DHDAT) of the major classification dictionary 12B. As a result, the feature value DC□ of the input character information SIN can be used without any conversion and directly used as successive information in the major classification dictionary 12B.

Since the feature amount Dcm of the input character information SIN can be directly used as access data for the major classification dictionary 12B, the speed at which candidate characters are successively produced can be increased, thereby further increasing the identification speed of the character recognition device as a whole. can be converted into

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

[G1] Principle configuration of character recognition device (Gl-1) Overall configuration In Fig. 2, l indicates the character recognition device as a whole,
The image scanner section 2 optically reads the supplied printed document 3 automatically or manually and provides two-dimensional image information INF to the character identification section 4 .

The character identification unit 4 identifies characters included in the image information INF and sends out character identification output data DATA, which is supplied to a host computer of a document processing system, for example, and also supplies display data DISP to a display device 5. do.

As shown in FIG. 1, the character identification section 4 receives the image information INF supplied from the image scanner section 2, and distinguishes between normal characters of normal size and shape (in contrast, small characters, horizontally long characters, etc.). Characters such as vertically long characters are called special characters)
Selecting similar characters having the same characteristic parts as the input characters as candidate characters from the characters to be identified stored in the major classification dictionary by performing a major classification process on the candidate characters, and then performing a subclassification process on the candidate characters. determines the closest character. Thus, the character identification section 4
Highly accurate character recognition can be achieved by executing hierarchical classification processing consisting of major classification processing and subclassification processing.

That is, the character identification section 4 receives the image information INF at the input/output processing section 11 . The input/output processing section 11 has a central processing unit (CPU), cuts out input characters to be subjected to identification processing from the image information INF, and sends them to the large classification processing circuit 12A of the large classification identification section 12 and the subclassification processing circuit 12A. It is sent to the normalization processing circuit 13A of the section 13.

(Gl-2) Major classification identification process As shown in FIG. 3 and FIG. (referred to as side A and side B)
The first and second peripheral features seen from the WAKUA and W A K U m sides, and the upper side and upper side (these are referred to as the 0 side and the D side) W A K U c and W A
Based on the third and fourth peripheral features seen from K U o, a special @t (expressed as a vector quantity) DcH* is generated by encoding the character structure created by the black character part against the white background. , candidate characters consisting of similar characters are selected based on this feature quantity DCHR.

Note that Japanese Unexamined Patent Publication No. 186390/1984 describes a method of character recognition based on peripheral characteristics.

The peripheral feature on the A side is that when the black character part of the third dot line along the left side MOJIa of the input character MOJI is viewed from the direction indicated by the arrow ARA, the black character part to the left of the dot line L. The lengths ds, , ds, , dS, are encoded and the feature quantity DC is
Form □.

In the case of Fig. 4, the length C of the scanning start part (this is called the start corner) at the upper left corner of the left character part MOJIA
A fairly long s can indicate that there is no dot in the upper left corner.

On the other hand, since the length C0 of the lower left corner at the end of scanning (this is called the end corner) is short, it can be indicated that there is a dot at the end corner.

In the case of this embodiment, the length C3 of the start corner is calculated by logically converting the data B0 of the 0th bit of the feature amount D CHR when the following formula is satisfied: BO=rlJ ・Old... As in (2), the length C3 of the start corner is When set to "1" and the condition of equation (1) does not hold, B, = rOJ... (3
), the 0th bit data B0 is set to logic "0".

Regarding the length C1 of the end corner, when the following condition holds, the data B of the first bit of the quantity DCHII is expressed as shown in the following formula (5).

is set to logical "1", and when the condition of equation (4) does not hold, B, = rOj... (6)
Set.

Start corner length C3 and end corner length C0
In the interval between, the length of the black character part ds, , dS
t -...d s, (n=3 in Figure 4)
is generated, but the length of each black character is ds, , dst...
2nd, 3rd, etc. (n+
1) Dot data Bt, Bs...B, l*
1 is set as the logic rOJ, as shown in FIG.

In this way, the characteristics of the start corner and the end corner are incorporated into the data B of the Oth and first bits of the feature quantity D Ca1l, and B1, and the data B of the second, third, . . . , (n+1)th bits are incorporated. , , B3...B
, l+1, information representing the arrangement order of dots and segments is taken in as the arrangement state of the black character portion.

In this way, all the features of the black character part on the A side are encoded, and the data of the logic rlJ is set in the (n+2)th bit following the last bit as shown in the following equation (10).

In this way, the peripheral feature of side A is converted into a feature quantity D CHI coded as a variable length code,
At this time, @'IkDcH* represents first-order (i = n + 2) vector data, and the decimal feature value numerical data VALoc is expressed by the conversion formula of the following formula % formula % (11)
Convert to m. This feature value numerical data VALDcHI
I is the feature amount D of the standard character in the major classification dictionary 12B (Figure 1)
C□ is stored as information representing C□, and candidate character information 5cAD representing similar characters is retrieved from the major classification processing circuit 12A by reading this as necessary and comparing it with feature value numerical data VALDCNI for the input character MOJ[. The information is sent to the classification identification section 13.

In this embodiment, the major classification processing circuit 12A uses the feature amount D
The order i of the CHI vector is i≧7 (12
), when the upper limit value is 7 or more, the feature quantity numerical data VALゎCME is set to VALDCHI = 128 --
By classifying the human characters into numerical data 128 as shown in (13), the human characters are processed as characters belonging to a "complex pattern" (instead of selecting candidate characters for each character).

The major classification dictionary 12B receives input character information SI from the input/output processing unit 11 by reading standard printed characters (normal characters) to be identified character by character using the image scanner unit 2.
After obtaining N, in the major classification processing circuit 12A, (11
) and (13), the feature value numerical data VAL
oc and * are calculated for sides A to D, respectively, and registered together with the character code.

In this way, for all the characters to be identified (for example, 4000 characters), the standard character code that has common peripheral features for each side A to D is the feature value numerical data VALゎc.
The information is roughly classified according to (1) and stored in advance in the major classification dictionary 13B.

In this state, when input character information SIN arrives at the major classification processing circuit 12A via the input/output processing unit 11 by reading a document with the image scanner unit 2, the major classification processing circuit 12A inputs the feature value value of the input character information SIN. Find the data VALDcHII and select the candidate character code having the feature value numerical data VALocN* from side A to D.
Pull out each side from the major classification dictionary 12B and select side A or D.
The standard character codes that have become candidate characters for all sides are sent to the subclassification identification unit 13 as candidate characters [Blue Report SCAD].

The character information drawn from the major classification dictionary 12B here is
Each side A to D is a union of characters having the same feature value D CHI, and the major classification processing circuit 12A calculates the candidate character code represented by the common term (i.e., the intersection set) of all the unions of each side. is sent as candidate character information SCAEI.

This means that instead of checking whether all of the features of each side of the input character exactly match the features of the target character, there is a match of one or more peripheral features for each of the four sides. By checking whether the candidate characters are the same or not, candidate characters can be narrowed down with sufficient accuracy for practical use through a relatively simple and short-time broad classification identification operation. According to experiments, on average 24.04 out of 4000 characters
This makes it possible to select candidate characters, thereby making it possible to perform the classification process in the subclassification identification section 13 much more easily and in a shorter time in practical terms.

Incidentally, as actual examples of candidate characters for input characters, the following candidate characters can be selected.

[Example 1] Two candidate characters, ``in-misaki'', were selected for the input character ``in''.

[Example 2] Twelve candidate characters were selected for the input character ``print'', ``Old Kinucha Printing Regulations Koibetsume Yoro''.

[Example 3] For the input character "Bun", 60 candidate characters "Aamei Ei Eno Okuhi Kankan Takamoxibustion Exploration Secrecy dog test I was able to select Zhongzang Food Responsibility, Tai Tai, Daimushiku, Mugibi, Omotefu, Bunpei, Maya, Yukoshi, and RokuJ.

[Example 4] 57 candidate characters for the input character ``character''. I was able to select ``A professional graduate who is a ruthless teacher and an emperor who is not good at his job.

(Gl-3) Subclassification Identification Process The subclassification identification unit 13 (FIG. 1) uses the input character information SIN about normal characters manually inputted from the input/output processing unit 11 as candidates sent from the major classification identification unit 12. literary circumstances tgsc
By performing a pattern matching process on the candidate character represented by ao, a process is performed to select a candidate character most similar to the input character from among the candidate characters selected in the major classification process.

In this subclassification process, first, the input character information SI is passed from the input/output processing unit 11 to the normalization processing circuit 13A.
As shown in FIG. 5, N is converted into an input character pattern PT, which is a character pattern composed of 24 x 24 dots, and this input character pattern PT, , is converted in the same way as shown in FIG. Pattern matching is performed by performing matching processing with a standard character pattern PTST configured as a 24×24 dot character pattern.

In the case of this embodiment, the cover turns set circuit 13 receives human cover turn data DPTIN consisting of dot data of the input character pattern normalized by the normalization processing circuit 13A.
At the same time, the standard pattern data DPTST representing the dot arrangement of the standard character patterns PT, , for characters to be identified is stored in advance in the subclassification dictionary 13C, and this is read out character by character by the candidate literary situation N5cAo. It is designed to be set in the standard pattern set circuit 13B.

In this way, the standard pattern and input cover turn data D, A, T and DPTIN set in the standard pattern set circuit 13B and the input cover turns set circuit 13D are processed in the subclassification processing circuit 13E as shown in FIGS. 5 and 6. , are sequentially read out while scanning in the X direction (that is, horizontal direction), and are processed to align the strokes (consisting of an array of black dots) in the X direction (first alignment process), and the Y By scanning in the direction (that is, the vertical direction), processing is performed to match the strokes in the Y direction (second matching processing).

For each scanning line in the X direction and the Y direction, the subclassification processing circuit 13E calculates strokes P TINI , P as input character patterns PT, N, as shown in FIG. 7, for example.
Input cover turn data DPTIN having T+Hz and P T+1lff is input to the input cover turns set circuit 13D.
When the standard pattern data D ptst having the strokes P Tsrl and P Ts□2 as the standard character pattern PT'st is set in the standard pattern setting circuit 13B, the input character pattern PT, ,
Stroke P T 181 , P T +s□, P
Regarding TIN3, its starting point coordinate IS and ending point coordinate IS
, and find its width WIS and center coordinate ISa. At the same time, the subclassification processing circuit 13E similarly detects the stroke starting point position 11iRs and the ending point coordinate R8t for the strokes PTst+ and PTstz of the standard character patterns PT, , and calculates the stroke width Wlls and the center coordinate R3o.

Based on the calculation results, the subclassification processing circuit 13E classifies each stroke PTINI s of the input character pattern PTIN.
P TIN! , P Stroke width Wl of Tl83.

and the center value Is, respectively, are sequentially converted into a standard character pattern P
The stroke PTstr of Tst is compared with the stroke width WllS and center value R5 of PTS2, and when the deviation is within the range of the predetermined stroke width threshold level WtH and the center value threshold level CTH, the strokes are matched. Execute matching processing that determines that the result has been achieved.

In the case of this embodiment, the subclassification processing circuit 13E is configured to perform such matching processing according to the processing procedure shown in FIG.

For example, by inputting the input text information M S IM representing the character "book" as the input character pattern P T I N, the major classification identification unit 12 selects two characters "hon" and "木" as the candidate character information S eAD. Standard character pattern P representing
When Ts□ and P'rSTll are input, the sub-classification processing circuit 13B reads the input character pattern PTIN and the loading truck character patterns PTSTA and PTst++, and then first reads the standard character patterns PTstA and P'rSTll, In addition to executing processing to match the human input character pattern PTIN based on the second input character pattern PT,
Standard character patterns PTsA and PTs based on N
Executes processing to match rm.

That is, first, if the input character pattern PTIN has strokes that match the written standard character patterns PTsyA and PTst+, the subclassification processing circuit 13E converts the data of the matched strokes into the standard character patterns PTstA and PTst+. Standard character pattern that was deleted from the data of PTsts and remained without being deleted P T stA
, P T srs, a standard pattern reference X-direction erasure pattern ER,l,A, , ERXZA is obtained.

Second, among the input character patterns PTIN taken into the subclassification processing circuit 13E, by erasing strokes that match the standard character patterns PT, A, and P Tlyl, the input cover turn reference X direction deletion pattern E
Obtain RX□A, E RX2m.

In addition to this, the subclassification processing circuit 13E similarly converts the standard character pattern PT with respect to the rotated cover turn PTIMY, which is obtained by rotating the input character pattern PT by 90 degrees counterclockwise.
Similarly, two-step matching processing is performed on rotated standard patterns PTs□7 and PTsymy, which are obtained by rotating syA and PTstm counterclockwise by '90 degrees.

In this embodiment, the rotation standard patterns PT, TAv and PTstmy are the standard character patterns PTstA and PT9.
, 1 are stored in advance in the subclassification dictionary 13G.

Thus, the standard pattern reference Y direction erased patterns ERy+A and ERttm obtained by erasing the rotation input cover turns PT and HV from the rotation standard patterns PTiyAv and PTstsy in the same manner as the alignment process in the X direction, and the rotation reference pattern PTstav from the rotation input cover turns PTINV. and PT, □, to obtain input cover turn reference Y direction erasure patterns ERvtA and ERvtm.

Thus, the four X-direction erasure patterns ERXIA-, E obtained as a result of the matching processing in the X-direction and the Y-direction
RXlm, E RxzA-E Rxtm, and Y-direction erasure pattern ERv-tASERy+s, ERV2
By calculating the logical product with A and ERvts, the subclassification processing circuit 13E calculates the corresponding four residual patterns ERT
IA, ERttm, ERtza, ERttm
seek.

Here, the X direction erase pattern ERx+a, ER□8, E
RXZA, ERX! l and Y direction erasure pattern ER□
a, ERYII, Eryta, ERvtm, X
Since it represents the stroke part that could not be matched when scanning in the X direction and the Y direction, the calculation result obtained by performing the AND operation is the stroke part that could not be matched in both the X direction scanning and the Y direction scanning. After all, the residual pattern ERT1A,
ERT+3, ER2A, and ERTtm represent the number and position of dots that could not be matched between the human character pattern P T I N and the standard character patterns PTSTA and P'Fsyll.

The subclassification processing circuit 13E calculates the sum of the dot numbers of the residual patterns ERTIA and ERoA, ERT, I, and ER, □ obtained for the standard character patterns PTstA and PTsys, respectively, in this way, and calculates the result of the calculation. Input character pattern PT, , and standard character pattern PTst
It is sent to the determination processing unit 14 as residual data D□ representing the pattern matching result between A and PT, □ (the first
figure).

The determination processing unit 14 converts the numerical value represented by the residual data DE11 into
Evaluate the score obtained for each candidate character as a result of the subclassification process,
Judgment result data S1. Send as.

In this embodiment, the input/output processing unit 11 displays the judgment result data 5ILE3 regarding the first recognized character on the display device 5 so that the operator can visually confirm the first recognized character. is not appropriate,
It is possible to use characters recognized in the second place or lower. In practice, this almost eliminates misrecognition.

By thus obtaining the residual pattern based on the AND result of the erasure patterns in the X direction and the Y direction, the input character pattern PTIN and the standard character pattern PTsr are If there is a phase change between the input character pattern PTIN and the standard character pattern PT, as shown in No. 9 [N (B),
Even if there is a variation in line width between the two patterns, pattern matching processing can be performed with high accuracy in practice while absorbing the effect.

[G2] Pipeline, parallel processing Based on the above-mentioned principle configuration, the character recognition unit 4 (Fig.
FIG. 2) is from the character extraction process of the input/output processing section
Major classification processing in the major classification identification unit 12, detailed classification identification unit 1
Normalization processing and subclassification processing in 3, determination processing unit 14
The configuration is such that image information INF can be processed at high speed by processing the determination process in a pipeline and parallel processing.

That is, the character identification unit 4 performs character extraction processing, major classification processing, standard pattern set processing, normalization processing, and input cover turns set processing, as shown in FIG. , subclassification processing, and determination processing are configured in a hierarchical structure so that pipeline processing can be performed.

That is, the input/output processing section 11 has an input/output processing circuit body 11A having a CPU configured as a microcomputer, and by latching the character extraction information 5INX to output circuits 11B and 11C having a dual port register configuration,
It is designed so that it can be delivered to the major classification processing circuit 12A and the normalization processing circuit 13A.

In this way, as shown in FIG. 11, the input/output processing circuit main body 11A starts the extraction process for the first character at time ti, and then finishes the first character extraction process and outputs the character extraction information 1slNX. Output circuit 11
At time t2 after latching to B and IIC,
Character extraction processing for the second character can be started.

Thereafter, in the same manner, the input/output processing circuit main body 11A is operated at time t3,
In L4..., the previous time points t2 and t3
Every time the character cutting process started in .

The character cutting information S INK latched in the output circuits 11B and 11C in this way is output to the major classification processing circuit 12, respectively.
Main classification processing circuit body 12 of A and normalization processing circuit 13A
A1 and the normalization processing circuit main body 13A1.

The major classification processing circuit main body 12A1 has a CPU configured as a microcomputer, takes in the character cutting information 5INX stored in the output circuit 11B as input character information SIN, and executes major classification processing on the input character information SIN. , the resulting candidate character information data SC
ADX first-in-first-a-ra) (FIFO)
By latching it to the output circuits 12A2 and 12A3 of the circuit configuration, it is possible to deliver it to the standard pattern set circuit 13B of the subclassification identification section 13 as the candidate document information 115eAo.

On the other hand, the normalization processing circuit main body 13A1 has a CPU configured as a microcomputer, and input character information SIN.
is read and normalization processing is performed, and each input cover turn data DP? obtained as a result is read. 1NX is sent to the output circuit 13A2 having a FIFO circuit configuration. Thus, the output circuit 13A
2 is each input cover turn data DP? When it receives l□, it passes it to the input cover turn set circuit 13D as input cover turn data Drt+N.

In this way, the major classification processing circuit body 12A1 of the major classification processing circuit 12A and the normalization processing circuit body 13A1 of the normalization processing circuit 13A simultaneously execute the major classification processing and the normalization processing independently from each other in parallel. Candidate character information S CAD and input cover turn data [) pt can be delivered to the standard pattern set circuit 13B and input cover turn set circuit 13D at the same timing.

The processing operations of the major classification processing circuit main body 12A1 and the normalization processing circuit main body 13A1 are similar to those of the input/output processing circuit main body 11A.
In this way, the input/output processing circuit main body 11A can perform the next processing without waiting for the processing power q of character information being processed in the main classification processing circuit main body 12A1 and the normalization processing circuit main body 13A1 to increase. Executes extraction processing for characters in parallel and simultaneously.

The standard pattern set circuit 13B and the input cover turns set circuit 13D each have a microcomputer configuration.
It has a PU and is configured to be able to execute processing operations independently and in parallel.

Thus, while the standard pattern set circuit 13B reads the standard character pattern for the candidate character specified by the candidate character information 5cAtl and executes the setting process, the input cover turns set circuit 13D simultaneously reads the input cover pattern data DPTIN. Executes set processing.

When input cover pattern data DPTIN starts to be set in the standard pattern set circuit 13B and the input cover turns set circuit 13D, the subclassification circuit main body 13E1 of the subclassification processing circuit 13E reads it and executes subclassification processing. Here, the subclassification circuit main body 13E1 is constituted by a dedicated hardware circuit, and thereby the standard pattern set data D is sent from the standard pattern set circuit 13B and the input cover turns set circuit 13D according to the scanning direction (that is, the X direction or the Y direction).
I? IE? and input cover turn set data D INK!
? are sent out in time series, the standard pattern reference residual patterns ERfIA, ER7, (8th
Figure) data as residual data D. At the same time as closing and sending out,
Similarly, the input pattern reference residual patterns E Ryza and E Rt are output through the output circuit 13E3 having the FIFO circuit configuration.
The data of □1 (Fig. 8) is sent as residual data DE, I.

As a result, the detailed classification circuit main body 13E1 executes the detailed classification operation almost simultaneously with the standard pattern setting operation and the input cover turns setting operation, as shown in FIG.

The judgment processing circuit main body 14A of the judgment processing circuit 14 has a CPU configured as a microcomputer, takes in residual data Dt11 independently from other processing circuits, executes judgment processing, and performs judgment through an output circuit 14B having a FIFO circuit configuration. The result data S□ is delivered to the input/output processing circuit main body IIA.

This result determination processing circuit 14, as shown in FIG.
While the subclassification processing circuit 13E is executing the subclassification process, the judgment process is executed at the same time.

In the configuration shown in FIG. 1O, the input/output processing section 11 operates at time 1 in FIG. At time 1t after the processing is completed and the input character information SIN is delivered to the major classification processing circuit 12A and the normalization processing circuit 13A, the extraction processing of the second character is executed. Start the cutting process.

Similarly, time 1. ．． Immediately after finishing the character extraction process currently being executed in 14..., a new character extraction process is started.

In this way, when the first, second, third, etc. characters are cut out, each time the major classification processing circuit 12A
The normalization processing circuit 13A simultaneously executes the major classification processing and the normalization processing in parallel, and converts the candidate literary circumstances flscAn and the input cover turn data D□ into the standard pattern set circuit 13.
B and input cover turns set circuit 13D, and a state awaits the arrival of new input character information S+H.

At this time, the standard pattern set circuit 13B and the input cover turn set circuit 13D to which the candidate character information S CAD and the input cover turn data Dl'TIN are delivered, while executing the pattern setting operation, set the standard pattern set data Dstsit and the input cover turn data. The set data D and A are sent to the subclassification processing circuit 13H, and the subclassification processing circuit 13E
This is subjected to subclassification processing almost in real time and the residual data D- is delivered to the determination processing circuit 14. When the processing operation is finished, the standard pattern set circuit 13B
And the input cover turnset circuit 13D is new candidate character information Sc^. Then, the process returns to the state where it waits for the input cover turn data Drt+w to be generated.

The judgment processing circuit 14, which has been handed over the residual data D□, executes judgment processing and outputs the character code for the first extracted character to the input/output processing unit 11 as judgment result data SRES. The process returns to the state of waiting for the residual data DEI+ to be delivered.

In this way, the processing operations for the first character are performed in sequence (input/output processing section 11) - (major classification processing circuit 12A, normalization processing circuit 13A) -1 standard pattern set circuit 13B, input cover patterns set circuit 13D ) - subclassification processing circuit 13E
)-(judgment processing circuit 14).

Such pipeline processing is started every time the input/output processing unit 11 extracts a new character, and thus the pipeline processing operations for multiple characters are executed in parallel and simultaneously.

In this way, according to the configurations of FIGS. 10 and 11,
When data to be processed sequentially is generated, each processing means arranged in a hierarchical structure is processed simultaneously (each performs a different job), thereby increasing the efficiency of the multiple processing means that make up the character recognition device. By being able to operate the character recognition processing operation, the overall speed of the character recognition processing operation can be further increased.

According to experiments, the recognition speed of a printed document, which was previously processed at a speed of several characters/second in a character recognition device configured to perform sequential processing, was increased to around 100 characters/second using the above-described configuration.

In the case of this embodiment, the main classification processing circuit main body 12A1 generates candidate character number information S CA as candidate character data S CADX.
The DH is latched in the output circuit 12A3, and is directly delivered to the judgment processing circuit main body 14A without passing through the standard pattern set circuit 13B and the subclassification processing circuit 13E,
This notifies the determination processing circuit main body 14A of the number of times the determination processing should be repeated.

At the same time, the major classification processing circuit main body 12A1 returns the same candidate character number information S CADN to the input/output processing circuit main body 11A via the output circuit 11B.
1 normalization processing circuit main body 13A1 and the output circuit 13A2 in order to inform the input cover turnset circuit 13D to supply information for matching the timing with the processing operation of the standard pattern setting circuit 13B.

[G3] Character extraction processing circuit (G3-1) Extraction of character parameters In the above description, the case where the input/output processing section 11 extracts normal characters has been described, but in addition to this, the input/output processing section 11 also performs the following:
It is designed to cut out special characters such as vertically long characters, horizontally long characters, and small characters.

That is, the input/output processing circuit main body 11 of the input/output processing section 11
A is the input character M from the image information INF supplied from the image scanner unit 2, as shown in FIG. 12(A).
OJI is cut out using the circumscribing frame WAKU, and character parameters of the cut out input character MOJI are extracted.

Here, the character parameter and meter are 15-byte character parameter data DM, which is the size and position information of the character cut out based on the circumscribing frame WAKU of the input character MOJI, as shown in FIG. 12(A). , and extract.

Character parameter data D. , l, the character parameters W and H represent the width and height of the circumscribing frame WAKUO.

Character parameters CNW to DLTH represent threshold data used when extracting feature amounts in the major classification processing circuit 12A, and are each selected to have the following values, for example.

HSW= □ ・・・・・・
(18) H3H= □ ・
... (19)DLTW= □
・・・・・・ (20) DLTH= □
(21) Character parameters W24 and H24 represent unit information when the input character MOJI is normalized in the normalization processing circuit 13A, and the following formula % formula % (22) For this, Character parameters WRT, HCNT.

HRT is data representing the shape and position of a character, and character parameter WRT represents the aspect ratio of the input character MOJI as shown in the following formula % formula % (24). Therefore, shape information such as whether the input character is horizontally long or vertically long can be obtained from the character parameter WRT.

In addition, the character parameter HCNT is calculated using the following formula: %formula% represents the center position of the input character MOJI.

Here, HL represents the distance from the highest height position to the lowest height position of all characters in the line containing the input character MOJI (this is called the maximum length).

Thus, the character parameter HCNT in equation (25) represents the center position of the input character MOJl in the maximum length HL of the line.

The character parameter HRT is the input character MOJI for the maximum length H4 as shown in the following formula.
represents the ratio of the height of the input character MOJI.
It is possible to know whether the height of the object is low or not.

(G3-2) Selection of special character candidates The character extraction circuit 11AI of the input/output processing circuit main body 11A (FIG. 10) receives character parameter data D. Based on Jl, the input character MOJI is a character that has a normal size and shape for the maximum length HL (i.e., a normal character) or a character that does not have a normal size and shape (i.e., a special character). Determine if there is an input character MO
If JT is a normal character, the cut out character MOJ
■Enter the image information as it is ff! s+, 4
It is delivered to the major classification processing circuit 12A via the output circuit 11B.

Thus, the character identification unit 4 as a whole executes the pipeline processing for the above-mentioned normal characters.

On the other hand, the character cutting circuit 11AI
If it is determined that I is a special character, character parameter data DM. Jl is used to extract the features of the input character MOJI, and a special character code representing a special character candidate having the extracted character parameter features is read out from the special major classification dictionary 11A2 and output as human character information 81.4. It is delivered to the major classification processing circuit 12A via 11B.

The characters that are determined to be special characters here are "!", "1"
", "-", "-", "-", ",", ",", "・"
, "9", and are vertically long characters, horizontally long characters, and small characters, and are characterized by their positions in the height direction and width direction in addition to their shape and size.

Therefore, the character cutting circuit 11AI uses the character parameter data D1. Of loJ+, character parameter WRT ((2
(4) formula), HCNT ((25) formula), HRT ((2
6) using the following formula WRTX= -X32 (27
)−+y L (28), and using the evaluation data WRTX, WRTX>83...
... When (30), the input character MOJI is evaluated as "a vertically long character", and using evaluation data HCNTX, HCNTX>24 ...... (3
1), it is evaluated as “vertical and left-sided”, and the HC
NTX<12 (32)
When 12≦HCN, it is evaluated as “vertically long and to the right”
When TX≦24 (33), it is evaluated as “vertically long and close to the center”.

Furthermore, based on the evaluation data WRTX, the character cutting circuit 11AI evaluates that the input character MOJI is a "horizontal character" when the following formula % formula % (34), and uses evaluation 1 city data HCNTX to
>24 ・・・・・・ (3
5), it is evaluated as "horizontally long and upward", and HCNTX
<12 ...... (36), it is evaluated as "horizontal and downward", and 12≦HCNTX≦
24 When (37) is satisfied, the image is evaluated as "horizontally long and in the center."

Further, the character extraction circuit 11AI uses the evaluation data HRTX to evaluate that the input character MOJI is a "small character" when the following formula % formula % (38), and uses the evaluation data HCNTX to determine that HCNTX>24...・・・
...When (39) is evaluated, it is evaluated as "small font and located at the top (to the left in case of vertical writing)", and HCNTX<14 ......(
40), "Downward in small letters (to the right in vertical writing)"
14≦HCNTX≦24 (
41), it is evaluated as "small letters in the center".

The character cutting circuit 11AI selects a corresponding character code from the special major classification dictionary 11A2 based on the determination result.

The special major classification dictionary 11A2 classifies standard special characters based on the evaluation criteria of formulas (30) to (41) and stores them in advance with unique character codes.
About input characters MOJI from 1AI (30) 2 ~ (4
1) When the evaluation result of the expression is obtained, the standard special character code corresponding to the evaluation result is delivered to the character extraction circuit 11AI.

Here, as shown in FIG. 13, the character cutting circuit 11AI inputs the vertically written character MOJI as the image information INF, and replaces it with the evaluation data described above for equations (28) and (29) by using the following equation -+ y L ...... (42) is used.

According to the character cutting circuit 11AI described above, when cutting out the input character MOJT from the image information INF, the input character M
By extracting OJI character parameters and selecting special candidate characters based on these character parameters, it is possible to further improve the accuracy of special character identification.

Incidentally, it is also possible to perform hierarchical processing of major classification processing and subclassification processing for special characters, but since it is easier to understand the characteristics of special characters with parameter features than with ferrule features, It is thought that the identification accuracy will be higher if the major classification process is not used.

[G4] Major classification processing circuit 12A As shown in FIG. 12, the major classification processing circuit 12A includes a peripheral feature detection circuit 21A and a candidate character search circuit 21B.
It has a configuration in which a CPU 21C having a microcomputer configuration executes a major classification process according to a program in a program memory 21D.

That is, when the input character information S0 is latched in the output circuit 11B of the input/output processing section 11, the CPU 21C takes in the data via the bus 21E and the data buffer circuit 21F, and also reads the data via the address buffer circuit 21G and control buffer circuit 21H. program memory 2
1D and address recorder 211.

In the case of this embodiment, the peripheral feature detection circuit 21A extracts the feature amount DCHK from the input character information SIN (FIG. 4).
It has a hardware configuration including a conversion ROM for generating input characters MOJI (Figure 3), and converts the left side character part MOJIA, right side character part MOJIa, upper character part MOJ IC, and lower character part MOJIo. Feature quantity numerical data V representing each imported feature quantity D CMll
A Locn* (Equations (11) and (13)) are converted so that the quantitative numerical data ■ALl, c, Il can be sent to the bus 21E at high speed at that time.

The candidate character search circuit 21B sequentially searches A side, B side, 0 side,
When the feature quantity numerical data VALOC) Il+ of side D is sent out, it is taken in and candidate characters having the corresponding feature quantity numerical data V A L DCHI for each side are searched from the major classification dictionary 12B (Fig. 10). do.

In FIG. 15, candidate character search circuit 21B has candidate memory 23A.

As shown in FIG. 16, the candidate memory 23A stores candidate character codes assigned to all recognition target characters (in this embodiment, numerical values from "0" to r4095J are assigned as candidate character codes) as addresses. It has a 4-bit memory area.

The 11th and 2nd configuring the memory area of each candidate character code
, the memory areas of the third and fourth bits are A side, B side, 0
The 1-bit candidate display data CAD for the side and the D side can be stored, and the input/output processing section 11 (the 14th
Input character information for one character from (Figure) S + N
is handed over to the major classification processing circuit 12A, and if there is a character with the same feature amount as the feature amount that the peripheral feature detection circuit 21A was able to find for the A side or the D side, the candidate assigned to the character Logic "1" candidate display data CAD is written in the character code memory area.

In this way, if there is a memory area of candidate character codes in which the candidate display data CAD on sides A to D are all logic "1", it can be determined that the character with the candidate character code is similar to the input character. is being done.

The major classification dictionary 12B is the major classification dictionary data DCLA! used when determining in which memory area of the candidate memory 23A the candidate display data CAD should be written based on the input character information S4.4. 3 (shown for the A side in FIG. 17) are stored in the A side to D side storage areas MIA to MID corresponding to the A side to D side.

Major classification dictionary data DCL□ is header data (DHD
AT) A and character code part data (DICDA T)
A, header part data (DHDAT) A contains all recognition target characters (candidate character code "0" to r409
5J is assigned) has the feature quantity numerical data V A LDCHN (Equations (11) and (13)) "8"...r128 For each J, the feature quantity numerical data VALocu* is Character code section data (DICDAT ) A set of dictionary address data D3 representing the start address of a is stored for each feature code DI, and when the special ml numerical data VALD is detected in the peripheral feature detection circuit 21A,
The feature value numerical data VALnco* allows direct access to the address where the feature code D1 is stored, and also allows readout of the candidate number data D2 and dictionary address data D3 that are combined with the feature code D1.

Character code part data (DICDAT) A is obtained by dividing 4096 characters with candidate character codes "0" to r4095J into groups of characters that share the feature code D1 among the A-side peripheral features. , stored in a memory area with a series of addresses "0" to r 4095 J.

In this way, the candidate character code DO stored in the character code section data (DICDAT) A is feature quantity numerical data representing the feature quantity DCH11 possessed by the A-side peripheral feature among the characters to which the candidate character code is assigned. VALDCHR as peripheral feature detection circuit 21
It can be read by inputting from A to the candidate character search circuit 21B.

For example, the candidate character search circuit 2 uses the feature value numerical data VALDCHII representing the first feature code Di (=r8J).
1B, the candidate character search circuit 21B searches the candidate number data D2 (= r143 J) from the start address "0" specified by the dictionary address data D3 (= rOJ) as the character code section data (DICDAT) a.
) candidate character codes DO are stored, that is, the memory area up to the end address r142J can be accessed.

The processing procedure for writing the candidate display data CAD corresponding to the characteristics represented by the characters of the input character information S0 into the candidate memory 23A in this way is as shown in FIG. Feature value numerical data (VALIICHR) obtained for edges A~(V
Major classification dictionary data D CL by ALIICHR)D
Header part data (D HD AT ) of ASM
By accessing a~(DHDAT)o, feature value numerical data (VALocm) A~(VALI, cm)
The feature code D1, candidate number data D2, and dictionary address data D3 corresponding to , can be defined as I.

Thus, using the characteristic code DI of this header part data (DHDAT) A, the character code part data (DI CD A
T) By accessing a to (DICDAT)n, all candidate character codes DO assigned to characters having the same characteristics as those of the input character information SIN are retrieved from the major classification dictionary data D CLAS3 to side A or side D. It can be read out separately.

The candidate character code DO read in this way is used as address information for the candidate memory 23A, and is used as address information for the candidate memory 23A.
3A, candidate display data CAD of logic "1" can be written in the memory area having the accessed candidate character code DO for each side A to D.

Such a function can be realized by the candidate character search circuit 21B having the configuration shown in FIG.

In FIG. 15, the major classification dictionary 12B has a candidate character code classification storage area M1, a work area M2, a candidate character reading rear address storage area M3, and a special character code storage area M4.

The candidate character code classification storage area M1 is a storage area section MIA, MI that stores the major classification dictionary data I)ct□ described above with reference to FIG. 17 for the A side, B side, 0 side, and D side.
B, MICSMID, and by specifying the side representing the peripheral feature and the feature code D1, the corresponding candidate character code DO can be sent to the candidate memory 23A as data DATA2.

That is, as shown in FIG. 17, for example, when the A-side feature detection data DATA1 representing the feature code "8" arrives from the peripheral feature detection circuit 21A, it is transferred to the address data ADDR via the address buffer circuit 23B.
1, the characteristic code D of the header part data (DHDAT) A stored in the storage area section MIA on side A of the candidate character code classification storage area M1.
1, the first set of feature codes DI (=r8J
) is accessed.

At this time, the major classification dictionary 12B stores the first set of candidate number data D2 (=r143 J) and dictionary address data D3 (=rOJ) as output data DATA via the address buffer circuit 23C into an operation count register. 23D and start address register 23E
write to.

At this time, the candidate number data D2 (-r143 J) is set in the operation count register 23D, so the control circuit 23
By sending out the control signal 31 based on the output of the timing generation circuit 23G, the candidate character search circuit 21B
start the search operation as a whole.

At this time, the storage contents of the head address register 23E, that is, the dictionary address data D3 (=rOJ) are the memory area at the 0th address of the character code part data (DiCDAT) a of the A side storage area MIA of the candidate character code classification storage area M1. access.

Here, the memory area at address 0 contains the candidate character code DO.
(=r67J) (FIG. 17) is stored, this is sent to the candidate memory 23A as access data DATA2, and thus the state becomes such that address "67" of the candidate memory 23A (FIG. 16) is accessed.

However, since a search operation is currently being performed regarding the peripheral characteristics of side A, the control circuit 23F sends out a signal specifying side A as the side selection signal HEN included in the control signal S1, and this is sent to the gate circuit 23H and the path. Buffer circuit 23! By specifying the A-side memory area of candidate memory 23A through
Logic rlJ is stored in the memory area on side A of address “67” of 3A.
The candidate display data CAD will be written.

When this operation is completed, the operation count register 2
3D performs decrement operation and the count content is r143
J, the start address register 23E increments and switches to a state in which the memory area at the first address of the character code section data (DICD AT) A is accessed as the address data ADDR1.

At this time, character code part data (DICDAT)
The candidate character code DO (= r241 J) stored in the memory area at the first address of A is the access data D.
It is sent to the candidate memory 23A as ATA2, and by accessing the memory area at the 241st address and side A of the candidate memory 23A, the logic "
1" candidate display data CAD is written.

When the write operation is completed, the operation count register 23D decrements and the start address register 23E increments at the same time as in the case described above, so that the next character code part data (
The control state is changed to access the memory area at address 3 of DICDAT)A.

Thereafter, in the same manner, among the character code part data (DICDAT) A stored in the A-side storage area MIA of the candidate character code classification storage area Ml, the 143 candidate character codes Do included in the first Mi are sequentially read. The data is output and used as access data DATA2 for the candidate memory 23A.

Eventually, when all the access operations for the 143 candidate character codes DO included in the first set of character code part data (DICDAT) a are completed, the count content of the operation count register 23D becomes 0, and the corresponding process is terminated. This means that the operation has ended, and at this time, the control circuit 23F puts the candidate character search circuit 21B as a whole into a state of waiting for the arrival of the next data DATA1.

In addition to this, the major classification processing circuit 12A subsequently processes the B side, 0
Every time the feature value numerical data VALnHc* representing the peripheral characteristics for the side and the D side arrives as data DATAI, the major classification dictionary 12B takes it in as the address data ADDR1 via the address buffer circuit 23B, so that the B side, 0 side, D side storage area part MI
B. MIC.

Major classification dictionary data D CLA! stored in MID
3, the candidate character code DO in the candidate memory 23A is input to the header part data (DHDAT).
(DHDAT). The character code part data (D I
CD A T)s, CD I CDAT) (DIC
By reading DAT)o and giving it as address data to the candidate memory 23A, the operation of writing candidate display data CAD of logic "1" to the corresponding memory areas of the B side, 0 side, and D side is repeated. .

When this operation is completed, all candidate characters with peripheral characteristics for the four sides of one character have been searched for each side, and candidate display data for all sides A to D has been searched. This means that the written character with candidate character code Do is determined to be a candidate character on all four sides, and therefore candidate display data CAD of logic "1" is displayed for all memory areas on sides A to D. The candidate character search circuit 21B performs operations such as reading from the candidate memory 23A and writing into the work area M2 of the major classification dictionary 12B.

That is, in the reading mode, the major classification dictionary 12
Among the read addresses stored in the candidate character read address storage area M3 of B, the last address of the candidate memory 23A (in this case, address 4095) + 1 (=409
6) is set in the operation count register 23D, and the start address of the candidate character reading address storage area M3 is set in the start address register 23E.

At this time, the control circuit 23F starts the reading operation of the candidate character search circuit 21B as a whole, and reads the address data ADDR sent from the first address register 23E.
1, the address data at the start address of the candidate character reading address storage area M3 (in this case, the cylinder O address) is sent out as access data DATA2 to the candidate memory 23A.

At this time, the candidate memory 23A reads out the candidate display data CAD written in the memory area at the 0th address on the A side as read data DATA4, temporarily stores it in the flip-flop circuit 23J, and all the output data are "
1” to the detection circuit 23K.
It is detected whether all the data on the side is logical "1".

The output data of the flip-flop circuit 23J is held by being fed back to the input terminal of the flip-flop circuit 23J via the gate circuit 23H and the pass buffer circuit 231.

Here, when the all "1" detection circuit 23K obtains the logic rlJ detection signal S3 indicating that the 4-bit candidate display data on sides A to D are all 1, the control circuit 23F detects the access data DATA2. The latch circuit 23L latches the latch output DATA5.
is written to the start address of the work area M2, the operation count register 23D is decremented, and the candidate count register 23M is incremented.

In contrast, the detection signal S to the all "1" detection circuit 23
When the control circuit 23F enters a state indicating that 3 is not all "1" (ie, logic "0"), the control circuit 23F proceeds to the next step without reading the access data DATA2 into the work area M2.

When the reading operation of the first address of the candidate memory 23A is thus completed, the number of operation count register 23D is decremented and the first address register 23E is incremented, so that the read address is stored in the next address of the candidate character reading rearaddress storage area M3. The read address (i.e., the first address) is sent to the candidate memory 23A as access data DATA2, and the candidate display data CAD on sides A to D written in the first address of the candidate memory 23A are all "1". It is read out to the detection circuit 23K.

At this time, when detecting that the detection signal S3 is all "1", the control circuit 23F outputs the access data DA.
TA2 is written to the memory area at the next address of the work area M2 via the latch circuit 23L, the operation number register 23D is decremented, and the candidate number count register 23M is incremented.

Thereafter, the above-described operations are repeated in the same manner until the count content of the operation count register 23D becomes 0.
As a result, the candidate display data CAD written in all addresses of the candidate memory 23A is sequentially read out to the all "1" detection circuit 23K, and when all "1" is detected, the access data (therefore, the candidate character code DO) is used as the workpiece. It is read into area M2.

When the reading operation of candidate display data has been completed for all addresses in the candidate memory 23A in this way, the work area M2 is filled with addresses where candidate display data CAD has been written for all sides A to D (therefore, candidate characters At the same time that the code DO) is stored, data representing the number of candidate characters is held in the candidate number count register 23M.

In this way, the major classification process for one human character is completed, and the candidate character codes Do read into the work area M2 of the major classification dictionary 12B are sequentially read out to the output circuit 12A2 and are standardized as candidate character information S CAD. At the same time, the count contents of the candidate number count register 23M are delivered as candidate character number information SCAIIN to the determination processing circuit body 14A (FIG. 10) via the output circuit 12A3.

In this state, the major classification processing circuit 12A as a whole is in a state of waiting for the arrival of the next input character information SIN, and when new input character information S arrives, it undergoes the same major classification processing as in the above case. immediately and independently from other circuit parts.

According to the large classification processing circuit 12A having the above configuration, the candidate display data CAD representing the peripheral characteristics of the A side to the D side is written for each side using the candidate memory 23A, and all of the A side to the D side are written. The address assigned to the memory area where the candidate display data was obtained is the candidate character code Do.
By reading the data as follows, it is possible to realize a large classification processing circuit that can perform large classification processing at high speed while combining hardware configurations with high operating speeds.

(In order to do so, the main classification dictionary 12B is converted into the header part data (
D HD AT) a ~ (DHDAT) D and character code part data (DICDAT) A ~ (DICDAT)
o, and the feature value numerical data V A L o, 1 cm representing the peripheral feature is directly used as the specification data of the feature code D1 of the header part data (DHDAT) A to (DHDAT) o. , multiple candidate character codes Do can be created using a simple data structure.
can be easily read out.

Also, candidate number data D2 of candidate characters having a common feature code D1 and character code part data (DICDAT) A
~ (DICDAT) I, dictionary address data D3 representing the start address of I, is header part data (D HD AT)
By using A to (DHDAT)D to read the candidate character codes DO of the character code section data, it is possible to reliably send out a large number of candidate character codes DO one by one with a relatively simple configuration. .

[G5] Subclassification Identification Unit 13 (G5-1) Overall Configuration The subclassification identification unit 13 receives candidate character information SCAI) from the major classification processing circuit 12A to the standard pattern set circuit 13B, as shown in FIG. When the X of subdivision dictionary 13C
The X direction and Y specified by the candidate character information S CAl1 from the direction dictionary section 13C1 and the Y direction dictionary section 13C2.
The direction standard character patterns are sequentially read out in that order and set in the standard pattern setting circuit 13B.

The standard character pattern consists of dot information for 24 lines x 24 dots, and the dot information for two lines, that is, the even number line and the odd number line, are stored in the even number line and odd number line stroke extraction circuit parts 33A and 33B of the stroke extraction circuit part 33, respectively. It is taken into stroke detection circuits 33AO and 33BO provided in the.

Corresponding to this, the subclassification identification unit 13 converts the dot information of the even and odd lines of the input cover pattern data DFTIN, which has been normalized to 24 lines x 24 dots in the normalization processing circuit 13A, into even and odd line strokes. Stroke detection circuit 3 of extraction circuit parts 33A and 33B
Import into 3A1 and 33B1.

The even line stroke detection circuits 33AO and 33A1 extract the strokes included in the corresponding even lines of the standard character pattern and the input character pattern, respectively, and are provided in the even line pattern matching circuit section 41A of the pattern matching circuit section 41. Stroke center coordinate and stroke width detection circuit section 41AI O and 41A20
The stroke center coordinates and stroke width are detected in the stroke center coordinate and stroke width coincidence detection circuits 41AOR and 41AOI, and coincidence is detected between the standard character pattern and the input character pattern.

Odd line stroke detection circuits 33BO and 33B1 similarly extract strokes included in odd lines,
Stroke center coordinates and stroke width detection circuit section 41B
If the stroke center coordinates and stroke widths detected in 10 and 41B20 match, the match detection circuit unit 41BI
Detected in R and 41BII.

The match detection outputs of even-numbered lines and odd-numbered lines are used in the standard character pattern residual calculation circuit section 45R to erase patterns based on the standard character pattern, and in the input character pattern residual calculation circuit section 45I, they are used to erase patterns based on the human character pattern. This is used to erase the pattern that has been created.

In this way, the residual data Dt11 obtained from the standard character and input character pattern residual calculation circuit sections 45R and 451 is sent from the output circuits 13E2 and 13E3 to the judgment processing circuit main body 14.
handed over to A.

(G5-2) Standard pattern set circuit 13B As shown in FIG. 19, the standard pattern set circuit 13B has a CPU 31A having a microcomputer configuration, and controls the program memory 31C and address decoder 31D by a control buffer circuit IB. Data processing is executed by supplying address data to the program memory 31C and address decoder 31D through the address buffer circuit 31E.

That is, the CPU 31A is the control buffer circuit 31.
By controlling the output circuit 12A2 and the flag register 31F of the major classification processing circuit 12A through the bus 31G1 and the flag register 31F, the candidate character information SC^ which is latched from the major classification processing circuit main body 12AI to the output circuit 12A2 is transmitted through the bus 31G1 and the data buffer circuit 31J. At the same time, it is taken into the address counter 31 through the control buffer circuit 31B.
By controlling H, the standard pattern data Dprsr is read from the X-direction and Y-direction standard pattern dictionary sections 13C1 and 13C2 stored in the subclassification dictionary 13C, and is written into the shift register 311 as dot information for even-numbered lines and odd-numbered lines. This is configured so that it can be sent as line data information QRDO consisting of parallel data of 23 bits per line by a shift control signal CIRO given from the subclassification processing circuit main body 13E1.

(G5-3) Input cover turns set circuit 13D As shown in FIG.
Compared to the standard pattern set circuit 13B shown in the figure, it has almost the same configuration as the standard pattern set circuit 13B except that there is no address counter 31H for reading the subclassification dictionary 13C.

Therefore, in FIG. 18, parts corresponding to those in FIG. 17 are shown with the same letters of the alphabet.

(G5-4) Stroke extraction circuit section 33 standard pattern set circuit 13B and input cover turns set circuit 13D shift registers 311 (Fig. 119) and 32 (20th
Line data QRDO and QIDO set in Figure)
is taken in one line at a time to the even line and odd line stroke extraction circuit sections 33A and 33B of the stroke extraction circuit section 33 of the subclassification processing circuit main body 13E1 shown in FIG.

Even number line and odd number line stroke extraction circuit section 33A
and 33B have the same circuit configuration, so the second
In FIG. 1, even number line stroke extraction circuit section 33
The detailed configuration of A is shown below.

The even line stroke extraction circuit 33A is shown in FIG.
) and (B), by taking in line data while cooperating with the shift register 311 of the standard pattern set circuit 13B and the shift register 321 of the input cover turns set circuit 13D based on the circuit clock CLOCK, The length of the black character stroke (i.e. the length of consecutive dots) included in each line.
Standard pattern coordinate data RA that extracts and represents its coordinates
DDO and input pattern coordinate data IADDo are formed.

Shift register 311 of standard pattern set circuit 13B
The load signal RLD is generated when the load signal RDOI (FIG. 22 (A) and (B)) generated in the address decoder 31D (FIG. 19) is generated.
Top 16 out of 24 dot data by OO
The bit dot data is loaded into the shift register 311, and then the lower 8
Load the bit load data into the shift register 311.

The load signals RLDOO and RLD01 are given as set signals to the enable flag circuit 34A (consisting of a flip-flop circuit) of the stroke extraction circuit section 33A, and the rear cylinder 2 from which the first load signal RLDOO is generated from the enable flag circuit 34A. load signal ■τ
The enable flag signal HDENR, which rises to the logic rHJ level, is sent out on the condition that D--T occurs.

The enable flag circuit 34A is reset by receiving as a reset signal the line data capture end signal LEND generated when the stroke extraction circuit section 33 finishes its stroke extraction operation.

This enable flag signal HDENR is supplied to the AND circuit 34.
B, and the shift control signal CIRO (FIG. 22(A)
) and (B)) to the logic rHJ level.

This logic rHJ level shift control signal CIRO is given to the shift register 311 of the standard pattern set circuit 13B as a shift permission signal, and at this time, the shift register 311 transfers dot data one dot at a time in each cycle according to the circuit clock CLOCK. line data QR
It is sent as a DO (Fig. 20 (A) and (B)).

This line data QRDO is given as a set signal to a cooperative operation circuit 34C having a flip-flop circuit configuration.

The cooperative operation circuit 34C is configured so that the line data QRDO is logical.
It is configured to perform a set operation when it transitions from the logic "1" level to the logic rOJ level, and at this time, the logic "1" is output to the output terminal.
The cooperative operation signal RDSR (FIGS. 22(A) and 22(B)) rising to the ``level'' is sent out.

The cooperative operation signal RDSR is inverted by the inverter 34D and supplied to the AND circuit 34B, and after the enable flag signal HDENR rises to the logic rlJ level, the line data QRDO changes from the logic "1" level dot to the logic "0" level. Since the cooperative operation signal RDSR is at the logic "0" level until the shift to the "level dot", the shift control signal CIRO is set to the logic "1" level.
level, and thus continues to send line data QRDO from the shift register 311.

On the other hand, when the dot data of the line data QRDO falls from the logic "1" level to the logic "0" level, the shift operation of the shift register 311 is controlled by lowering the shift control signal CIRO to the logic "0" level. It is made to stop.

Thus, after the load signal RLDO is generated at time t0, the shift register 3 is activated at time t1 when the enable flag signal HDENR rises to the logic "1" level.
11 performs a shift operation, and after the line data QRDO, which is sequentially captured, once transitions to logic "1" (
Logic “0” (represents the point at which the first character dot is scanned)
'' level (meaning the end point of the character section), the shift operation of the shift register 311 is stopped.

In this embodiment, the standard pattern set circuit 13B outputs data between the 2nd bit to the 4th bit, between the 7th bit, and between the 9th bit to the 11th bit, etc., as shown in the following formula. Data with black character strokes is input,
Therefore, when the shift register 311 starts the shift operation at time t in FIG. Line data QRDO rises from logic "0" to logic rlJ at the timing when moving from the fourth bit to the second bit, falls from logic rlJ to logic "0" when moving from the fourth bit to the fifth bit, and from the sixth bit to logic "0". When moving to the 7th bit, logic rOJ
It rises to logic “1” from 7th bit, and falls from logic “1” to logic rOJ when moving from the 7th bit to the 8th bit,
When moving from the 8th bit to the 9th bit, it rises from logic "0" to logic "1", and when moving from the 11th bit to the 12th bit, it falls from logic "1" to logic "0"...
By exhibiting changes in the logical level such as...
The timing at which the logic rises from logic "0" to logic "1" represents the start point of the stroke, and the timing at which the logic subsequently falls from logic "1" to logic "0" represents the end point of the stroke.

The start point and end point of this stroke are detected by the standard pattern start point and end point detection circuit section 33D.

The standard pattern start point end point detection circuit section 33D has a stroke detection circuit 37A having a flip-flop circuit configuration, and when the data rises from the logic rOJ to the logic rlJ upon receiving the line data QRDO, the circuit clock CLOCK is output.
The set operation is performed at the timing of , and then the line data QR
When DO falls from logic "1" to logic "0", a reset operation is performed at the timing of the circuit clock CLOCK.

(The output end of the stroke detection circuit 37A has a second
As shown in Figure 2 (A) and (B), the line data QR
Time t when DO rises from logic "0" to logic "1"
! A stroke detection signal REF that rises from logic "0" to "1" is sent out at the timing of . This stroke detection signal REF then falls from the logic rlJ to "0" at the timing t3 when the line data QRDO falls from the logic "1" to "0".

Thus, at time t2-1. The stroke of the first character portion can be represented by the stroke detection signal REF which rises to logic "1" during the period.

The stroke detection signal REF is applied together with line data QRDO to a start point detection circuit 37B and an end point detection circuit 37C, each of which is composed of a flip-flop circuit. Logic ' during the clock period
Generates a start point detection signal RRCLOO that rises to 1.
Further, at the time t when the stroke detection signal REF falls to logic "0", the end point detection signal RRG rises to logic "1" from the end point detection circuit 37C for one clock period.
Send LOI.

The shift control signal CIRO is given to the standard pattern address counter 34D, and the shift control signal CIRO is set to logic r.
1J, the standard pattern address counter 34D outputs the circuit clock CLOCK in synchronization with the shift register 311 sending out the line data QRDO one bit at a time.
By counting , standard pattern coordinate data RADDO representing the bit address of the sent standard pattern data (therefore, the position coordinates of 24 dots included in one line) is sent out.

Standard pattern coordinate data RADD1 is similarly sent out from the odd line stroke extraction circuit section 33B.

The input cover turn line stroke extraction circuit section 33Al is
It has a processing system similar to that of the line data QRDO for the standard pattern, and as shown by attaching the same alphabetic characters to corresponding parts, the load signal ILDO
The enable flag signal HDENI obtained from the enable flag circuit 35A receiving O and -ILI is sent as a shift control signal C110 to the input cover turn shift register 321 and the input cover turn address counter 35D via the AND circuit 35B. The cooperative operation signal ID5R obtained from the cooperative operation circuit 35C based on the line data QIDO of the shift register 321 is applied to the AND circuit 35B via the inverter 35E.

Thus, from the input cover turnset circuit 13D to FIG.
As shown in A) and (B), when line data QIDO having a bit arrangement as shown in the following formula % is sent from the shift register 321, as shown in FIG.
and the load signal RLDO0 or cooperative operation signal RDS used during standard pattern data processing in (B).
As shown by the load signals Tτm to ID5R shown in correspondence with R, the load signals TTTT and IL go5
15 set in shift register 321 by TT
Processing based on the 47 minute line data QI Do is executed.

The standard pattern side cooperative operation signal RDSR and the cover turn side cooperative operation signal ID5R are applied to an AND circuit 36A, and the AND output thereof is applied to a reset pulse generation circuit 36B.

When the AND output of the AND circuit 36A becomes the logic rlJ, the reset pulse generating circuit 36B generates a signal as shown in FIG. 22(A).
And as shown in (B), after the delay time DL has elapsed, a reset pulse QDSR that falls to the logic rLJ level by a predetermined time width DLR is generated, and this is sent to the standard pattern side and input cover turn side cooperative operation circuits 34C and 35C. By applying this as a reset signal to QDSR, the cooperative operation circuits 34C and 35C are reset at the timing when the reset signal QDSR rises to the logic "1" level.

Thus, when the cooperative operation circuits 34C and 35C perform a reset operation, the cooperative operation signals RDSR and ID5R fall to the logic rLJ level at the same time, and this fall causes the shift control signal CIRO to become the logic rHJ level via the inverter 34E and the AND circuit 34B. By raising the shift register 311 and the standard pattern address counter 34D to the logic "1" level, the shift register 311 and the standard pattern address counter 34D are operated for shifting and counting. The shift register 321 and the input cover turn address counter 35D are started to shift and count.

Thus, the standard pattern data processing system and the input cover pattern data processing system of the even line stroke extraction circuit section 33A simultaneously begin the stroke extraction operation for the next character section.

In addition to this configuration, the reset pulse signal QDSR is applied to the even line data capture end signal generation circuit 36C. Even line data capture end signal generation circuit 36C
22 (A) and (A) when the stroke detection operation for the even-numbered line is completed (that is, when the address becomes "24") together with the standard pattern coordinate data RADDO and the incoming pattern coordinate data IADDO.
As shown in B), an even-numbered line data acquisition end signal CHAEND rising to the logic "H" level is generated and sent to the line data acquisition end signal generation circuit section 33C.

The line data capture end signal generation circuit section 33C waits for the odd line data capture end signal CHBEND (FIG. 22 (A) and (B)) to be given from the odd line stroke extraction circuit section 33B, and then Line data capture end signal CHAEND and CH
When both BBNDs are obtained, Fig. 22 (A) and (B
), a line data acquisition end signal LEND that falls to the logic rLJ level during a predetermined period is generated.

This line data capture end signal LEND is transmitted to the standard pattern side cooperative operation circuit 34C and the enable flag circuit 3.
4A, input cover turn side cooperative operation circuit 35C and enable flag circuit 35A as a reset signal,
As a result, the even-numbered line stroke extraction circuit section 33A as a whole enters a standby state in which it takes in the line data of the next line.

Stroke center point comparison outputs IER and R are sent from the pattern matching circuit section 41 to the cooperative operation circuits 34C and 35C.
ER is provided to enable the pattern matching operation described above with respect to FIG.

The incoming cover turn start point and end point detection circuit section 33E has the same configuration as the standard pattern start and end point detection circuit section 33D, and generates a stroke detection signal IEF in the stroke detection circuit 38A based on the line data QIDO and outputs the start point detection signal IRG. Ding TT and end detection signal - “π”
produce] - with the mouth.

In this way, the end point detection signal RRGLOO1IRGLOO and the end point detection signal RRGL formed in the standard pattern and input cover turn start point end point detection circuit parts 33D and 33E
OI and IRGLOI are respectively given as pattern matching operation control signals to the pattern matching circuit section 41 shown in FIG.

(G5-5) Pattern Matching Circuit Section 41 As shown in FIG. Pattern coordinate data RADD
1 and an odd line pattern matching circuit section 41B that receives input cover pattern coordinate data IADDI (
Figure 18). Note that in FIG. 21, the odd line pattern matching circuit section 41B has exactly the same configuration as the even line pattern matching circuit section 41A, so illustration and description thereof will be omitted.

The standard pattern coordinate data RADDO is given to the starting point address register 42A and the ending point address register 42B, and the standard pattern starting point and ending point detection circuit section 33D (FIG. 21)
When receiving the start point detection signal RRGLOO and the end point detection signal RRCLOI obtained from the start point address register 42A and the end point address register 42B,
write to.

In addition, in FIGS. 22 (A) and (B), the starting point detection signal ■ 100τshikata rising time and the end point detection signal RRGLO
Although the timing is shown such that the rising point of 1 is the last point in the clock period of the address data when the logic level of the line data QRDO switches, in reality, the standard pattern address counter 3
Since the switching of address data in 4B is delayed,
The start point address register 42A and the end point address register 42B can latch the determined address data in the start point address register 42A and the end point address register 42B when a change occurs in the line data.

The start point address and end point address latched in the start point address register 42A and the end point address register 42B are given to a stroke center coordinate detection circuit 42C and a stroke width detection circuit 42D.

The stroke center coordinate detection circuit 42C and the stroke width detection circuit 42D are each configured with a conversion ROM, and the conversion outputs and I)+z are sent to the stroke center coordinate comparison circuit 43A and the stroke width comparison circuit 43B, respectively.
is given as a comparison input.

On the other hand, the input cover turn coordinate data IADDO is similarly generated by the start point address register 44A and the end point address register 44B by the input cover turn start point and end point detection circuit section 33E.
Starting point detection signal IRC; LOO and IRGL obtained from
latched by OI, and its latch output is the conversion RO
In the M-configured stroke center coordinate detection circuit 44C and stroke width detection circuit 44D, the stroke center coordinate data [)it and the stroke width data I)tt are the stroke center coordinate comparison circuit 43A and the stroke width comparison circuit 4.
3B as the second comparison input.

The stroke center coordinate comparison circuit 43A compares the stroke center coordinate data DI1 on the standard pattern side and the stroke center coordinate data D2 on the input cover turn side. When the matches,
A coincidence detection signal EQLC at the logic rlJ level is generated and sent to the AND circuit 43C.

In this embodiment, the stroke center coordinate comparison circuit 43A determines whether the difference in input data falls within a predetermined threshold level, and sends out a coincidence detection signal EQLC when a positive result is obtained.

The stroke width comparison circuit 43B receives the standard pattern side stroke width data Dl! And input cover turn side stroke width data D! ! When there is a match, a match detection signal EQLW that rises to the logic rlJ level is generated, and this is sent to the AND circuit 43.
Give to C.

In this embodiment, the stroke width comparison circuit 43B determines whether the difference in input data falls within a predetermined threshold range, and when a positive result is obtained, obtains a coincidence detection signal EQLW.

When the AND output of the AND circuit 43C becomes the logic "1" level, it is applied as the erase control signal 5ERA to the standard character pattern stroke erasing circuit 43D and the input character pattern stroke erasing circuit 43.

The standard character pattern stroke erase circuit 43D receives as input data the start point address data latched in the start point address register 42A and the end point address data latched in the end point address register 42B, and is given an erase control signal 5ERA of logic "1" level. When the timing is between the start point address and the end point address, the logic becomes “0”.
In response to this, the erase control signal 5ER is sent out.
When A is at the logic "0" level, logic rlJ data is output at the timing of the start point address and end point address.

Thus, when the input character pattern has a stroke having a position and width that match the input character pattern with reference to the stroke of the standard character, the stroke of the standard character pattern can be erased by the stroke of the input character pattern.

On the other hand, if the input character pattern does not include strokes that do not match in either position or width, the standard character pattern stroke deletion circuit 43D converts the stroke data corresponding to the input data into standard character deletion pattern data. The standard character erasing pattern data REFA is sent from the circuit 43F.

The input character pattern stroke deletion circuit 43E is similar to the standard character pattern stroke deletion circuit 43D, except that the strokes to be deleted are the start point address data and end point address data latched in the start point address register 44A and the end point address register 44B. The input character erasing pattern data INA can thus be obtained from the input character erasing pattern data forming circuit 43G.

In this embodiment, the standard character erasing pattern data forming circuit 43F has a register circuit 43F1 that dynamically stores the addition output by feeding it back to the input terminal, and when receiving erasing data from the standard character pattern stroke erasing circuit 43D, After rewriting the data of the corresponding coordinates, the result is sent out as standard character erasing pattern data REFA and is also dynamically stored.

In this way, when a plurality of strokes occur in one line of data in the start point address register 42A and the end point address register 42B, unerased stroke data is generated at the coordinate position of the stroke.

The input character erasing pattern data forming circuit 43G also has a similar register circuit 43G1.

In addition to the above configuration, the pattern matching circuit section 41 is provided with a comparison circuit 43H that receives the sending outputs of the stroke center coordinate detection circuits 42C and 44C, and [)it as the comparison human power A and B. When the strokes do not match, the comparison output IER of the logic "1" level is obtained, the comparison output RER of the logic rlJ level is obtained when A<H, and the comparison outputs IER and RER are given to the cooperative operation circuits 35C and 34C. By temporarily stopping the shift of the dot data with larger coordinates, the seventh
As described above with respect to the figures, all strokes included in the input character pattern can be matched with all strokes included in the standard character pattern.

Here, if the center coordinates of the strokes of the standard pattern and the input pattern match, the stroke center coordinate comparison circuit 43A
When the comparison output EQLC of becomes logic “1”, tIA
Outputs RDSR and ID of adjustment circuits 34C and 35C
If both SRs become logic "1", it means that matching has been achieved. At this time, by outputting the reset signal QDSR, the operations of address counters 34D and 35D and shift registers 311 and 321 are restarted.

Also, the start and end points of the standard pattern and the input pattern part are detected, and the outputs RDSR and IDSR of the cooperative operation circuits 34C and 35C are set as RDSR=rlJ and I
When D5R=rlJ, if the output EQLC of the stroke center coordinate comparison circuit 43A is logic "0", it means that matching has not been achieved.

In this state, when the center position of the stroke of the standard pattern is larger than the center position of the stroke of the input pattern, that is, when RADDc > IADD, the comparison output IER becomes logic "1", so that the stroke extraction circuit section 33 (the Figure 21) FIA on the input cover turn side
The adjustment circuit 35C is reset and the shift register 321
and starts the operation of address counter 35D.

On the other hand, the cooperative operation circuit 34C on the standard pattern side maintains an unreset state.

When the center position of the stroke is reversed, the cooperative operation circuit 34
The operation of C and 35C is reversed.

In this way, all the strokes that are practically necessary for the input pattern can be matched with all the strokes of the standard pattern.

In the case of this embodiment, gate circuits 431 and 43J are provided at the input terminals of the enable input signal QDSR of the standard character and input character deletion pattern data forming circuits 43F and 43G, and the gate circuits 431 and 43J are provided as the opening/closing control signal of the comparison circuit 43H. Comparison outputs RER and ER are provided, and when there is a mismatch, the gate is opened and the residual error is written.

(G5-6) Residual calculation circuit section 45 As shown in FIG. 24, the residual calculation circuit section 45 converts the standard character erasure pattern data REFA sent from the pattern matching circuit section 41 into a standard character erasure pattern matrix conversion circuit 46A.

This standard character erasing pattern matrix conversion circuit 46A scans the standard character erasing pattern data obtained in the pattern matching circuit section 41 in the X direction for all odd lines and even lines with respect to the standard character pattern obtained based on the X direction scanning. After writing the standard character erasing pattern for one character by writing in order,
By reading out the standard character erasure pattern for one character in the order of the Y scanning direction, the X direction erasure pattern is
Standard character rotation deletion pattern data R similar to rotated
FQ is output and latched one bit at a time in a latch circuit 46B having a flip-flop circuit configuration.

By the way, as described above with reference to FIG. 19, the standard pattern set circuit 13B is connected to the
After reading out the X-direction standard pattern data from the Y-direction standard pattern dictionary section 13C2, the Y-direction standard pattern data is read out from the Y-direction standard pattern dictionary section 13C2. The pattern data REFA arrives in the order of the X-direction standard character erasing pattern data and the Y-direction standard character erasing pattern data.

Therefore, at the timing when the first data of the Y-direction standard character erasing pattern data arrives as the standard character erasing pattern data REFA, the X-direction standard character erasing pattern data has been written in the standard character erasing pattern matrix conversion circuit 46A without excess or deficiency. , it is the timing to read the first data.

Using this relationship, standard character erasing pattern data RE
The FA is latched one bit at a time in a latch circuit 46C having a flip-flop circuit configuration.

The latch output data of the latch circuits 46B and 46C is applied to an AND circuit 46D, which latches the AND output into the latch circuit 46 having a flip-flop circuit configuration.

In this way, the X-direction standard character erasing pattern data at the same coordinate position as the coordinate position of each bit of the Y-direction standard character erasing pattern data that is sequentially arriving as the standard character erasing pattern data REFA is read from the standard character erasing pattern matrix conversion circuit 46A. By outputting the data and performing an AND operation in the AND circuit 46D, the X-direction standard character erasing pattern and the Y-direction standard character erasing pattern are finally determined.
When there are strokes remaining at the same coordinates that are not erased,
The logic rlJ data for this bit is sent to the latch circuit 4.
It will be latched to 6E.

The erasure pattern data for one line of 24 bits latched by the latch circuit 46E in this way is given to the residual data calculation circuit 46F having a conversion ROM configuration, and is applied to the remaining strokes of the erasure pattern for one line. The data is converted into included dot number data and input to the standard character total residual data forming circuit 46G.

This standard character total residual data forming circuit 46G is composed of an addition circuit that dynamically stores the addition result by feeding back the addition output to the addition input terminal.
Thus, when residual data for 24 lines (that is, one character) is sent out from the residual data calculation circuit 46F, the total residual bit number is calculated and sent as standard character total residual data ZNRD.

The above configuration is a processing circuit for the standard character erasing pattern data REFA, but the input character erasing pattern data I
Similarly, an input character erasing pattern matrix conversion circuit 47A is prepared for NA, and the input character rotation erasing pattern data INQ is latched into the latch circuit 47B, and input character erasing pattern data INA representing the Y direction input character erasing pattern is is latched into the latch circuit 47C,
The logical product data is obtained in a logical product circuit 47D and is supplied to an input character total residual data forming circuit 47G via a latch circuit 47E and a residual data calculation circuit 47F.

In this way, the input character total residual data ZNID can be obtained from the input character total residual data forming circuit 47G.

(G5-7) Effect In the above configuration, the subclassification identification unit 13 forms line data by executing software calculation processing using the CPU in the standard pattern set circuit 13B and the input cover turns set circuit 13D. are a stroke extraction operation in the stroke extraction circuit section 33, a pattern matching process in the pattern matching circuit section 41,
Since the residual calculation in the residual calculation circuit section 45 can be processed by hardware by providing a unique data processing circuit, the data processing time required for subclassification processing can be reduced overall by software. Compared to the case where the calculation process is performed manually, the time can be significantly shortened.

Accordingly, in the stroke extraction circuit section 33,
The 1947 minutes of pattern data set in the shift registers 31 and 321 of the standard pattern set circuit 13B and the input cover turns set circuit 13D are made to coordinate the input operations of the standard pattern and input cover turn character parts, so that the stroke The data processing operation in the subsequent data processing circuit that processes the extracted result data can be executed on a stroke-by-stroke basis, making it easier and faster.

In addition, in the pattern matching circuit section 41, when a match is obtained in the standard character pattern stroke deletion circuit 43D and the input character pattern stroke deletion circuit 43 based on the width of the stroke and the position coordinates of the center, the data of the stroke is transferred to the subsequent stage. By not sending out the strokes, it is possible to easily realize a circuit configuration that can erase matching strokes from the standard character pattern and the input character pattern within a short processing time using a simple configuration.

Furthermore, by using the standard character erasure pattern matrix conversion circuit 46A and the input character erasure pattern matrix conversion circuit 47 as the residual calculation circuit section 45, residual data is generated from the erasure pattern scanned in the X direction and the erasure pattern erased in the Y direction. When obtaining the result, it is possible to easily realize a residual arithmetic circuit that can perform an AND operation with a relatively simple configuration and can significantly shorten the processing time.

[G6] Other embodiments (1) In the above embodiment, when performing matching processing between input character patterns and standard character patterns in subclassification processing, pattern data for two lines, that is, even-numbered lines and odd-numbered lines, is used. Although we have described the case where the matching process is performed using pattern data as a unit, the unit amount of pattern data during the matching process is not limited to this, and can be selected to various values, for example, 3 lines or more, 24 lines or more. You can select up to the line as needed.

Increasing the number of processing units in this manner inevitably increases the burden on the hardware configuration for processing them, but it is possible to further reduce the processing time for pattern matching.

(2) In the above embodiment, the case where one normalized character has the number of dots of 24 lines x 24 dots was described, but the size of the character is not limited to this, and the present invention can be applied widely to various cases. It can be passed.

(3) In the above embodiment, a case has been described in which peripheral features are used as features to be used when broadly classifying input character information, but other features such as parameter features may also be used. Even in this case, the same effect as in the above case can be obtained.

(4) Also, in the above embodiment, the major classification word 512B
Header part data (DHDAT) A~(DHDAT
) Although the starting address of the memory area that stores the candidate character code DO of the same feature amount is used as the dictionary address data D3 of o, a predetermined address other than the starting address may be used.

Effects of the Invention H As described above, according to the first invention, the special @ and amount of input character information are directly used as access data for reading candidate character codes from the major classification dictionary. The speed at which candidate character codes are read out can be further increased.

Further, according to the second invention, the header part data includes a feature code representing a feature amount, dictionary address data representing the start address of character code part data including candidate character code data, and a candidate character candidate having the same feature amount. By including the numerical data, the read speed can be further increased.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the character recognition section, Fig. 2 is a block diagram showing the overall structure of the character recognition device, Fig. 3 is a plan view showing an example of input characters, and Fig. 4 is a block diagram showing the structure of the character recognition device. Figure 5 and Figure 6 are route maps used to explain the feature quantities of sides, Figures 5 and 6 are route maps used to explain scanning of input character patterns, standards, and quasi-character patterns, and Figure 7 is a route map showing the principle of pattern matching. , FIG. 8 is a route map showing the erasure processing procedure used in pattern matching, FIG. 9 is a route map explaining the causes of variation in character patterns, and FIG. 10 is a block diagram showing the specific configuration of the character identification section. , Fig. 11 is a route map for explaining pipeline processing, Fig. 12 is a route map showing parameters of special characters, Fig. 13 is a route map showing vertically written characters, and Fig. 14 is a configuration of a major classification processing circuit. 15 is a block diagram showing the configuration of a candidate character search circuit, FIG. 16 is a route map for explaining the procedure for selecting candidate character codes, and FIG. 17 shows the data structure of the major classification dictionary. 18 is a block diagram showing the configuration of the subclassification identification section, FIG. 19 is a block diagram showing the configuration of the standard pattern set circuit, and FIG. 20 is a block diagram showing the configuration of the input cover turns set circuit. Figure 21 is a block diagram showing the configuration of the detailed classification processing circuit, Figures 22 (A) and (B) are signal waveform diagrams for explaining the classification processing operation, and Figure 23 is a block diagram showing the configuration of the pattern matching circuit section. 24 are block diagrams showing the configuration of the residual calculation circuit section. l...Character recognition device, 2. ...Image scanner section, 3...Print document, 4...
・Character identification unit, 5...Display device, 11...
...Input/output processing section, 12...Major classification identification section, 1
2A...Major classification processing circuit, 12B...
Major classification dictionary, 13... Subdivision identification section, 13A.
... Normalization processing circuit, 13B ... Standard pattern set circuit, 13C ... Subdivision dictionary, 1
3D...Input cover turnset circuit, 13E...
. . . Detailed classification processing circuit, 14 . . . Determination processing section. Text palm approval bag l Danzen x Hon appetizer bottom custom 2 Nagi No. 13 Figure 3 Nagi No. 4 Figure Procedural amendment 1. Indication of the case 1986 Patent Application No. 107871 2, Name of the invention Character recognition device 3, Person making the amendment Relationship to the case Patent applicant address 6-7-35, Tokyo Parts Illustrated Product Name (21
8) Sony Corporation Representative Norio Ohga 4, Agent 150 (Telephone 03-470-659)
1) Residence No. 22-10, Jingumae 3-chome, Shibuya-ku, Tokyo "Detailed description of the invention" column and Drawing 6, Contents of amendment (1) Specification, page 11, line 7, "Side A" Insert "side A to side D, for example" before . (2) Same, page 11, line 8, [MOJIAJ on the left side, [
Correct the A side of the left side character part MOJIA as W A KU AJ. (3) Same, page 11, line 9, after “line”, “LA”
Insert. (4) Same, page 11, line 16, ``upper left corner'' is corrected to ``start corner.'' (5) Same, page 13, line 3 from formula (6), "black background" is changed to "
"Black," he corrected. (6) Same, page 14, one line from formula (7), after "when the condition is satisfied", insert "(means that the black text part is a dot)" do. (7) Same, page 14, two lines from formula (7), "dot",
Correct it to "bit". (8) Same, page 15, line 2, “When the conditions do not hold.”
After , insert ``(meaning that the black text part is a dash, that is, a segment)''. (9) From formula (10) on page 16 of the same page, insert ``(This indicates that the code for the black text portion has ended)'' next to ``Set data'' in one line. (10) Same, page 17, one line from formula (13), "classification" is corrected to "setting". (11) Same, page 23, lines 10, 12 and 14,
Correct "center value" to "center coordinates." (12) Insert the following sentence between lines 16 and 17 on page 23. ``In other words, as a consistency evaluation formula, 1(R3z R31)-(rsz IS+)l<W
t. ...... (13A) ...... (13B) are used. In this embodiment, the subclassification processing circuit 13B, when aligning the center coordinates of the strokes PTINI 1PT+Nt, PTIN3 and the strokes P Tst+, P Tstt, adjusts the center coordinate I according to the movement of the coordinates of the scanning point.
Either Sa or PSo, for example l5o (or PS
O) is selected as the reference coordinate and the other center coordinate PSo (
Or calculate the difference with l5(1) and execute the matching process,
If alignment is not achieved, the difference is the center coordinate threshold level C
When TH is exceeded, the reference coordinate is switched to the first center coordinate PS6 (or l5o) that exceeds the center coordinate threshold level CTH, and the next center coordinate IS, (or PSO
), thus making it possible to process pattern matching efficiently in practice. That is, in FIG. 7, the first stroke P of input character patterns PT and H whose phase is advanced in the scanning direction
When the center coordinate ISo of TIN+ is compared with the center coordinate PS0 of the first stroke PTst+ of the standard character pattern PTST and the difference exceeds the center coordinate threshold level CTH, the subclassification processing circuit 13E It is determined that matching has not been achieved, and the stroke used as a reference during the next matching process is switched to the first stroke PT, a of the standard character pattern PTsr, and this is changed to the second stroke PT of the input character pattern PT1.
Perform matching processing with INg. However, if matching cannot be achieved here, the subclassification processing circuit 13E switches the stroke to be used as a reference in the next matching process to the second stroke PT1o of the input character pattern PTIN, and uses this as the standard character pattern PTsy.
Matching processing is performed with the second strokes PT and T□. Furthermore, if there is no consistency between the two, the subclassification processing circuit 13E
The stroke used as a reference during the next matching process is the standard character pattern PT, and the second stroke P T s of A is the standard character pattern PT.
A2 is switched to match the third stroke PTINff of the input character pattern PTIN. In this way, the subclassification processing circuit 13E calculates the strokes PTIMI, PT+Nt of the input character pattern PTrN.
When matching ...... with the strokes PTst+, PTsTz... of the standard character pattern PTst, the center coordinates of the stroke of the reference input character pattern PTIN (or standard character pattern PTsy) are delayed. Compare the center coordinates of the stroke of the standard character pattern PTsA (or input character pattern PTIN) with a phase of is not included in the standard character pattern PTsy (or input character pattern PTIN), and the standard character pattern PTs is
Switch the reference stroke to the next phase stroke of the other character pattern, that is, the standard character pattern PTst (or input character pattern PTIN), without performing matching processing with other strokes of t (or input character pattern PTIN). By doing so, the pattern matching processing efficiency can be further improved. ” (1
3) Same, page 24, line 4, "is input" is corrected to "is selected." (14) Same, page 29, line 7, "Figure 2" is replaced with "Figure 1"
I am corrected. (15) Same, page 31, line 8, “Candidate character information SeA
! Next to lJ, “and candidate character information data S cAt+
Insert xJ. (16) Same, page 38, line 18, “Figure 12 (A)”
is corrected to "Figure 12 (B)". (17) Same, page 49, line 2, "Figure 12" is corrected to "Figure 14." (1st) Same, page 50, line 11, "(Figure 1O)" is corrected to "(Figure 15)". (19) Same, page 52, line 1, next to rMIDJ, “
(Fig. 15)" is inserted. (20) Same, page 54, line 20, “Header data (
After DHDAT)AJ, insert "~(DHDAT)!, J." (21) Same, page 60, line 9, r V A L oH
cmJ to ``(VALooc member) l・(VALo to e
R) c5(VAL DHCll). ” he corrected. (22) Same, page 71, line 12, "1 line 23 bits" is corrected to "1 line 24 bits." (23) Same, page 76, lines 15 and 17, "character section" is corrected to "stroke". (24) Same, page 82, line 14, rDLJ, rDL
Correct it as IJ. (25) Same, page 88, line 20, “Data D! □”
is corrected to "converted to data D2t." (26) Same, page 90, line 15, insert "pause" after "address". (27) Same, page 94, lines 9 and 10, "reset" is changed to "set to a state that can be reset by the reset pulse signal QDSR, and thereby the input cover turn side"
I am corrected. (28) Same, p. 94, lines 16 to 18, "It is possible to make the entrance cover turn..." is corrected as follows. "By controlling the cooperative operation circuits 34C and 35C of the stroke extraction circuit section 33 (FIG. 21) by the comparison outputs RER and IER obtained from the comparison circuit 43H of the pattern matching circuit section 41 (FIG. 23), the standard When the strokes of the character pattern and the strokes of the input character pattern cannot be matched, the strokes to be matched are switched using the method described above with reference to Fig. 7. That is, the operations shown in Figs. 22 (A) and (B) In the case of the example, the standard character pattern side has the coordinates of the second to fourth dots, the coordinates of the seventh dot, and the coordinates of the ninth to 11th dots have the fourth, second,
While there is a third stroke, there are first and second strokes at the coordinates of the fourth to fifth dots and the eleventh dot on the input character pattern side. Therefore, between time points t and t4 in FIGS. 22(A) and (B), the stroke extraction circuit unit 33 (FIG. 21) outputs a start point detection signal RRGLOO and an end point detection signal RRGLOT for the first stroke of the standard character pattern. The obtained coordinate values ("2" and "5") can be latched into the start point address register 42A and end point address register 42B of the pattern matching circuit section 41 (FIG. 23), and the coordinate values ("2" and "5") can be latched into the start point address register 42A and end point address register 42B of the pattern matching circuit section 41 (FIG. 23). The start point detection signal IRGLOO and the end point detection signal IRGLOI can be obtained and their coordinate values ("4" and "6") can be latched into the start point address register 44A and the end point address register 44B. Thus, the standard character pattern and the first input character pattern
The matching process between the strokes is executed. By the way, the center coordinates of the first stroke of the standard character pattern is "3.5", whereas the center coordinates of the first stroke of the input character pattern is "5", so the stroke center coordinate comparison circuit 43A The threshold level is set to ``2'' to determine that the two match)
, center coordinate coincidence signal EQLC (second
Figure 2 (A)) is sent. In this state, the delay time D L + after time t4
Stroke erasure processing is executed during this period (FIG. 23), and eventually a reset pulse signal QDSR is generated at time tll. At this time, the comparison circuit 43H is not sending out the comparison outputs IER and RER (center coordinates -
Since the defeat signal EQLC is logic “1”), the cooperative operation circuit 3
4C and 35C are simultaneously reset by the reset pulse signal QDSR. Therefore, the shift registers 311 and 32r start shifting operations at the same timing at time t□. As a result, between time points t□1 to 111, the stroke extraction circuit unit 33 (FIG. 21) executes the extraction operation of the second stroke of the standard character pattern and the second stroke of the input character pattern, and the extraction results The pattern matching circuit section 41 executes pattern matching processing based on the above. However, the start point coordinates of the second stroke of the standard character pattern imported by this pattern matching process are "7" and the end point coordinates are "8", so the center coordinates are "7.5". Since the start point coordinates of the second stroke of the input character pattern are "11" and the end point coordinates are "12", the center coordinates are "rll,5". Therefore, at this time, the stroke center coordinate comparison circuit 43A sends out a center coordinate coincidence signal EQLC (FIG. 22(A)) of logic "0" (meaning a mismatch). In this state, when the reset pulse signal QDSR is generated at time LRTt after time LRTt, the comparison output RER of logic "1" is supplied from the comparison circuit 43H (FIG. 23) only to the cooperative operation circuit 34C. ,
Only the shift register 311 on the standard character pattern side starts a shift operation. Thus, between time points tRT□ and tz+, the start point and end point coordinate data of the third stroke of the standard character pattern are taken into the pattern matching circuit section 41, and this is combined with the start point and end point coordinate data of the second stroke of the input character pattern. By comparing, pattern matching processing is performed. Here, if the center coordinates of the second stroke of the standard character pattern are large, the shift register 321 on the input character pattern side will be shifted, contrary to the above case. In the case of the above embodiment, the results of the stroke extraction process and pattern matching process at time points tit□ to txt,
When the stroke center coordinate comparison circuit 43A detects coincidence, the reset pulse signal QD is generated at time t, 73.
At the timing when SR is obtained, the center coordinate coincidence signal EQLC is sent.
is in the state of logic "1" (Figure 22 (B))
, As a result, the shift registers 311 and 321 simultaneously perform a shift operation, thereby capturing all standard character patterns and input character patterns. However, in this embodiment, strokes cannot be extracted during this period. Eventually, when the standard pattern coordinate data RADDO and the input pattern coordinate data IADDO both reach "24" (this means that the processing of one line of dots has been completed), the even line data acquisition end signal CHAEND is sent.
(FIG. 22(B)) occurs, waits for the odd line data capture end signal CHBEND (FIG. 22(B)) to occur, and waits until time t! When the data acquisition end signal LEND is generated at N(l, the pattern matching process for dots on the even and odd lines is completed.) (29) Figures 1, 7, 12, and Figure 15, 18
22(A), 22(B), and 23 are corrected as shown in the attached sheet.

Claims (2)

[Claims] (1) In a character recognition device that extracts feature quantities from input character information and reads out candidate character codes having the above feature quantities from a major classification dictionary, the broad classification dictionary extracts feature codes representing the above feature quantities. 1. A character recognition device comprising header data that can be accessed as an address to read out candidate character codes of a plurality of candidate characters having the same feature amount as the feature amount. (2) The header data includes, in addition to the feature code representing the feature amount, dictionary address data representing the address of the character code portion data including candidate character code data, and candidate characters having the same feature amount as the feature amount described above. The character recognition device according to claim 1, characterized in that the character recognition device includes data on the number of candidates.