JPH01277946A - Word length variable storage device - Google Patents

Abstract

PURPOSE:To fix the constitution of hardware and to only change the number of stages of hardware to change the word length by accessing data, whose word length is integer-number of times as long as the word length of one unit, by memory areas where data having the word length of one unit are stored in a prescribed address order. CONSTITUTION:A word length set control circuit 24 is set in accordance with the word length of used data of a microprocessor to which this device is connected, and concretely, 8, 16, or 32 bits are set. This set signal is inputted to an operation memory selecting circuit 22, and upper two bits of an address bus 21 are used and a chip select signal to select one of memories M1-M4 is generated when the word length of access data is 8 bits. When it is 16 bits, one upper bit of the bus 21 is used and memories are divided into two pairs of memories M1 and M2 and memories M3 and M4, and one of these pairs is selected. When it is 32 bits, the whole of memories M1-M4 is used by the same technique.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a variable word length storage device in which the word length of accessed data is variable.

(Prior Art) In information processing and devices using microprocessors, storage devices using semiconductor memory and the like are generally indispensable.

FIG. 2 is a block diagram showing an example of such a conventional storage device.

In the figure, a microprocessor 11 includes a memory circuit 1.
2 is connected, and this memory circuit 12 is composed of an upper byte memory 13a and a lower byte memory 13b. This microprocessor 11 has a word length of −1
It processes 6-bit data, and the upper byte memory 13a and lower byte memory 13b provided in the memory circuit 12 are each semiconductor memories of 8 bits per word. Also, a microprocessor 11 and a memory circuit 12. These are connected by an upper byte data bus 14a, a lower byte data bus 14b, and an address bus and control bus 15.

The upper byte data bus 14a is connected to the upper byte memory 13.
connected to the input/output port of a, and the lower byte data bus 1
4b is connected to the input/output port of the lower byte data memory 13b. Further, the address bus and control bus 15 are connected in parallel to the address and control signal input terminals of both memories 13a and 13b.

When the microprocessor 11 accesses the memory circuit 12, it outputs, for example, a read control signal and an address signal in which the data is stored to the address bus and control bus 15. When these signals are input to the memory circuit 12, 8-bit data corresponding to the address is simultaneously read from the upper byte memory 13a and the lower byte memory 13b, and the 8-bit data corresponding to the address is read out from the upper byte data bus 14a and the lower byte data bus 1.
16-bit parallel data is read into the microprocessor 11 through 4b. The same applies to data writing.

As described above, the microprocessor 11 accesses data using, for example, two semiconductor memories.

(Problem to be solved by the invention) By the way, in devices that perform various complicated controls,
Such microprocessors are used in various parts of the device, and the word length of data used in calculations by each microprocessor is not necessarily constant. That is, various word lengths are used, such as 8 bits, 16 bits, 32 bits, etc.

Conventionally, for example, one 8-bit semiconductor memory was used to
In combination with a 16-bit microprocessor, using two similar semiconductor memories (as in the example explained in Figure 2),
I used four of them and combined them with a 32-bit microprocessor.

However, as shown in Figure 2, each memory circuit is wired for a specific word length, and the circuit configuration is different for each microprocessor, making component management complicated and lacking in versatility. There was a problem.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a variable word length storage device that has a common circuit configuration and has versatility.

(Means for Solving the Problems) A variable word length storage device of the present invention includes a plurality of memory areas for storing one unit of word length data in a predetermined address order, and is connected to an input/output port of each of the memory areas. a plurality of bus lines each having a width of the word length of the one unit; a word length setting control circuit that sets the word length of data accessed through the bus line to an integral multiple of the one unit; and the word length setting. Based on the control circuit settings,
The present invention is characterized by further comprising an operational memory selection circuit that selects one or more memory areas that enable the data access operation from among the memory areas.

(Function) The above device stores one unit of word-length data in a predetermined address order using a plurality of memory areas.
Data with a word length that is an integral multiple of the unit can be accessed.

For this purpose, bus lines each having a width of one unit of word length are connected to the input/output ports of each memory area. Then, the word length is set by the word length setting control circuit, and the memory to be operated in one access operation is selected by the active memory selection circuit. This results in
Data of a set word length can be read from or written to a predetermined bus line from a plurality of memory areas. Furthermore, the accessible word length can be easily changed by changing the settings of the word length setting control circuit.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram showing a first embodiment of a variable word length storage device of the present invention.

This device includes, for example, four memories M1 that store word-length data of 8 bits per unit in a predetermined address order.
~M4 is provided. And each memory M1 to M4
An address bus 21 is connected to the address bus 21 for accessing data stored therein. Further, the upper two bits of this address bus 21 are wired so as to be simultaneously input to an operational memory selection circuit 22. The operational memory selection circuit 22 is connected to a control bus 23 on which control signals for controlling the access operations of the respective memories M1 to M4 are manually input. The above memories M1 to M
All of 4 are composed of semiconductor memory elements and the like.

In addition to this, this circuit also includes a word length setting control circuit 24.
and a port selection control circuit 25 are provided.

The word length setting control circuit 24 is a circuit that sets the word length of data to be accessed in this device. The signal set here is connected to be input to the operational memory selection circuit 22 and the port selection control circuit 25. Note that this word length setting control circuit 24 is composed of, for example, a deep switch, etc., and is, for example, 8 bits, 16 bits,
Alternatively, it outputs a several-bit signal that sets a 32-bit word-length access operation.

The operating memory selection circuit 22 is connected to the upper two addresses of the address bus 22.
To selectively operate the memories Ml-M4 based on signals inputted from the bit and control bus 23,
This circuit outputs control signals 26a to 26d including chip select signals, write/read control signals, and the like. The operational memory selection circuit 22 is composed of a logic circuit or the like that is a combination of gates.

Further, the port selection control circuit 25 includes four switches SWI
~This is a circuit that controls the operation of SW4.

These switches SWI to SW4 are connected to the memories M1 to M4.
It is a switch circuit that selectively connects each input/output port to the data bus 29.

The data bus 29 is composed of four sets of bus lines each having a width of one unit, that is, eight bits. here,
Each bus line is named a first byte bus line 29a, a second byte bus line 29b, a third byte bus line 29c, and a fourth byte bus line 29d.

Incidentally, the port selection control circuit 25 includes each switch SWI.
This is a circuit that controls SW4 and outputs a selection signal to connect the input/output ports 27a to 27d connected to each switch to any one bus line. Therefore, the port selection control circuit 25 is also configured by combining gate circuits and the like.

The above device operates as follows.

First, depending on the word length of data used by the microprocessor to which this device is connected, the word length setting control circuit 24
Define the settings. Specifically, the dip switch is switched to indicate 8 bits, 16 bits, or 32 bits. When this signal is input to the operational memory selection circuit 22, the operational memory selection circuit 22 uses the upper two bits of the address bus 21 and selects each memory MI if the word length of the data to be accessed by the device is 8 bits.
A chip select signal is generated to select any one of NM4.

When the word length is 16 bits, the upper 1 bit of the address bus 21 is used to connect the memories M1 to M4 to the memories M1, M2, M3 . M4 is divided into two groups, and a chip select signal for selecting one of the groups is generated.

Furthermore, when the word length is 32 bits, a chip select signal is generated to select all memories M1 to M4, regardless of the contents of the address signal. These chip select signals are combined with the control signal inputted from the control bus 23 to form control signals 26a to 26d, and inputted to each of the memories M1 to M4.

On the other hand, when the word length is 8 bits, the port selection control circuit 25 selects the human output port 2 of all memories M1 to M4.
The switches SWI to SW4 are controlled so that the switches 7a to 27d are connected to the first byte bus line 29a.

Also, if the word length is 16 bits, the memories M1 and M
The input/output ports 27a and 27c of memory M2 and memory M4 are connected to the second byte bus line 29b, and the input/output ports 27b and 27d of memory M2 and memory M4 are connected to the first byte bus line 29
Each switch SWI to SW4 is controlled to connect to a.

When the word length is 32 bits, the input/output port 27a of the memory M1 is connected to the fourth byte bus line 29d, the input/output port 27b of the memory M2 is connected to the third byte bus line 29c, and the input/output port 27b of the memory M3 is connected to the third byte bus line 29c. Input/output port 2
7c to the second byte bus line 29b, and the memory M
4 input/output port 27d to the first byte bus line 29a.
Each of the switches SWI to SW4 is controlled to connect to the switch SWI to SW4.

As described above, in this device, when processing data with a word length of 8 bits, first, the memories Ml-M4
one of them is selected and the address bus 21 is connected to it.
An address signal is input through the first byte bus line 29a, and data at that address can be accessed via the first byte bus line 29a.

Furthermore, when processing data with a word length of 16 bits, any two of the memories M1 to M4 are selected. For example, if memories M1 and M2 are selected, an address is sent to them simultaneously via the address bus 21. A signal is input, and data at that address can be accessed via the first byte bus line 29a and the second byte bus line 29b.

Furthermore, when processing data with a word length of 32 bits, an address signal is input to all memories M1 to M4 through the address bus 21, and these memories are connected to the first byte bus line 29a to the fourth byte bus line, respectively. 2
Since they are connected to 9d in order, the total of 8 bits x 4 is 3.
2-bit parallel data can be accessed.

Such an operation can be easily switched by changing the set value of the word length setting control circuit 24, as described above.

FIG. 3 shows a block diagram showing a second embodiment of the apparatus of the present invention.

In this embodiment, a four-port memory in which separate memory elements as shown in FIG. 1 are combined into one is used. This memory is an expansion of the conventionally well-known dual port memory, and is a memory that receives four sets of address signals and control signals and allows data access from each of four input/output ports.

When using this 4-port memory, data can be freely and independently accessed through corresponding input/output ports using four sets of address signals and control signals. However, since the data storage area is common, if the same address is accessed, either one
It has the function of prioritizing only one access request. This function is a function employed in known dual port memories, and further detailed explanation will be omitted.

Now, in FIG. 3, this device is provided with a word length setting control circuit 24 similar to that shown in FIG.

This configuration is similar to that described in FIG. or,
In addition, a port selection control circuit 31 and an address generation circuit 3
2 is provided. An address bus 21 and a control bus 23 are connected to these circuits.

On the other hand, the 4-port memory 30 includes a port selection control circuit 3.
1 and the address signal 33a from the address generation circuit 32.
33d and control signals 34a to 34d are connected manually.

In addition, the input/output ports 35a to 35d of the 4-port memory 30
are connected in sequence to the two data buses from the first byte bus line 29a to the fourth byte bus line 29d, respectively.

The above circuit operates as follows.

First, the input/output ports 35a~ of the 4-port memory 30
35d is fixedly connected to each bus line of the data bus 29, and is connected to the 4-port memory 3 in order to selectively output word length data from 8 bits to 32 bits.
Address signal 33 for ports P1 to P4 of
a to 33d and control signals 34a to 34d are selectively controlled manually.

The port selection control circuit 31 and address generation circuit 32 are
This circuit has the operations of the operational memory selection circuit 22 and port selection control circuit 25 shown in FIG. 1, and is composed of a logic circuit combining gates and the like to perform the following operations.

That is, first, when performing an operation with an 8-bit word length, only the address signal 33a and the control signal 34a are valid and are input only to the port PI. Then, the first
The data can be accessed on the byte bus line 29a. In this case, input/output ports that are not operating are in a high impedance state.

Next, when performing a 16-bit word length operation, address signals 33a and 33b and control signals 34a and 34b become valid and are input in parallel to ports P1 and P2.

A first byte bus line 29a and a second byte bus line 2 are connected to the input/output ports 35a and 35b.
9b allows 16-bit data access.

Finally, when handling 32-bit data, all address signals 33a to 33d and all control signals 34a
~34d are enabled, and these are respectively port PI~
Input to port P4.

Then, 32
Bit data access becomes possible.

Note that when performing such an operation, the port selection control circuit 31 selects the address signals 33a to 33d and the control signal 34a as described above based on the bit length of the data set in the word length setting selection circuit 24. ~
Select the port that outputs 34d.

Further, in the case of processing of 8-bit data length, the address generation circuit 32 directly outputs the address signal to be accessed to the port P1. On the other hand, in the case of 16 bits or 32 bits, address signals to be output to each port are generated as follows.

In other words, in this memory, 8-bit word-length data of one unit is stored in address order, and when reading two or four units of separate data at the same time,
A separate address must be selected for each.

Since only one address signal is input from the host device etc. to access this memory, the address generation circuit is
Two or four types of address signals are generated based on the signals.

For example, specifically, in the case of a 16-bit word length access, the most significant bit of the address signal input to port P1 is inverted and input to port P2. In addition, in the case of access with a word length of 32 bits, codes O to 3 are generated in the upper two bits of the address signal input to the ports, and the codes are output to ports P1, P2, . Port P3. Separate address signals are input to port P4. By doing so, it is possible to simultaneously read data of word length of 2 units or 4 units from the 4-port memory 30 according to a fixed rule, and output it to a predetermined data bus for access.

An example of the word structure of the memory in the device of the present invention will be summarized using FIG. 4.

As shown in FIG. 4(a), if the minimum unit of 8 bits is one word, the 8-bit wide data up to D o ND t is stored in memories Ml-M4 (or port P
1 to P4) are read out in the order of their addresses.

On the other hand, as shown in FIG. 4(b), if 16 bits is one word, the 16-bit wide data from D0 to DIs is stored in the memory M1. M2 (or port P
2. Pi) simultaneously in the order of their addresses, and then the memory M3. They are simultaneously read from M4 (or port P2.Pi). In this case, the address area becomes 1/2 compared to the area shown in FIG.

Similarly, as shown in FIG. 4(c), if 32 bits are used as one word, data D. - 16-bit wide data up to D31 is stored in each memory M1 to M4 (or port P
4 to PI), and the address area is reduced by the length of the word.

As described above, by changing the settings in the word length setting control circuit of the variable word length storage device of the present invention, for example, three kinds of Can have configuration memory function.

The present invention is not limited to the above embodiments.

In the above embodiment, the memory area for storing one unit of word length data is formed by using four memory elements or by dividing one memory into four areas, but the number of areas is The selection, memory configuration, etc. are not limited to these, and various selections may be made. For example, in the embodiment shown in FIG. 3, a configuration may be adopted in which two dual port memories are used.

Further, in the embodiment shown in FIG. 1, a switch is used to selectively connect the input/output port of the memory to the data bus.
In the embodiment shown in FIG. 3, the input/output ports of the memory are fixedly connected to the data bus, and the input/output ports are selected by control signals. There is no problem in adopting the system shown in FIG. 3, or in the embodiment shown in FIG. 3, the system shown in FIG. However, according to the method shown in Figure 3,
There is also the advantage that switch circuits and the like can be omitted and the amount of hardware can be reduced.

Also, although the example was shown assuming that the word length of one unit was 8 bits,
If the word length of one unit is set to 4 bits, even more various combinations can be made, and the versatility can be further improved. Further, the word length setting control circuit has been shown as an example in which setting is performed using a dip switch, but it may also be constituted by a register or the like that stores a setting signal inputted from a host device or the like. In this case, there is an advantage that the word length can be changed freely under the control of the host device.

(Effects of the Invention) According to the variable word length storage device of the present invention described above,
By keeping the hardware configuration constant and making it possible to change the word length simply by changing the settings, there is no need to prepare separate memory circuits for each processor that uses data with different word lengths, making maintenance and management of memory circuits easier. Simplify and
The cost can be reduced. Furthermore, this device can be widely used as a replacement part for various existing memory circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the variable word length storage device of the present invention, FIG. 2 is a block diagram of a conventional storage device, and FIG. 3 is a block diagram showing a second embodiment of the device of the present invention. The block diagram shown in FIG. 4 is an explanatory diagram showing an example of the word structure of the memory of the device of the present invention. 21...Address bus, 22...Operation memory selection circuit, 23...Control bus, 24...Word length setting control circuit, 25...Port selection control circuit, 26a-26d...Control signal , 27a-27
d...I/O port, 29a-29d...Bus line, M1-M4. PL-P4...Memory area, SWI~S
W4...Switch. Patent Applicant: Oki Electric Industry Co., Ltd. (a) 8 bits (b) 16 bits as 1 word Memo No. D 31...D 24 of the device of the present invention D2s・・・・・・・・・
・Dos・・・・・・D7...D.・Rino word composition side explanatory diagram 4 diagram

Claims (1)

[Scope of Claims] A plurality of memory areas that store data with a word length of one unit in a predetermined address order, and a plurality of memory areas each having a width of the word length of one unit connected to an input/output port of each of the memory areas. a bus line, a word length setting control circuit that sets the word length of data accessed through the bus line to an integral multiple of the one unit, and based on the setting of the word length setting control circuit, 1. A variable word length storage device comprising: an operational memory selection circuit that selects one or more memory areas that enable data access operations.