JPH01277886A - Display color expanding device - Google Patents

Abstract

PURPOSE:To simplify the constitution of the display color expanding device by constituting a device which switches image data from plural image memories and outputs them after color expansion by using one lookup table circuit. CONSTITUTION:The image data D1 and D2 from the image memories 11 and 12 are multiplexed by a multiplexing means 21 into one output cycle and then the one lookup table circuit 22 performs the color expansion. Output image data determining means 25 and 26 determine image data to be outputted as image data in output cycles according to the transparent color information of the color-expanded and multiplexed image data LM, and image data selecting means 23 and 24 select the determined image data among the multiplexed image data and output them. Consequently, even when there are plural memories 11 and 12 provided as image memories, the color expansion processing is performed by using the one lookup table circuit 22, whose part can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display color expansion device that expands the display colors of images displayed on, for example, a cathode ray tube (CRT) display device.

[Prior Art] There are various devices such as a captain terminal device, a teletext receiver, and a personal computer as devices for displaying image data stored in an image memory on a CRT display device. The depth of the image memory used in such an image processing device is approximately several (3 to 5) bits.

By the way, when image data is read out from the image memory 1 as shown in FIG. The number of colors displayed is limited by the depth of the image memory 1. For example, if the depth is 3 pixels (three primary color signals R, G, B), the display colors are limited to eight colors: red, green, blue, yellow, magenta, cyan, white, and black.

Therefore, a display color expansion device that expands the colors that can be displayed using a look-up table circuit has already been proposed. As shown in FIG. 4, for example, 3-bit image data outputted from the image memory 1 is selected only during the display period via the selector circuit 4 based on the display period signal REFR8, and then sent to the buffer memory circuit 5. Give as address data. For example, 12-bit image data instructed in advance is given and stored in the buffer memory circuit 5 via the data bus DAS, and the image data corresponding to the address data is read out and given to the digital/analog conversion port 82. .

Therefore, by using the lookup table circuit 6 consisting of the selector circuit 4 and the buffer memory circuit 5,
3-bit image data is converted to 12-bit image data, and the number of colors that can be displayed on the CRT display device 3 is 21.
2 (4096) colors. However, in one display operation, 8 colors out of 4096 colors are displayed.

Note that during periods other than the display period, address data from the address bus ADB is applied to the buffer memory circuit 5 by the selector circuit 4, and at this time, a predetermined color is applied to the CRT display device 3.

By the way, some image processing apparatuses that expand display colors using look-up table circuits have only a plurality of image memories so as to be able to handle special displays such as superimposed display and superimposed display. The expanded configuration of display colors in this case has conventionally been as shown in FIG.

In FIG. 5, a clock signal CK is input to the address counter 10, and the count is incremented according to the clock signal CK to form rask-shaped read address data AD for the image memories 11 and 12. . The image memories 11 and 12 are, for example, frame memories, each of which stores, for example, 3-bit image data, and reads the image data D1 and D2 from the memory area designated by the incoming address data AD, and performs the corresponding lookup. It is applied to table circuits 13 and 14.

Each lookup table circuit 13, 14 receives the incoming image data D1, D2 as address data, takes out expanded image data L1, L2 of, for example, 12 bits from the memory area of the address, and selects the selector circuit 1.
5 as a selection input signal. Further, the image data L1 of one of the lookup table circuits 13 is provided to the transparent color determination circuit 16.

The transparent color determination circuit 16 determines whether the incoming image data L1 indicates a transparent color, for example, if all bits are logic "0".
), and when a negative result is obtained, the image data L1 from the lookup table circuit 13 is selected, and when a positive result is obtained, the image data L2 from the other lookup table circuit 14 is selected. A selection control signal SEL for selecting is given to the selector circuit 15. Selector circuit 1
5 selects one input image data according to the selection control signal SEL and supplies the image data C1 to a latch circuit 17 having a D-type flip circuit configuration.

The latch circuit 17 is also supplied with a clock signal CK, performs a latching operation in response to this clock signal CK, and supplies the latched image data OUT to a CRT display device via a digital/analog conversion circuit (not shown).

Therefore, when the address data AD shown in FIG. 6(B) is incremented by the clock signal CK shown in FIG. 6(A) so as to perform raster readout, the sixth Figures (C) and (
Image data D1 and D2 as shown in D) are output. As a result, color-expanded image data L1 and L2 shown in FIGS. 6(E) and 6(F) are output from the memory areas of look-up table circuits 813 and 14 corresponding to these image data D1 and D2.

Here, if the image data L2 (L22 and L24) in the second and fourth readout cycles shown in the figure are transparent, the transparent color determination circuit 16 selects the image data L1 in the second and fourth readout cycles. The selection control signal SEL shown in FIG. 6(G) for selecting the other image data L2 in another readout period is outputted, and thus the selector circuit 15 synthesizes the image data L2 as shown in FIG. 6(H). Image data C1 is obtained, and this is the latch circuit 17.
is synchronized with the clock signal CK and output as output image data OUT shown in FIG. 6(I).

In this way, the lookup table circuit 13
Priority is given to the image data L1 from
When is a transparent color, priority is given to the other image data L2, and the two images are combined. However, the color-expanded image data O
The UT is obtained and displayed by a CRT display.

[Problems to be Solved by the Invention] In the future, there is a tendency for many parts of color expansion devices to be constructed as gate arrays and integrated circuits. In that case, it is desirable to have a configuration that is as lean as possible and facilitates formation of a gate array.

In this case, it is desirable to efficiently use memory portions with high occupancy rates. At this time, image memories must be prepared separately depending on the number of images.

However, according to the above-mentioned circuit, since a look-up table circuit with the same configuration is provided for each image memory,
It can be said that there is a lot of waste.

If this look-up table circuit part is made simple, it is considered suitable for integration into an integrated circuit.

The present invention has been made in consideration of the above points, and has the following features:
The present invention aims to provide a display color expansion device capable of color expansion of image data from a plurality of image memories using lookup table circuits, and furthermore, capable of synthesizing the expanded image data. .

[Means for Solving the Problem] In order to solve the problem, in the present invention, image data from a plurality of image memories is color-expanded using a look-up table circuit, and at the same time, the color expansion is performed using a look-up table circuit. A display color expansion device that selects and outputs color-expanded image data includes a multiplexing means for multiplexing image data from a plurality of image memories in an output cycle of the color-expanded image data; One lookup table circuit that color-expands image data, and output image data that determines image data to be output in that output cycle based on the transparent color information of the multiplexed color-expanded image data for each output cycle. a determining means; and an image data selecting means for selecting from the multiplexed color-expanded image data from the look-up table circuit based on the determination information of the output image data determining means as image data of the output cycle. Prepared.

[Operation] Image data from a plurality of image memories are multiplexed within one output cycle by the multiplexing means, and then color expanded by one look-up table circuit. Based on the transparent color information of the color-expanded and multiplexed image data, the output image data determining means determines the image data to be output as the image data of the output cycle, and uses the determined image data as the image data. The data selection means selects and outputs the multiplexed image data.

As a result, even if a plurality of memories are provided as image memories, color expansion processing can be performed using one lookup table circuit.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1, in which parts corresponding to those in FIG. 5 are given the same reference numerals, a clock signal CKI with a duty ratio of 50% and twice the frequency of the conventional device is input as a clock signal. The signal is frequency-divided by two through the frequency circuit 20, converted into a lock signal CK, and applied to the address counter 10, as in the conventional case. The address counter 10 changes the address data AD in accordance with this clock signal CK, and outputs the image data D1,
Output D2.

In this embodiment, image data D1 and D2 output from each image memory 11 and 12 are provided to a selector circuit 21. A clock signal CK is given to the selector circuit 21 as a selection control signal, and the clock signal CK
The image data D1 and D2 are multiplexed and provided to the look-up table circuit 22 through a selection operation every half cycle. The lookup table circuit 22 receives the multiplexed image data DM as an address and outputs color-expanded image data LM from the corresponding memory area.

This color-expanded image data LM is converted into two image data (Ll, L2) included in one cycle of the clock signal CK by sequentially activating two stages of latch circuits 23 and 24 having a D-type flip-flop circuit configuration. > is selected and applied to the CRT display device via a digital/analog conversion circuit (not shown).

The latch command signal for selecting the color-expanded image data using the latch timing of the latch circuits 23 and 24 in this manner is generated by the first and second latch command signal generators 25 and 26. . The first latch command signal generating section 25 forms a latch command signal for the latch circuit 23, and the second latch command signal generating section 26 forms a latch command signal for the latch circuit 24.

The first latch command signal generating section 25 includes a two-input OR circuit 2
Equipped with 7. This OR circuit 27 has a clock signal CK.
and CKi, and outputs a pulse signal P1 having the same frequency and phase as the clock signal CK and having a duty ratio of 75%. Further, the first latch command signal generation section 25 has a two-input OR circuit 28. The OR circuit 28 is supplied with the clock signal CK inverted via an inverter circuit 29, and is directly supplied with the other clock signal CKI, which has the same frequency as the clock signal CK and a phase of half a period. A pulse signal P2 with a duty ratio of 75% is output. These pulse signals P1 and P2 are given to the selector circuit 30.

Here, the pulse signal P1 is the image data of the first half of the image data multiplexed within one period of the tarok signal CK,
That is, the timing is determined so that the color-expanded image data L1 corresponding to the image memory 11 can be latched.

On the other hand, the pulse signal P2 takes a timing at which the second half of the multiplexed image data, that is, the color-expanded image data L2 corresponding to the image memory 12, can be latched within one period of the clock signal CK. It is. Note that the image data L from the lookup table circuit 22
Since M is almost synchronized with the clock signal CK, it is also almost synchronized with these pulse signals P1 and P2.However, since the delay time associated with the read operation from the lookup table circuit 22 is large, these pulse signals P1 and P2
is designed to provide a stable latch timing.

A selection control signal for the selector circuit 30 is formed based on the determination result of the transparent color determination circuit 31. The color expanded and multiplexed image data LM output from the lookup table circuit 22 is input to the transparent color determination port 831, and the transparent color determination is performed on this time-series image data LM to generate a determination signal H. It is converted and applied to the latch circuit B32 having a D-type flip-flop circuit configuration. This latch circuit 32 is given a clock signal CKI as a latch command signal, and is synchronized with the clock signal CK.

This synchronized discrimination signal H8 is applied to the OR circuit 33. The OR circuit 33 is also directly supplied with the clock signal CK, and its OR output is supplied to the selector circuit 30 as a selection control signal.

Therefore, even if both of the color-expanded image data corresponding to the image memories 11 and 12 have a transparent color, the OR circuit 33 determines that the color-expanded image data corresponding to one of the image memories 11 is a transparent color. Logic “0” only if
A significant transparent color determination signal H3 is obtained and applied to the selector circuit 30. That is, the OR circuit 33 receives the clock signal CK
Logic "0" when the first half of the image data L1 of the image data LM that has been multiplexed within one cycle and has been extended in brown color is transparent.
, and when the latter half of the image data L2 is transparent, the logic is "1".
” is output.

In addition, during the period when the color is not transparent, the judgment signal H5 is logic "1".
I try to take it.

The selector circuit 30 selects the pulse signal P2 when the selection control signal H8 indicates a transparent color, and selects the pulse signal P1 when the selection control signal H8 does not indicate a transparent color. therefore,
The selector circuit 30 selects image data L in the first half of one clock cycle of the multiplexed color-expanded image data.
1 is not a transparent color, the first half image data is latched by the latch circuit 23 for only one clock cycle, and when the first half cycle image data L1 is transparent color, the image data arriving in the first half of one clock cycle is latched by the latch circuit 23. The output pulse signal C0N1 is formed by switching and controlling the pulse signals P1 and P2 so that the first half is latched as is and the second half is latched as is.

The latch command signal generation section 26 includes an inverter circuit 35 and a D-type flip-flop circuit 36.

A clock signal CK is applied to the data input terminal of the flip-flop circuit 36, and the other clock signal CKI, which is inverted via the inverter circuit 35, is applied to the clock input terminal. In this way, the flip-flop circuit 35 obtains a signal having the same period and duty ratio as the clock signal CK, but whose phase is delayed by 1/4 period with respect to the clock signal CK, and sends it to the latch circuit 24 as the latch command signal CON. Output. Based on this latch command signal COH, the latch circuit 24 further latches the latch signal LT from the latch circuit 23 and outputs it as output data 0tJT1.

In the above configuration, when the clock signal CKI shown in FIG. 2 (A>) is given, the clock signal CKI shown in FIG. This clock signal CK is applied to the address counter 10, and the address data AD shown in FIG. 2(C) is sequentially incremented.As a result, the address data AD shown in FIG. Image data D1 and D2 shown in and (E) are output, and are multiplexed by selector circuit #121.

The multiplexed image data DM shown in FIG. 2(F) is outputted to the lookup table circuit 22, and color-expanded by the lookup table circuit 22, resulting in the color-expanded image shown in FIG. 2(G). Data LM is output.

Further, a pulse signal P1 for latching the first half data L1 of the multiplexed image data LM shown in FIG. given,
Further, from both clock signals CK and CKI, a pulse signal P2 shown in FIG. Given.

Here, assuming that the first half data L12 and Li2 of the second and fourth clock cycles of the clock signal CK in FIG. 2 are transparent color data, the transparent color determination circuit 31 sends the determination signal shown in FIG. () is output, this is synchronized with the clock signal CK by the latch circuit 32, the transparent color portion of the first half data L1 is extracted via the OR circuit 33, and the determination signal shown in FIG.
0 as the selection control signal H3.

In this way, the latch command signal C0NI as shown in FIG. Data L1
is output for only one clock period, and for the clock period whose first half includes the transparent color image data L1, the first half and the second half image data L1 and L2 are output as shown in FIG.
A latch signal LT shown in M) is obtained from the latch circuit 23 and applied to the latch circuit 24.

Further, from both clock signals CK and CKI, a latch command signal CON shown in FIG. CON is applied to latch circuit #I24. Based on this latch command signal CON, the latch circuit 24 performs a latching operation, and the image data LMF in the first half of each multiplexed clock cycle G is transmitted from this latch circuit 24 as shown in FIG. If the image data is not a color, the image data is output for one clock cycle, and if the first half of the multiplexed image data L1 is transparent color image data, the second half of the image data L2 is output for one clock cycle. Output image data 0UTI to be output is formed.

Therefore, according to the embodiment described above, even when a plurality of memories are provided as image memories and image data is selectively output, color multiplexing can be performed using one lookup table circuit, and the configuration is simple. , a compact display color expansion device can be obtained. As a result, a circuit suitable for integration can be realized.

In the above-described embodiment, an example having two image memories is shown, but the invention can be similarly applied to an example having three or more image memories.

Further, the display color expansion device of the present invention can be applied to devices having a plurality of image memories, regardless of the type of device.
For example, it can be applied to a captain terminal device, a personal comparator, a teletext receiving device, etc. Although the number of bits of image data before expansion differs depending on the application device, the present invention can be applied even if the number of bits before expansion differs.

Further, the configuration for multiplexing image data before color expansion and the configuration for selecting color-expanded image data according to the multiplexed image data are not limited to the configurations of the above-described embodiments.

[Effects of the Invention] As described above, according to the present invention, it is possible to configure a device that switches image data from a plurality of image memories, expands the color, and outputs it using a single lookup table circuit. It is possible to obtain a display color expansion device suitable for forming an integrated circuit into a compact and simple integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a display color expansion device according to the present invention, and FIG. 2 is a timing chart of each part thereof.
Figure 3 is a block diagram showing the configuration when outputting image data without color expansion, Figure 4 is a block diagram showing the basic configuration when outputting image data with color expansion, and Figure 5 is the conventional configuration. FIG. 6 is a block diagram showing a color expansion device, and a timing chart of each part of the conventional device. 10...Address counter, 11.12...Image memory, 20...2 frequency divider circuit, 21.30...Selector circuit, 22...Lookup table circuit, 23.
24.32.36...Latch circuit, 27.28.33
. . . OR circuit, 29.30.35 . . . Inverter circuit, 31 . . . Transparent color determination circuit.

Claims (1)

[Scope of Claims] A display color that expands the color of image data from a plurality of image memories using a lookup table circuit, and selects and outputs the color-expanded image data that corresponds to one of the image memories. The expansion device includes: multiplexing means for multiplexing image data from the plurality of image memories in an output cycle of color-expanded image data; and one look-up table circuit for color-expanding the multiplexed image data. and output image data determining means for determining image data to be output in each output cycle based on the transparent color information of the multiplexed color-expanded image data for each output cycle, and multiplexing from the look-up table circuit. and image data selection means for selecting from the color-enhanced image data based on the decision information of the output image data decision means and selecting it as image data of the output cycle. .