JPH01277033A - Code error detecting system - Google Patents

Abstract

PURPOSE:To enhance detecting accuracy for a code error apt to occur on a transmission path by putting in a frame the last (n) figures of a binary number which expresses the result of counting the number of bits of 1 or 0 in one frame on a transmitting side, sending them and comparing the sent information about the last (n) figures with a result of counting and processing by the same technique on a receiving side. CONSTITUTION:On the transmitting side of a system to supervise the line quality of digital communication and detect the code error, the number of the information bits to show either a logic 1 or a logic 0 in one frame is counted by a counting means. A part corresponding to the last 2 figures when the result of the counting is expressed with the binary number are inserted as a transmitting side counting result P1 and P2 as bits to show code error supervising information. A synchronization is obtained by a frame synchronizing circuit on the receiving side, the number of the information bits of 1 is counted, the last 2 figures when its result is expressed with the binary number is sent to a comparing circuit 3 as a receiving side counting result signal 8, they are compared with the transmitted P1 and P2 taken out by the circuit 4 and when they do not coincide, a code error pulse is outputted.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention provides code error detection that is checked on the receiving side based on code error monitoring information inserted at the transmitting side in order to monitor the quality deterioration of a digital communication line. The present invention relates to a detection method, and particularly to a code error detection method that can accurately detect quality deterioration in a transmission path.

(Prior Art) A typical conventional code error detection method for digital communication lines is a parity check method.

In this parity check method, the transmitting side counts the number of "1" or "0" information bits in one frame, and adds a so-called parity bit, which indicates whether the number is even or odd, to the transmitted signal string. Send it to the transmission path, count the number of information bits "1" or rOJ in one frame on the receiving side, and compare the even/odd information of that number with the parity bit information to detect code errors in the received signal. are doing.

(Problems to be Solved by the Invention) In the conventional parity check method described above, when two or more errors occur in one frame, if the number of errors is an even number, the receiving side that should be compared with the parity bit The disadvantage is that error detection cannot be performed because the code error monitoring information does not change. In particular, since the transmission path has conditions that make it easy for consecutive code errors to occur, even number of code errors like this often occur, which is an important problem.

The purpose of the present invention is to eliminate such drawbacks and to provide a method for detecting code errors that affect the quality of digital communication lines, using a conventional method that can detect even an even number of code errors in one frame. The object of the present invention is to provide a more accurate error code detection method.

(Means for Solving the Problems) In order to achieve the above object, the code error detection method of the present invention requires the transmitting side to count the number of information bits representing either logical 1 or 0 in one frame. When the results of counting by the means are expressed in binary numbers, n is 2.
It has a means for inserting the lower one digit code error monitoring information, which is an integer above, into a predetermined position in the frame and sending it out to the transmission path. means 2 for counting the number of information bits representing one of the information bits;
The method has a means for comparing the last digit of n, which is an integer of 2 or more when expressed in base numbers, with the code error monitoring information in the frame sent from the transmitting side.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing relevant parts of a receiving side used in an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of the frame structure of a transmission line code transmitted from the transmitting side in the embodiment shown in FIG.

The frame used in this example is shown in FIG. 2(a).
It is configured as shown in K.

FIG. 2 (In the case of Xun, it consists of 1 bit of miframe synchronization pulse, 10 bits of information bit, and 2 bits of the counting result on the transmitting side.

Then, on the transmitting side, the number of logic "1" bits of the information bits in one frame is counted, and when the result is displayed in binary, the part corresponding to the last two digits represents code error monitoring information. P, , P shown in FIG. 2(a) as bits
, is placed in the position.

Therefore, for example, if the number of bits representing "1" in one frame is 0, 4, or 8, P8 is "0", P3 is "0", and the number of bits representing "1" is If the number is 1, 5, or 9, Pl is 0.
”, P.

Hereinafter, Pl # The bit "1" or "0" in the position of Pl becomes "1" as shown in FIG. 2(b). On the receiving side that receives such a transmission signal, error detection is performed using a configuration including a counting circuit 2, a comparing circuit 3, and a frame synchronization circuit 4, as shown in FIG.

The operation on the receiving side is synchronized by the frame synchronization circuit 4, and the counting circuit 2 counts the number of "1" information bits, and when the result is displayed in binary, the lower two digits are used as the counting result signal on the receiving side. 8 to the comparison circuit 3, while the frame synchronization circuit 4
The comparator circuit 3 extracts P, , P, indicating the counting result on the transmitting side and sends it to the comparator circuit 3 as the transmitting side counting result signal 7.
compares the two and outputs a code error pulse to the output terminal 9 if they do not match.

Note that 6 is a reset coefficient sent from the frame synchronization circuit 4 at the turn of every frame in order to reset the counting circuit 2.

Now, on the transmitting side, the number of "1" information bits is 5.
If there are only 1, "0" and "1" are entered in P%tPs, respectively.

If, on the transmission path, a code error occurs at two places in the information bit "0" in l frame, and the number of "1"s becomes 7, the counting result on the receiving side will be that Pl is "1" and Pl is "1". , is “1”
”, and the sender processing results P, rOJ, Pt rlJ
Since they are different from each other, it can be seen that a code error has occurred.

In this way, the occurrence of an even number of code errors, which could not be detected conventionally, can be known.

Furthermore, even when the number of bits containing code error monitoring information is set to 3 or more, the information bit code errors in one frame can be prevented by transmitting the counting result with an amount of information of n bits to a predetermined position in one frame. is less than or equal to 2n-1, then 2
Code errors of bits or more can be reliably detected. Further, even if the ratio is 2-1 or more, the code error detection accuracy is much higher than that of the conventional method.

(Effects of the Invention) As explained above, in the present invention, the transmitting side counts the number of bits of "1" or rOJ in one frame, and calculates the last digit (n is an integer of 2 or more) of the result expressed in binary. ) is sent in a frame, and the receiving side calculates and processes the result using the same method and compares the received last digit information.
This has the effect that detection accuracy for multiple code errors, which are particularly likely to occur on a transmission path, can be made extremely high.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a receiving side configuration according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing an example of a frame structure of a transmission line code used in the embodiment of FIG. 1. 2... Counting circuit 3... Comparison circuit 4... Frame synchronization circuit 5... Receiving side signal input terminal 6... Reset signal 7... Transmitting side counting result signal 8... Receiving side counting Result signal 9...Output terminal F...Frame synchronization pulse ■...Information bit

Claims (1)

[Claims] In a code error detection method for monitoring the line quality of digital communication, a transmitting side includes means for counting the number of information bits representing either logical 1 or 0 in one frame, and a result of counting by the means. When expressed as a binary number, the receiver side has a means for inserting the last n digits, where n is an integer of 2 or more, into a predetermined position in the frame as code error monitoring information and sending it out to the transmission path. means for counting the number of information bits representing either logical 1 or 0 in one frame; and lower n digits where n is an integer of 2 or more when the result of counting by the means is displayed in binary. A code error detection method comprising means for comparing the code error monitoring information with the code error monitoring information in the frame sent from the transmitting side.