JPH01276754A - Manufacture of cmos semiconductor device - Google Patents
Manufacture of cmos semiconductor deviceInfo
- Publication number
- JPH01276754A JPH01276754A JP63105795A JP10579588A JPH01276754A JP H01276754 A JPH01276754 A JP H01276754A JP 63105795 A JP63105795 A JP 63105795A JP 10579588 A JP10579588 A JP 10579588A JP H01276754 A JPH01276754 A JP H01276754A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon substrate
- substrate
- film
- cmos semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 241000406668 Loxodonta cyclotis Species 0.000 description 1
- 210000001015 abdomen Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- -1 phosphorous ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高速、高集積MO3半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a high speed, highly integrated MO3 semiconductor device.
高不純物濃度シリコン基板上に低不純物濃度シリコンエ
ピタキシャル層を成長させたシリコン基板を用いてCM
OS半導体装置を作製する場合、基板葛面は常に酸化膜
、窒化膜により覆っておく必要がある。シリコン裏面が
露出していると拡散炉中の熱処理において、高濃度シリ
コン基板から不純物が外方拡散し、他のシリコン基板表
面に入り込み基板抵抗率を変化させたり、炉内の至る所
に付着し汚染源となるからである。特にシリコン基板の
不純物としてボロンを用いるとその現象は強い。CM using a silicon substrate with a low impurity concentration silicon epitaxial layer grown on a high impurity concentration silicon substrate
When manufacturing an OS semiconductor device, it is necessary to always cover the surface of the substrate with an oxide film or a nitride film. If the backside of the silicon is exposed, impurities will diffuse outward from the highly concentrated silicon substrate during heat treatment in a diffusion furnace, enter the surface of other silicon substrates, change the substrate resistivity, or adhere to everywhere in the furnace. This is because it becomes a source of pollution. This phenomenon is particularly strong when boron is used as an impurity in the silicon substrate.
本発明はシリコン基板裏面を常に絶縁膜で覆っておくた
めに、基板と逆導伝型の深い拡散層を形成した後の酸化
膜除去工程をHF蒸気エツチャーにより行い、表面の酸
化膜だけを選択的に除去するものである。In the present invention, in order to always cover the back surface of the silicon substrate with an insulating film, after forming a deep diffusion layer of the opposite conductivity type to the substrate, the oxide film removal process is performed using an HF vapor etcher, and only the oxide film on the surface is selected. It is intended to be removed.
第3図に従来のボロンを不純物として用いたP壁高濃度
シリコン基板上に、ボロンを不純物として用いたP型低
濃度シリコンエピタキシャル膜を設けたP/P’型シリ
コン基板を用いてCMOSを製造する工程順の断面図を
示す。Figure 3 shows CMOS fabrication using a P/P' type silicon substrate in which a P-type low-concentration silicon epitaxial film using boron as an impurity is provided on a conventional P-wall high-concentration silicon substrate using boron as an impurity. A cross-sectional view of the process order is shown.
第3図(alはP/P”型シリコン基板中に比較的深い
N型ウェル3を拡散により形成した様子を示す。FIG. 3 (al indicates a state in which a relatively deep N-type well 3 is formed in a P/P" type silicon substrate by diffusion.
これはP/P”型シリコン基板からの外方拡散を防ぐた
めに、化学気相成長法(CVD法)により約5000人
酸化膜を裏面に被着したP/P”型シリコン基板を用い
て、まず酸化により5000〜6000人の酸化膜を成
長させ、次にフォトリソグラフィー工程によりフォトレ
ジストをパターニングし、ウェットエツチングにより後
にN型ウェルとなる場所の上の酸化膜を除去する。次に
酸化膜をシリコンが露出している部位上の厚さが約10
00人となるように成長させ、イオン注入法によりリン
イオンを1〜5×10′!/ci程度打ち込み、110
0℃〜1200°Cの温度にて、5〜15時間非酸化性
雰囲気中にて拡散を行う事により形成される。この時点
までP/P”型シリコン基板裏面の酸化膜は最初の酸化
により5000人から約10000人となり、酸化膜ウ
ェットエツチングにより1500〜2000人、イオン
注入前の酸化により2000〜2500人となっており
、P/P’型シリコン基板裏面は常に1000Å以上の
酸化膜により覆われておりP/P’型シリコン基板裏面
から不純物が外方拡散する事はない。This uses a P/P" type silicon substrate with approximately 5,000 oxide films deposited on the back side by chemical vapor deposition (CVD) to prevent outward diffusion from the P/P" type silicon substrate. First, an oxide film of 5,000 to 6,000 layers is grown by oxidation, then the photoresist is patterned by a photolithography process, and the oxide film above the area that will later become an N-type well is removed by wet etching. Next, apply an oxide film to a thickness of approximately 10 mm on the exposed silicon area.
00 people, and 1 to 5 x 10' of phosphorous ions are added using ion implantation method! /ci input, 110
It is formed by diffusion in a non-oxidizing atmosphere at a temperature of 0°C to 1200°C for 5 to 15 hours. Up to this point, the oxide film on the back side of the P/P" type silicon substrate had grown from 5,000 to about 10,000 due to initial oxidation, 1,500 to 2,000 due to oxide film wet etching, and 2,000 to 2,500 due to oxidation before ion implantation. The back surface of the P/P' type silicon substrate is always covered with an oxide film with a thickness of 1000 Å or more, so that impurities do not diffuse outward from the back surface of the P/P' type silicon substrate.
次にP/P”型シリコン基板表面の熱酸化膜4aを除去
するが、N型ウェル以外の領域上の酸化膜厚は6000
〜6500人であり、裏面の酸化膜厚は2000〜25
00人であるためそのままシェフトエソチングにより酸
化膜除去を行うとP/P”型シリコン基Fi裏面のシリ
コンは露出し、次工程の酸化において不純物の外方拡散
が起こる。そこで第3図(′b)に示すようにフォトレ
ジスト6をP/P”型シリコン基板裏面にコートして、
ウェットエツチングにより表面の酸化膜4aだけを除去
する。Next, the thermal oxide film 4a on the surface of the P/P" type silicon substrate is removed, but the oxide film thickness on the area other than the N type well is 6000.
~6500 people, and the oxide film thickness on the back side is 2000~25
00, so if the oxide film is removed by sheft etching, the silicon on the back surface of the P/P'' type silicon base Fi will be exposed, and the outward diffusion of impurities will occur in the next oxidation process. As shown in b), photoresist 6 is coated on the back surface of the P/P" type silicon substrate,
Only the surface oxide film 4a is removed by wet etching.
次に硫酸と過酸化水素の混合液によりフォトレジスト6
を除去しく第3図(C1)、次工程の酸化に進む。以後
裏面は常に酸化膜又は他の絶縁膜により覆われ熱処理や
酸化工程において不純物が外方拡散する心配はない。Next, photoresist 6 was applied using a mixture of sulfuric acid and hydrogen peroxide.
3 (C1), proceed to the next step of oxidation. Thereafter, the back surface is always covered with an oxide film or other insulating film, so there is no fear that impurities will diffuse outward during heat treatment or oxidation steps.
しかしP/P”型シリコン基板裏面にフォトレジストを
コートする際、素子を形成する側の表面はコーターの搬
送のためのベルトや真空チャックと接触し、表面が汚染
されたり、キズがついて歩留まりを下げる要因となる。However, when coating the back side of a P/P" type silicon substrate with photoresist, the surface on which elements will be formed comes into contact with the conveyor belt of the coater and the vacuum chuck, resulting in contamination or scratches on the surface, which reduces yield. This is a factor that lowers the amount.
上記課題を解決するために本発明は、U型ウェル形成後
の酸化膜除去工程をHF蒸気エツチャーにて行うように
した。In order to solve the above problems, the present invention uses an HF vapor etcher to perform the oxide film removal step after forming the U-shaped well.
上記によると、表面の酸化膜だけを選択的に除去でき、
裏面は酸化膜を残したままである事から工程を削減し、
しかも熱処理工程における不純物外方拡散を阻止できる
。さらに表面は常に非接触であり、歩留まりを落とす事
もない。According to the above, only the surface oxide film can be selectively removed,
The oxide film remains on the back side, reducing the number of steps.
Furthermore, outward diffusion of impurities during the heat treatment process can be prevented. Furthermore, the surface is always non-contact, so there is no reduction in yield.
以下に本発明の実施例を図面に基づいて説明する。第1
図はP/P”型シリコン基板を用いて、N型ウェル3を
形成した後、HF 77気エツチヤーチエンバー中に置
かれた様子を示す。HF蒸気エツチャーとしては例えば
米国FSI社製Excalibur等がある。ウェハー
はターンテーブル上に置かれており、HF蒸気は上方か
ら導入されるため、表面の酸化膜4aを除去した後でも
、裏面酸化膜4bのターンテーブル上に置かれた酸化膜
の減少は全くなく、ターンテーブル上ではない所はHF
蒸気の回り込みにより多少減少する。6インチ径ウェハ
ーを用いて、熱酸化膜6000人成長させ、表面の酸化
膜を除去した場合、裏面酸化膜厚はウェハーエッヂによ
り5龍の所は約500〜1000人の酸化膜が残り、1
0nの所は約3000人残り中心は6000人残る0第
2図はその様子を示した図である。従って、裏面の大部
分が2000Å以上の酸化膜に覆われており、後の熱処
理工程において、ボロンの外方拡散をほぼ完全に抑制で
きる。Embodiments of the present invention will be described below based on the drawings. 1st
The figure shows how a P/P" type silicon substrate is placed in a HF 77-gas etcher chamber after forming an N-type well 3. Examples of the HF steam etcher include Excalibur manufactured by FSI, USA, etc. Since the wafer is placed on a turntable and the HF vapor is introduced from above, even after removing the oxide film 4a on the front surface, the oxide film placed on the turntable on the back side oxide film 4b is removed. There is no decrease at all, and the area not on the turntable is HF.
It decreases somewhat due to the circulation of steam. When a 6-inch diameter wafer is used to grow a thermal oxide film of 6,000 layers and the surface oxide film is removed, the backside oxide film thickness will be approximately 500 to 1,000 layers depending on the wafer edge, and 1.
About 3,000 people remain at 0n, and 6,000 people remain at the center.Figure 2 shows this situation. Therefore, most of the back surface is covered with an oxide film of 2000 Å or more, and the outward diffusion of boron can be almost completely suppressed in the subsequent heat treatment process.
本発明は以上説明したように、P/P”型シリコン基板
を用いた場合のNウェル形成後の酸化膜除去をHF蒸気
エフチャーにて行う事により、レジストコート工程を削
減でき、表面は常に非接触であるため歩留まりを落とす
事もない。また、基板裏面の大部分を厚い酸化膜で覆っ
ているため、不純物の外方拡散を生じない。As explained above, the present invention uses HF vapor etcher to remove the oxide film after N-well formation when using a P/P'' type silicon substrate, thereby reducing the resist coating process and keeping the surface clean. Since it is a contact, there is no drop in yield.Also, since most of the back surface of the substrate is covered with a thick oxide film, outward diffusion of impurities does not occur.
第1図は本発明を説明するためのHF蒸気エツチャー中
のシリコン基板の様子を示す断面図、第2図はHF蒸気
エフチャー処理後の基板裏面の酸化膜残り具合を示す断
面図、第3図fal〜(C1は従来の製造方法の工程順
断面図である。
1・・・高不純物濃度シリコン基板
2・・・低不純物濃度シリコンエピタキシャル膜3・・
・N型ウェル
4a、4b・・・酸化膜
5・・・フォトレジスト
以上
出廓人 セイコー電子工業株式会社
狡峡MO5手導那置a肚加斜零オニ象・頂酢面図第3図FIG. 1 is a cross-sectional view showing the condition of a silicon substrate during HF vapor etching to explain the present invention, FIG. 2 is a cross-sectional view showing the amount of oxide film remaining on the back side of the substrate after the HF vapor etching process, and FIG. fal ~ (C1 is a cross-sectional view of a conventional manufacturing method in the order of steps. 1... High impurity concentration silicon substrate 2... Low impurity concentration silicon epitaxial film 3...
・N-type wells 4a, 4b...Oxide film 5...Photoresist and above Suppliers Seiko Electronics Co., Ltd. Kokyo MO5 Hand guide na position a belly Calculating zero Oni Elephant / Top surface view Figure 3
Claims (1)
シリコンエピタキシャル膜を設けたシリコン基板を用い
たCMOS半導体装置の製造方法において、基板と逆導
伝型の深い拡散層を形成した後の酸化膜除去工程をHF
蒸気エッチャーにより表面の酸化膜だけを選択的に除去
することを特徴とするCMOS半導体装置の製造方法。In a method for manufacturing a CMOS semiconductor device using a silicon substrate in which a low impurity concentration silicon epitaxial film is provided on a silicon substrate containing high impurity concentration, oxide film removal after forming a deep diffusion layer of conductivity type opposite to that of the substrate. HF process
A method for manufacturing a CMOS semiconductor device, characterized in that only a surface oxide film is selectively removed using a steam etcher.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63105795A JPH01276754A (en) | 1988-04-28 | 1988-04-28 | Manufacture of cmos semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63105795A JPH01276754A (en) | 1988-04-28 | 1988-04-28 | Manufacture of cmos semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01276754A true JPH01276754A (en) | 1989-11-07 |
Family
ID=14417061
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63105795A Pending JPH01276754A (en) | 1988-04-28 | 1988-04-28 | Manufacture of cmos semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01276754A (en) |
-
1988
- 1988-04-28 JP JP63105795A patent/JPH01276754A/en active Pending
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