JPH01274578A - Picture storage device - Google Patents

Abstract

PURPOSE:To allow the storage device to flexibly cope with each status by revising a blanking region at fetch or readout of a picture in a picture memory as required. CONSTITUTION:The field of a reproduced video signal being a field picture and the field from a reference synchronizing signal generating circuit 250 are matched and color difference discrimination is applied during 1V period. Then a selector 254 selects a synchronizing signal generating circuit 248 and reduces the picture of the reproduced video signal in the succeeding 1V period and writes it into a picture memory of picture memory circuits 228, 230. Then the selector 254 selects the circuit 250 to read the picture memory. The circuit is operated by a blanking signal by the latch circuit. Then the reproduction track of a magnetic sheet 215 is fed to store the reduced picture, the field picture or the frame picture is obtained. Thus, the blanking region is revised freely as required and proper region is set.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an image storage device.

[Conventional technology]

Conventionally, in an image recording and reproducing device having an image memory, the image memory stores only the image area (non-blanking area) of the input image. The area was reduced and written to the image memory.

In addition, when reading a reduced image and superimposing it on an input image, it has a signal indicating the image area of the reduced image and a signal indicating a frame area for adding a frame to the reduced image, and superimposes the image using this signal. Ta.

[Problem to be solved by the invention]

However, in the conventional example, when reducing and storing an input image in an image memory, a method is used in which the image area of the input image is reduced and written in the image memory, so as shown in FIG.
When you import reduced images into image memory in a grid pattern,
It is not possible to display all of this on the monitor screen,
The drawback is that part of the reduced image is missing.

In addition, when trying to superimpose a reduced image on an input image, in addition to the signal indicating the image area of the reduced image, there is a drawback that a signal indicating the frame area for attaching a frame to the reduced image must be provided separately. be.

Therefore, an object of the present invention is to provide an image storage device that eliminates the above-mentioned drawbacks.

[Means to solve the problem]

The image storage device according to the present invention is characterized in that it is equipped with a means for changing the blanking area as necessary when loading or reading an image into the image memory. By being able to change it accordingly, it is possible to set an appropriate area according to each situation, and the above-mentioned drawbacks of the conventional example can be solved.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a block diagram of the overall configuration of a still image recording and reproducing apparatus to which the present invention is applied. 210 is a video input terminal for inputting a video signal from the outside, 212 is a decoder that separates the video signal into a luminance signal and a color difference signal, and 214 is a switch that is switched in synchronization with horizontal synchronization signals H1A and H1C from the decoder 212. The two color difference signals R-Y and BY outputted from the decoder 212 are converted into line-sequential color difference signals. 216 and 217 are magnetic heads that reproduce video signals recorded on the magnetic sheet 215, which is a magnetic recording medium; 218 is a switch that selects the magnetic head 216 or 217; and 220 is a switching control circuit that controls switching of the switch 218. , 222 is a reproduction circuit that demodulates the reproduction output of the magnetic heads 216 and 217 and outputs a luminance signal and a line-sequential color difference signal, and 224 selects the luminance signal from the decoder 212 or the luminance signal from the reproduction circuit 22.2. A switch 226 is a switch for selecting the line sequential color difference signal from the decoder 212 or the line sequential color difference signal from the reproduction circuit 222.

228.230 is an input/D converter, an image memory and a D/D converter.
The image memory circuit 228 is for luminance signals, and the image memory circuit 230 is for color difference signals. The image memory circuit 230 outputs color difference signals in line-to-line time. 232 is the output of the decoder 212 (luminance signal and two color difference signals) or the image memory circuits 228, 23
A switch for selecting the output of 0, 234 is the switch 232
An encoder 236 performs modulation, synthesis, etc. on the luminance signal and color difference signal from the encoder, and 236 is an output terminal for the synthesized video signal.

A switch 238 converts the two color difference signals outputted from the image memory circuit 230 into line-sequential signals, and is switched in synchronization with the horizontal synchronization signal. 240 is a recording circuit that performs various processing for magnetic recording such as modulation on the luminance signal and color difference signal from the image memory circuit 228 and 230 (more precisely, the switch 238); 241 and 242 are magnetic sheets 243; A magnetic head 244 magnetically records signals from the recording circuit 240, and a switch 244 selects between the magnetic heads 241 and 242.

246 is a synchronization separation circuit that separates a synchronization signal from the luminance signal selected by the switch 224, and 248 is a PLL that separates a clock, horizontal synchronization signal, vertical synchronization signal, etc. synchronized with the horizontal synchronization signal output from the synchronization separation circuit 246. 250 synchronous signal generation circuit that generates various synchronous signals
is a reference synchronization signal generation circuit that generates various synchronization signals such as a clock, a horizontal synchronization signal, and a vertical synchronization signal using a crystal resonator. By turning on the reset switch 252, the reference synchronization signal generation circuit 250 is brought into a reset state by an external horizontal synchronization signal, vertical synchronization signal, or the like. A selector 254 selects the output of the synchronization signal generation circuit 248 or the reference synchronization signal generation circuit 250, and the selection signal is applied to the image memory circuits 228, 230 and the encoder 234. 256 is the circuit 248, 250
This is a comparison circuit that compares the fields of synchronization signals output from the synchronous signals, and controls head switching by the switching control circuit 220 and the image memory circuits 228 and 230 depending on whether the fields match or do not match.

, in FIG. 2, in the recording mode in which an input video signal from the outside is recorded on the magnetic sheet 243, switch 2 is turned on.
24 and 226 select the decoder 212 side. The input signal of the input terminal 210 is separated into a luminance signal and a color difference signal by a decoder 212, and the luminance signal is applied to the image memory circuit 228 via the switch 224, and the color difference signal is made line sequential by the switch 214 and applied to the image memory circuit 230. be done.

By operating a recording command key (not shown), the image is stored in the image memory circuits 228 and 230.

At this time, the selector 254 has selected the synchronization signal generation circuit 248, and the image memory circuits 228, 230 and encoder 234 operate according to the synchronization signal from the circuit 248. Note that the motor (not shown) that rotates the magnetic sheet 243 always rotates in synchronization with the vertical synchronization signal output from the reference synchronization signal generation circuits 2 and 50, and the reset switch 252 must be turned on. The device enters the external reset state and synchronizes to the input video signal.

Next, the selector 254 selects the reference synchronization signal generation circuit 250, and the image memory circuits 228, 230 and encoder 234 operate according to the synchronization signal. The image memory circuits 228 and 230 are in the continuous state, and the zero color difference signal that outputs the luminance signal and the color difference signal is line sequentialized by the switch 238. A recording circuit 240 performs recording processing, and its output is recorded on a magnetic sheet 243 by magnetic heads 241 and 242. The reset switch 252 is kept in the OFF state during the recording period on the magnetic sheet 243 (two vertical intervals, ie, 2■ for a frame image, and IV for a field image).

After the recording on the magnetic sheet 243 is completed, the selector 254 selects the synchronization signal generation circuit 248 again.

Then, the images stored in the image memories 228 and 230 are read out in a reduced size, and a signal superimposed on the input video signal is applied to the encoder 234 by switching control of the switch 232. As a result, the video signal at the output terminal 236 represents an image in which the image recorded on the magnetic sheet is displayed in a reduced size as a part of the image of the input video signal.

Next, a reproduction mode for reproducing the recorded signal on the magnetic sheet 215 will be explained. In the reproduction mode, the magnetic heads 216, 21
The reproduction output of 7 is demodulated by the reproduction circuit 232 and sent to the image memory circuits 228 and 23 via switches 224 and 226.
0 and stored. The output of the image memory circuits 228 and 230 is output from the switch 23 at the same time as the storage.
2 and an encoder 234 to an output terminal 236. At this time, the selector 254 selects the synchronization signal generation circuit 2.
48 is selected, and the reset switch 252 is kept in the off state.

When writing to the image memory circuits 228 and 230 is completed,
The selector 254 selects the reference synchronization signal generation circuit 250, and the image memory circuits 228 and 230 enter the successive state.

FIG. 1A shows a detailed block diagram of the image memory circuit 228. 100 is an A/D converter that digitizes the input analog luminance signal; 102 is a clamp circuit; 104
is a K (0<K<1) times multiplier, 106 is (1-K)
108 is an adder that adds the outputs of the multipliers 104 and 108, 110 is a selector that selects one of the inputs of the multipliers 104 and 108 and the output of the adder 108, and 112 is a selector that selects predetermined data. 114 is a selector that selects the output of the selector 110 or the output of the latch circuit 112, and 116 is a random access port (hereinafter referred to as P port) and a serial output port (hereinafter referred to as S boat). A dual port image memory 118 having a dual port 5 latches three pixels worth of image data output from the selector 114 and outputs it in parallel, and serially outputs three pixels worth of image data output from the image memory 118. -p-s conversion circuit.

120 is 3 output from the S port of the image memory 116.
Latch circuit for temporarily storing image data for pixels, 122
124 is a selector that switches and selects the output of the latch circuit 120 at a video rate; 124 is a 5-ps conversion circuit 118;
126 is a selector that selects the output of adder 124 or the output of selector 122, and 128 is D that converts the output data of selector 126 into an analog signal.
/A converter.

130 is a blanking signal generation circuit that outputs a signal indicating a blanking area, 132 and 134 are latch circuits that hold a signal that determines a blanking area, and 136 is an address signal for random access boat of the image memory 1160 (hereinafter referred to as A P address generation circuit 138 generates a P address signal (referred to as a P address signal);
Boat address signal (hereinafter referred to as S address signal)
140 is a selector that selects the output of the P address generation circuit 136 or the S address generation circuit 138, and 142 is a memory control circuit that controls the image memory 116.

FIG. 1B shows a detailed configuration block diagram of the image memory circuit 230. Note that the circuits 100 to 110 in FIG. 1B are the same as in FIG. 1A except that the circuits 100 to 110 in FIG. , and the circuits 130 to 142 are the first
It has the same effect as the one in figure A. 150 is a color difference discrimination circuit that discriminates color difference signals R-Y and B-Y of line sequential color difference signals; 152 and 154 are latch circuits that hold predetermined data;
154 is a selector that selects the output of the launch circuits 152 and 154; 158 is a selector that selects the output of the selector 110 or 156; 160 is a launch that stores the image data from the selector 158 at a normal video rate of 173; 162 (162a, 162b) is an image memory having dual ports like the image memory 116; 164 is a latch circuit that holds two image data output from the S port of the image memory 162; 166 is a latch circuit 164; selector for selecting two outputs of 168
170 and 172 are adders that add the output of the launch circuit 168 to the output of the latch circuit 164; 174,17
6 is the output of the latch circuit 164 or the adder 17, respectively.
Selector for selecting output of 0,172, 178,180
is a selector that selects the output of selectors 174 and 176,
182° and 184 are D/A converters.

Clamp circuit 102 and 1B of FIGS. 1A and 1B
The detailed configuration block diagram of the color difference discrimination circuit 150 shown in the figure is shown in the third figure.
Shown in Figure A. In FIG. 3A, 300 is an A/D converter 100
302 is an adder, 304 is an input terminal for image data from
is the output data of the adder 302 as n (an integer greater than 1)
306 is a multiplier that multiplies the output of the launch circuit 304 by 1/n; 308 is a subtracter that subtracts the output data of the multiplier 306 from the input data of the input terminal 300; 310 is a subtraction circuit; A processing circuit 312 is an output terminal for outputting the output data of the processing circuit 310, and is connected to the multiplier 108 and the selector 110. In the color difference discrimination circuit 150, 3
14 is a launch circuit that holds the output of the latch circuit 304 at a specific timing; 316 is a comparison circuit that compares the output of the launch circuit 304 with the output of the latch circuit 314; 318
is a counter that counts the comparison results of the comparison circuit 316;
320 is a latch circuit for notifying as a flag whether the count value of the counter 318 has exceeded a predetermined value.

The operation of FIG. 3A will be explained. When the image data input to the input terminal 300 is luminance signal data, the latch circuit 3
04 is cleared to zero during the horizontal sync period. and,
A clock is applied to the latch circuit 304 n times (an integer greater than 1) during the bank poaching period of input image data, and cumulative addition is performed n times. Adder 302 adds the output of latch circuit 304 to input image data, and applies the addition result to latch circuit 304 . Due to this loop, data for the bank porch period, that is, a value obtained by adding the pedestal level value n times, is stored in the latch circuit 304.

Next, the output of the latch circuit 304 is converted to 1 by the multiplier 306.
/n, and find the average value of n-time additions of the pedestal level. When the subtracter 308 subtracts the output of the multiplier 306 from the input image data, the image data at the output terminal 312 is clamped to 00□8. Note that if the output of the subtracter 308 underflows, the processing circuit 310 forcibly sets it to 0OHzx.

In FIG. 3A, even when the input image data is line-sequential color difference signal data, it can be clamped to 00HtX in the same way as the luminance signal. However, since color difference signals have positive and negative polarities, 80H! If X is determined to be O■, 80, ltx must be clamped. If the input image data is RY/BY(t) and the n-times addition average value of the pedestal level is 1/nΣ'Pi tllll, then in order to perform 80□8 clamping,
This is equal to 00□8 clamps plus 808EX.

Normally, there is no burst signal in the luminance signal and color difference signal output from the decoder 212 (FIG. 2), but burst signals with small amplitudes may remain due to leakage in the circuit. In such a case, if the above-mentioned clamp is performed, the frequency of the clock applied to the latch circuit 304 during the back porch period (burst signal period) is set to 2mfB (m is a positive integer, rsc is the subcarrier frequency), and the number of cumulative additions is increased. 21 times (l is a positive integer), and the coefficient of the multiplier 306 is 1/21. Thereby, the burst signal component can be canceled. In this case, this is not limited to clamping of luminance signals and color difference signals, but also clamping of N where burst signals exist.
The TSC signal can also be applied directly to clamping.

The operation of the color difference discrimination circuit 150 will be explained. The signal B-Y of the line-sequential color difference signal recorded on the magnetic sheet has an offset value, and is higher than the signal R-Y by this amount.

Therefore, by comparing the n-time addition value of the data input during the back porch period with the data before or after IH during the clamping described above, the line-sequential color difference signals RY and B-Y can be determined. This will be explained in more detail with reference to FIG. 3B. 3B (a) shows the reproduction line sequential color difference signal input to the input terminal 300, (b) shows the horizontal synchronization signal, (C) shows the clock controlling the latch circuit 314, and (d) shows the counter 31.
This is the clock applied to 8. Note that the counter 318 is cleared to zero during the vertical synchronization period. Latch circuit 304
The output of is determined during the back porch period and is shown in Figure 3B (C).
It is latched by the launch circuit 314 at the timing of . The output of the latch circuit 304 is newly determined in the next back porch period, and this output and the output of the latch circuit 314 are compared by the comparison circuit 316. Based on the comparison result of the comparison circuit 316, it is controlled whether or not the counter 318 performs counting. This is done for one field period, and depending on whether the count value of the counter 318 is larger than a predetermined value, the latch circuit 320
Determine the flag of.

In other words, in order to reliably perform color difference discrimination even if there is noise or dropout, a counter 318 is provided to take a majority vote within one field period.
It is possible to know whether -Y and BY are even or odd rasters, respectively.

The configuration shown in FIG. 2 has a recording mode in which the input video signal is recorded on the magnetic sheet, and a reproduction mode in which the recorded video signal is reproduced from the magnetic sheet. First, the operation in recording mode will be explained. FIG. 4A shows the flowchart, and FIG. 4B shows the time chart. In Figure 4B, 410
412 is a freeze signal; 414 is a signal indicating the recording period; 416 is a signal indicating the superimposition period of the reduced image; 418
is a selection signal of the selector 254, and is a signal indicating that the synchronization signal generation circuit 250 has been selected. 420 is a signal indicating a reset state in which the reset switch 252 is on.

Selector 254 selects synchronization signal generation circuit 248, and reset switch 252 is turned on. Then, switch 232 selects the input video signal side, and input terminal 2
The 10 input video signals are output as they are to the output terminal 236 (S400). Next, the image memories 116, 16
2 to a predetermined value (S401), image memory 11
In the case of 6, a predetermined value is latched in the latch circuit 112,
This is selected by the selector 114, and the 5-p-s conversion circuit 1
One frame is written into the image memory 116 via 18.

The launch circuit 132 is set with a value indicating a blanking area so as to satisfy all the normal image areas, and the latch circuit 134 is set with a value indicating a blanking area so as to clear all the memory space of the image memory 116. While clearing the 0 image memory 116 to be set, it operates using a blanking signal from the latch circuit 134, and at other times, it operates using a blanking signal from the latch circuit 132.

Furthermore, regarding the image memory 162, the latch circuit 320
is set to indicate the R-Y signal, and then a predetermined value is set in the latch circuits 152 and 154, and the selector 156 selects the latch circuits 152 and 154 at the timing of the horizontal synchronization signal.
This is selected by the selector 158.

Then, one frame is taken into the image memory 162 via the latch circuit 160. However, writing to the image memories 162a and 162b is switched for each raster. Furthermore, the blanking area of the blanking signal generation circuit 130 is set so as to completely clear the memory space of the image memory 162, but this is the same as in the case of the image memory 116. As a result, the image memory 162a is completely cleared to the setting value of the latch circuit 152, and the image memory 162b
are all cleared to the setting value of the latch circuit 154, the image memory 162a becomes the RY memory, and the image memory 162b becomes the B-y memory.

When a command to record an input video signal onto a magnetic sheet is input (S402), the input luminance signal is changed to A/A in FIG. 1A.
D converter 100. Clamp circuit 102, selector 110
．． 114 and a 5-ps conversion circuit 118, one frame is written into the image memory 116. At this time,
A latch circuit 132 that indicates the image area of the input luminance signal.
It is operated by a blanking signal.

Further, the input color difference signal is converted into a line sequential signal by a switch 214. At this time, it is optional to select which of the R-Y component and the B-Y component comes first, but since the latch circuit 320 was set to indicate R-Y at the time of clearing, in this example, the R-Y component need to be done first. This line-sequential color difference signal is written into the image memory 162 for one frame via the A/D conversion 100, the clamp circuit 102, the selectors 110 and 158, and the latch circuit 160 in FIG. 1B. At this time, the latch circuit 132 operates with a blanking signal so that the entire image area of the input line sequential color difference signal can be stored, and after the vertical blanking period ends, the first raster to be stored is The image data is taken into the image memory 162a, the image data of the second raster is taken into the image memory 162b, and thereafter, it is taken in alternately for each raster. As a result, the RY component of the input line sequential color difference signal data is taken into the image memory 162a, and the B-Y component is taken into the image memory 162b (
S403).

Next, selector 254 selects the output of synchronization signal generation circuit 250 and turns off reset switch 252. Then, the image memories 116 and 162 are read out and recorded on the magnetic sheet (S404). That is, in FIG. 1A, the image data stored in the image memory 116 in frames is read out from the S port, and the latch circuit 120, selector 122,
126 to a D/A converter 128. When recording frame images to be stored in the image memory 116 on a magnetic sheet, it is sufficient to record one frame of the output of the D/A converter 128. When recording as a field image, the average of image data between fields is taken and recorded. The averaging between fields corresponds to filtering between fields.

That is, the signal of the first field of the image data stored in the image memory 116 as a frame is sent to the S address generation circuit 13.
8, from the 1st rusk, S boat truck 1, YO + Yl
+YZ+Y3+Y4+ '-, and so on, sell 8.

At the same time, the P address generation circuit 136 sequentially reads out the signal of the second field from the P boat starting from the first rask as Y0° mountain + hZY3' + Y4Z'-''.The selector 126 selects the output of the adder 124. Therefore, the output of the D/A converter 128 is (YO+YO')
/2. (Yl+Yl")/2. (yz+yz')/2
．． (Y3+Yi')/2. (Y4+Y4.')
/2. - and record this as one field.

Further, the color difference signal is handled as follows. In FIG. 1B, the image data stored in the image memory 162 in frames is simultaneously transferred from the S boat by two rusks to RYo, RYo,
RYz, RYz, BY4. BY4. RYE, R
Yb, -'-BY+, BY+, BY3. B
h, BYs, BYs, BY7. Read out as BY71-. Latch circuit 164 and selector 174
~180, the D/A converters 182 and 184 always output R-Y and BY signals, respectively.

When recording the image stored in the image memory 162 as a frame image on a magnetic sheet, the switch 23 is alternately activated for each rask from the component (RY) indicated by the latch circuit 320.
8 (Fig. 2), RYo, BY+
, RYz, BY2. RYa, BYs, RYiBY71'
Line-sequentialize as -. This is recorded for one frame on a magnetic sheet. Further, at this time, data may also be read from the P boat at the same time to perform synchronization as described later.

On the other hand, in the case of field recording, the average of image data between fields is taken and recorded. That is, one field of the image data recorded in the image memory 162 as a frame is simultaneously transmitted from the S port by two rusks: RYO, RYO, RYt, BY2 . BY4. BY4. R
YE, RYE, -m-BY+, BY+, BY
3. BY3. BYS, BYS, RYt, RY
It is read out as t, -. At the same time, change the other field from P port to R-Y and B-Y rasters alternately.
Y, ", BY+', RYz', BYI', BY4
It is read out as ゛, BYs', .-. Selectors 174 and 176 both switch input signals every rask, and selectors 178 and 180 switch input signals from D/A converter 182.1.
84 are switched to always output R-Y and B-Y signals, respectively. As a result, the output of the D/A converter 182 is (RYO+RYO')/2. RYO, (RYz
+RYz°)/2. RYt, (RY.

+RY4')/2. RYt becomes -, and D/A converter 1
The output of 84 is BYl, (BY++BY1')/2. B
Y3. (BYs+BYi')/2. BYs.

(BY, +BY5')/2. −=.

Here, from the component (RY) indicated by the latch circuit 320, 1
When the switch 238 is alternately switched for each raster, the raster becomes a raster in which addition and averaging are always performed, and the output of the switch 238 is (RYO+RYO')/2. (BYl+BY
1”)/2+ (RYz+Rh')/2+ (BY3
+BY! )/21 (RY4+RY4')/2°(BYs+BY5")/2-. This is recorded on the magnetic sheet for one field.

Next, selector 254 again selects the output of synchronization signal generation circuit 248 and turns on reset switch 252. Then, the images stored in the image memories 116 and 162 are read out in a reduced size and superimposed on the human video signal (5405
). That is, in FIG. 1A, image data stored in frames in the image memory 116 is read out from the S port, and data for three pixels is latched into the latch 120. Selector 122
selects only one of these pixels. Image memo I71 by continuously outputting from S boat at video rate
The 16 stored images are 1/3 horizontally. Furthermore, by making the vertical address signal from the S address generation circuit 13B indicate an address every three rusks, the image memory 1
The 16 stored images are also reduced to 1/3 in the vertical direction.

Further, in FIG. 1B, two russes of image data stored in frames in the image memory 162 are simultaneously read out from the S port as RY and BY. Since the color difference signal has a narrow band, it is stored at the normal video rate of 173, so
When continuing at a normal video rate, the number of images stored in the image memory 162 becomes 173 in the horizontal direction. Furthermore, S
By making the vertical address signal from the address generation circuit 138 point to an address every 3 steps, RYo, RYz, RYb, RYs, RY+z, RY+4 are generated simultaneously from the S boat by 2 rusks.
．． -BYI, BY3. BY7. BYg, BYI3. BY
+s, ---, and the image memory 16
The stored image of No. 2 is also 1/3 in the vertical direction.

In FIG. 5A, if the areas other than the image out of the entire space of the image memories 116 and 162 are read out in duplicate in both the horizontal and vertical directions, it is easy to frame the image reduced to 1/3 Xi/3. Can be attached. That is, the S address generation circuit 138 normally outputs the horizontal address as X o - 11X, but here, it outputs the horizontal address as X+"""Xi("Xo)→x1→
xz, and the vertical address is usually V o =
y+, but here y1 → yz (=yo) → y, →
Output as y2. As a result, a frame can be formed as shown in FIG. 5B. When displaying a reduced image, the switch 232 is connected to the output side of the image memory circuits 228 and 230, and otherwise the input video signal (decoder 212) is connected to the output side of the image memory circuit 228, 230.
By connecting to the side of , it is possible to display a reduced image superimposed on the input image, as shown in FIG. 5C.

The control signal of the switch 232 is equal to the blanking signal of the blanking signal generation circuit 130, and the superimposition position of the reduced image can be moved by changing the blanking signal. Here, a new value is set in the latch circuit 134, and the latch circuit 134 is operated by the blanking signal.

Next, move the recording heads 241 and 242 (5406).
, enters a standby state until the next recording command is input, and then repeats the above operations.

Incidentally, FIG. 4A is a time chart in the case of frame recording of the input video signal on the magnetic sheet, and
16.162 is cleared and recorded on the magnetic sheet twice.

Next, the playback mode will be explained. FIG. 6A shows the flowchart, and FIGS. 6B and 6c show the time charts. 610 and 612 are synchronization signal generation circuits 24
8,250 is a generated field signal, 614 is a signal indicating the color difference discrimination period of the reproduction line sequential color difference signal, 616 is a freeze signal, and 618 is a selection control signal of the selector 254, which indicates that the synchronization signal generation circuit 250 has been selected. A signal 620 indicates the state of the reset switch 252 (reset when on).

The synchronizing signal generating circuit 248 is synchronized with the horizontal synchronizing signal of the reproduced video signal reproduced from the magnetic sheet 215, and is reset by the vertical synchronizing signal, so that it outputs the same synchronizing signal as the synchronizing signal of the reproduced video signal. In addition, the magnetic sheet 21
5 rotates in synchronization with the vertical synchronization signal output from the reference synchronization signal generation circuit 250, and since the reset switch 252 is off, the reproduction reproduced from the magnetic sheet 215 The vertical synchronization signal of the video signal is synchronized with the vertical synchronization signal output from the reference synchronization signal generation circuit 250. In the case of a field picture, the fields match every field, but if the reproduced picture is a frame picture, the resynchronization signal generation circuits 248, 2
50, the fields may not match. When the signal recorded on the magnetic sheet 215 is a frame, when switching between the various synchronous signals generated by the synchronous signal generation circuit 248 and the various synchronous signals generated by the reference synchronous signal generation circuit 250, the above-mentioned If the fields do not match, a skew will occur when switching the synchronization signal.

Therefore, first, the fields are matched (S600), that is, the video signals recorded as two fields on two tracks of the magnetic sheet 215 are played back alternately by the switch 218 to perform frame playback. Comparison circuit 2 indicates that they do not match.
56, this alternate playback is stopped for a period of 1v. By stopping the switching of the switch 218 for a period of 1, the mutual fields are made to match. Thereafter, the color difference discrimination circuit 150 discriminates each of the two fields, and this is stored in the latch circuit 320 (S601). Here, the selector 254 selects the synchronization signal generation circuit 248, turns off the reset switch 252, and freezes the reproduced video signal.

When the signal recorded on the magnetic sheet 215 is a field picture, the reproduced video signal is always one field, but the reference synchronization signal generation circuit 250 generates a frame picture synchronization signal when the reset switch 252 is off. occurs, so the fields will match every field,
If the synchronization signals of the synchronization signal generation circuits 248 and 250 are switched when they do not match, a skew will occur. Therefore, first, the fields are matched (S600). That is, when the comparison circuit 256 detects that the fields do not match as described above, the image memory circuits 228, 2
The fields can be aligned by controlling 30 and waiting for a period of 1.

Thereafter, the color difference discrimination circuit 150 performs discrimination in the next 12 period, and the discrimination results are stored in the launch circuit 320.

At this time, the fields do not match (S6
01). Here, the selector 254 is the synchronizing signal generating circuit 2
48 is selected, and the reproduced video signal is frozen in the next 12 period. Note that at this time, the fields will match.

Now, in FIG. 1A, the reproduced luminance signal is transmitted to the A/D converter 100, the clamp circuit 102, and the selectors 110 and 114.
And via the 5-p-s conversion circuit 118, one frame or one field is written into the image memo I 7116 from the P port as Yo+Y++Yz+Y'z+Yt+Ys+'- . This signal is simultaneously read out from the S port as Yo+Yo+Yt+Yz+Yx+Y4+・-, and is then read out from the S port as follows:
28 and is output to an output terminal 236 via a switch 232 and an encoder 234. On the other hand, selector 12
The output of No. 2 is also applied to the selector 110, which is the image data one rask before the input reproduced luminance signal, and if there is a dropout in the reproduced video signal, the output of the selector 110 is applied during that period. 110 selects the image data one raster before this and performs dropout compensation.

In FIG. 1B, the reproduction line sequential color difference signal is transmitted through the A/D converter 100, the clamp circuit 102, and the selectors 110 and 158.
and R to the image memory 162 via the latch circuit 160.
Yo, BYl, RYz, BYs, BY4. BYs, RY
&+BY? Assume that the RY components are input in order such as + and -. This image data for one frame or one field is taken into the image memories 162a and 162b from the P port alternately for each rask. 2 rusks at the same time from S boat, RYo, RYo, RYoIRYolRYz, RYz, B
Y4. BY41-BYI, BYI, BYl, BYl, B
Y3. BY3. It is read out as BYS, BYS, -... Then, this image data is selected by the selector 17.
4.176.178,180, D/A converter 18
2.184 are distributed to D/A converters 182 and 184 so as to always output RY and BY components, respectively. On the other hand, the selector 166 selects BY6. BYI, RYO
, BYI, BY2. BY3. BYl、BY、、RY、、
BY7. -・, and this output is selector 1
10 is also applied. In other words, this is the image data two rasters earlier than the input reproduction line sequential color difference signal, and if there is a dropout in the reproduced video signal, the selector 110 selects the image data two rasters earlier during that period. ,
Dropout compensation is performed (S602).

Next, in FIG. 1A, the reproduced luminance signal is continuously input to the A/D converter 100, and the selector 110 is inputted to the adder 1.
08 is selected and one frame or one field of this is frozen in the image memory 116. At the same time, the same fields as the reproduced luminance signal are output from the S port as Yo, Y+, and Yz.

Y31Y4. YSl...--read, this data is multiplied by a coefficient K (0<K<1) using a multiplier 1°4, and
An adder 108 adds the reproduced luminance signal multiplied by a coefficient (1-K) by a multiplier 106 . At this time, if there is a dropout in the reproduced luminance signal, the selector 110 selects the output side of the selector 122 during that period to perform dropout compensation.

In FIG. 1B, the A/D converter 100 is continuously supplied with reproduction line sequential color difference signals, and the selector 110 is input to the adder 1.
08 is selected and one frame or one field of this is frozen in the image memory 162. At this time, the same fields as the reproduced line sequential color difference signal fields from the S boat are simultaneously transmitted 2 rasks at a time: RYo, RYo, RYz, RYz, RYn, BYl.
,RYRY,,-・BY++BY+,BYz+BYi
, BYs, BYs, BY7. BY7.・Read it out like this. The selector 166 selects this and selects RYo,
BY+, RYZ, BY31RY4. BYs,
Output as RY BY,...-. This is multiplied by the coefficient K (0<K<1) in the multiplier 104, and the reproduction line sequential color difference signal is multiplied by the coefficient (1-K
) are multiplied by 1 and 2 and then added by an adder 108. If there is a dropout in the reproduction line sequential color difference signal, the selector 110 selects the output side of the selector 166 during that period,
Perform dropout compensation.

By performing the above operation for a period of several volts, the magnetic sheet 21
The image data of the same still image reproduced from 5 is added several times. Random noise can be reduced by addition (S603). If the reproduced video signal is a frame, the above operation is performed frame by frame, and if the reproduced video signal is a field, the above operation is performed when the field of the reproduced video signal matches the field of the synchronization signal generation circuit 250. If not, inter-field interpolation to be described later is performed and the image memory 116, 162 is read.

FIG. 6B is a time chart when the reproduced video signal is a frame, and shows a time chart when no noise reduction is performed, and when the reproduced video signal is a frame.
This shows the case where noise reduction is performed over frames.

FIG. 6C is a time chart when the reproduced video signal is a field, and shows a case where noise reduction is not performed and a case where noise reduction is performed over four fields.

Next, the data stored in the image memories 228 and 230 is read out (S604). In the case of a luminance signal, stored data is read from the S port of the image memory 116 in accordance with the address signal from the S address generation circuit 138 in FIG. 1A. This successive signal is applied to the D/A converter 128 via selectors 122 and 126. Image memory 116
If the stored image is a frame image, it is sufficient to alternately read one field at a time. Further, in the case of a field image, a signal read out as is is used for one field, and a signal subjected to inter-field interpolation is used for the other field.

That is, when using an image stored in an odd field of the image memory 116, when outputting it as an odd field signal, Yo+Y+
+Yt+Yi+Y*+Ys+Y6+ '-, the data is read out in the normal rask order and output via the selectors 122 and 126 and the D/A converter 128.

When outputting as an even field signal, the S port to Y of the image memory 116 is output. ,Yb,'Yt,Ys,
Yt, YS+Y6+ '----, and at the same time read YI+Yl+Yl+Y4+Y2. from the P boat.
Read out as Y6+-... The S port output and the P port output are averaged by an adder 124, and a selector 126 selects the output of the adder 124. As a result, the output of the D/A converter 128 is Y in the odd field.
,,Y,,Y,,Y:l+Y4+YStY&+ ---
In the even field, (Y0+Y+)/2. (
Y++Yz)/2. (Yt+Y:+)/2. ('h
+Yt)/2. (Y4+Y5)/2, . . . are interpolated values between fields.

In addition, when using a signal stored in an even field of the image memory 116 and outputting it as an even field signal, Yo, Y
i, Yz, Yi, Yi, Ys, Y...- When reading out in the normal rask order and outputting it as an odd field signal, Y is read from the S boat of the image memory 116.
O+Yl+Y1. At the same time as reading Y3+Y*+YS+Y6+ '-, YO+YO+ is read from P boat.
The data of the previous rask is read out in normal rask order, such as Yl+YIY3+Yl+YS+. The S boat output and the P boat output are averaged by an adder 124,
A selector 126 selects the output of the adder 124.

As a result, the output of the D/A converter 128 is (yo+yo)/2. (Yo+Y+)/2.
(Y++Yz)/2. (Yt+Ys)/2+ (Y:
++Y*)/2. (Y4+Ys)/2+-... is the interpolated value between fields, and in even fields, it is Yo.

Y++Yz+Ya+Yn+Ys+Y6+'-.

The color difference signal is as follows. Image memory circuit 2
Since the input signal to 30 is a line-sequential color difference signal, it is necessary to perform line-to-line time conversion when outputting the stored data. That is, in FIG. 1B, the line sequential color difference signals input to the image memory 162 are RYo, BY+, B for each raster.
Y2. BY3. BY4. BYS, BY6. BY?
.

-, when starting from the R-Y component, the image memory 162a contains the R-Y components RYO, RYZ, BY4 .
BY6°-. is stored, and B- is stored in the image memory 162b.
Y components BY+, BY+, BYs, BYt, - are stored, and the latch circuit 320 of the color difference discrimination circuit 150 is in a state indicating that the first rask is the RY component. The data stored in the image memory 162 is stored in two rusks from the S boat at the same time: RYo, RYo, RYz, RYz, BY4. RYE
, RYE, RYil-BY+, BY, BYs, BY
It is read out as follows: s, BYs, BYs, BYt, BYw, -. At the same time from P boat, R-Y, B
-Y raster alternately BY++RYz+BY++RY4
+BY3. It is read as RYE, BYS, '-.

The selectors 174 and 176 both switch the human signal every 1 rask, and the selectors 178 and 180 switch the D/A converter 18.
2 and 184 are switched so that they always output R-Y and B-Y signals, respectively. As a result, the D/A converter 182
is RYo, (RY6+RYz)/2. RYil (R
YilRY4)/2. BY4. (RY4+RY&)/
2. -, and the D/A converter 184 outputs (BYI+BY
+)/2. BY+, (BYl+BY3)/2. BY!
.

(By:++Bys)/2. BYs, -... are output to form a line-to-line time-varying color difference signal.

Further, when the line sequential color difference signal input to the image memory circuit 230 starts from the B-Y component, the image memory 162
a has BY components BYo, BYz, BYa, BYi, -
--- is stored, the image memory 162b stores RY components BY+, RYi, RYs, RYt, --., and the latch circuit 320 of the color difference discrimination circuit 150 stores the first rask as the BY component. It is in a state that indicates that. The data stored in the image memory 162 is stored in two rusks simultaneously from the S port: BYo, BYo, BYg, BYz, BYn, BY4 . B
Yb, BYthl'--BYt, BYt, BY3. R
Yi, RYs, RYs, RYt, RYy, etc. are read out, and at the same time, RY, B-
Y raster alternately, BYt, BYz, RYt, BY4
．． They are read out as RYIBY&, RYS+, --, and so on. By switching selectors 174 to 180, D/A
Converter 182 is (RYt+RY+)/2. BYt, (R
Y++RYs)/2. RYs, (RYilRYS)/
2. The D/A converter 184 outputs BY
. + (BY o+BYz) /21 BY! , (B
Y t+ BY a) / 2+ BYt+ (BY
Outputs 4+BY&)/2, -.

If the image stored in the image memory 162 is a frame image, the above operation may be performed for each field. Further, in the case of a field image, the above operation is performed twice in succession in one field (S604).

Next, move the playback head 216, 217 (5605),
The device enters a standby state and repeats the above operations.

In the above reproduction mode, the latch circuit 132 indicating the blanking area is operated, and this satisfies the entire image area of the reproduced video signal.

In the playback mode, the playback image is reduced and stored in the image memory 11.
6,162 will be explained.

The flowchart is shown in FIG. 7A. The time chart at this time is the same as that shown in FIG. 6C when the reproduced video signal is a field and noise reduction is not performed.

First, the image memories 116 and 162 are cleared to predetermined values (S700). Next, field alignment is performed between the reproduced video signal of the field image and the reference synchronization signal generation circuit 250 (5701), and discrimination is performed by the color difference discrimination circuit 150 in a period of 1.5 cm (S702). The details of this part are the same as the previous explanation, so the explanation will be omitted.
54 selects the synchronization signal generation circuit 248, reduces the image of the reproduced video signal in the next 1V period, and reduces the image memory 116.54.
162 (S703). That is, in FIG. 1B, the reproduction line sequential color difference signals are RYo, BY+ for each rask.
, RYt, BYs, BYt.

RY as BYs, RYi, BYt,'-・
Let's start with the component 1. For example, convert this to 115 X11
When reducing the field image to 5 field images and storing it in the image memory 162, in order to multiply the horizontal direction by 115, the clock for generating the horizontal address signal of the P address generation circuit 136 is divided by 175, and the vertical direction is multiplied by 175. For this purpose, the frequency of the horizontal synchronization signal for generating the vertical address signal of the P address generation circuit 136 is divided by 175. That is, sampling is performed alternately from the RY component at a rate of 1 rask for every 5 rasks from the reproduction line sequential color difference signal, and other data is thinned out. for example,
RYo, BY+, RYz, BYs, BY4. BYs, R
Yi, BYt, BYt, BYq, BYt. +BYll+
'- from RY,,BY,.

R.Y. ,-... or RY,,B
Y,,RY,. .

BYz, '- sampling is performed. The thinned rasters are always captured in the lowest raster region of the memory space of image memory 162 for dropout compensation. In other words, in the case of R-Y, the image memory 162a, B-
In the case of Y, it is taken into the lowest raster area of the image memory 16'2b. At the same time as this writing, the lowest raster area of the memory space of the image memory 162 is always read out two rasters from the S boat, and is alternately selected by the selector 166 and used for dropout compensation of the reproduced video signal as described above. .

As described above, a 115×115 reduced image can be stored as a field image in the image memory 162 from the reproduced line-sequential color difference signal of the field image.

Furthermore, when reducing the frame image to a 115 x 15 frame image and storing it in the image memory 162, multiplying the frame image by 175 in the horizontal direction is the same as described above. To multiply the frequency by 175 in the vertical direction, the horizontal synchronizing signal for vertical address signal generation of the P address generation circuit 136 is divided by 275 or a similar frequency division ratio. In other words, the reproduction line sequential color difference signal is sampled at a rate of 2 rasks for every 5 rasks, and the RY components are sampled at a rate of 2 rasks at a time.

For example, RYo+RYz, BYS+BYt+RY+. I
Sample RY+z+・-, or RYo, RYz
, BY, 1BYq, BYzo, BYzz, '-' are sampled. Then, the fields are alternately switched one rask at a time. In the former case, store RYo, BYs, BYzo, - in the odd field of image memo I7162,
Even fields include RYz, BYy, BYz z
,... are stored. As before, the thinned out raster is stored in the lowest raster area of the memory space of the image memory 162, read out from the S boat, and used for dropout compensation of the reproduced video signal.

As described above, a 115 x 15 reduced image can be stored in the image memory 162 as a frame image from the reproduced line-sequential color difference signal of the field image.

By changing the initial value of the P address generation circuit 136, the reduced image can be placed and stored at any position in the memory space of the image memory 162, but the image memory 162 is Since it is a color difference memory, it must be read from the RY component raster of the image memory 162.

Similarly, regarding the reproduced luminance signal, the P address generation circuit 1
1 clock for generating 36 horizontal address signals
By dividing the frequency by 75, reduction is performed in the horizontal direction, and in the vertical direction, the raster of the luminance signal corresponding to the raster of the reproduced line sequential color difference signal imported into the image memory 162 can be imported into the image memory 116. Compensation can be done in the same way. Here, a new value is reset in the latch circuit 134 so as to store an area smaller than the image area of the reproduced video signal determined by the latch circuit 132, and the resulting blanking signal is used to store the reduced image. Store in image memory.

The reproduction line sequential color difference signal is BYo, RYE, B for each raster.
Yffi+ RYs+ BY4. RYS, BYE,
Assuming that the B-Y components are input sequentially like RYt, BYs, -, the blanking area is set by shifting one rask, and BYz, BYz, RYa, BYn, RYs
, BY6. The above operation is performed assuming that the RYt, BYs, - and RY components are input sequentially.

Next, the selector 254 selects the reference synchronization signal generation circuit 250 and sequentially outputs the image memories 116 and 162 (S7
04). At this time, the blanking signal from the latch circuit 132 operates. Then, by forwarding the reproduction track of the magnetic sheet 215 (S705) and similarly storing the reduced image, it is possible to obtain 25 5×5 field images or frame images as shown in FIG. 7B.

Note that the same process can be performed at other reduction ratios.

〔Effect of the invention〕

As can be easily understood from the above explanation, according to the present invention, by making the blanking area freely changeable when importing or reading an image into the image memory, it is possible to flexibly respond to each situation. Become.

[Brief Description of the Drawings] Figure 1A is a block diagram of the configuration of an image memory circuit for luminance signals, Figure 1B is a block diagram of the configuration of an image memory circuit for line-sequential color difference signals, and Figure 2 is a block diagram of an image memory circuit for line-sequential color difference signals. System configuration block diagram, FIG. 3A is a detailed configuration block diagram of the clamp circuit 102 and color difference discrimination circuit 150 in FIGS. 1A and 1B, FIG. 3B is a time chart of the color difference discrimination circuit 150, and FIG. 4A is a recording Flowchart of mode, Figure 4B is a time chart of recording mode, Figures 5A, 5B and 5C are explanatory diagrams of picture-in-picture display, Figure 6A is a flowchart of playback mode, Figure 6B
7 and 6C are playback mode time charts.
FIG. A is a flowchart of multi-screen freezing, FIG. 7B is an explanatory diagram of a 5×5 multi-screen, and FIG. 8 is an example of a conventional screen display. 116-Image memory 118-5-P-5 conversion circuit 13
0-Blanking signal generation circuit 132, 134...-
Latch circuit 136--P address generation circuit 138
-・S address generation circuit 150-・-color difference discrimination circuit
162 (162a, 162b) --- Image memory 2
10-External input terminal 215-Magnetic sheet for reproduction 22
8,230--Image memory circuit 236--Output terminal 243--Magnetic sheet for recording 246--Synchronization separation circuit 248--Synchronization signal generation circuit 250--m-Reference synchronization signal generation circuit 252--Reset ·switch

Claims (1)

[Claims] An image storage device characterized by comprising means for changing a blanking area when loading or reading an image into an image memory as necessary.