JPH01274118A - Top stagger type thin-film transistor array of amorphous silicon - Google Patents

Abstract

PURPOSE:To prevent the generation of the disconnection of gate wirings by forming an amorphous silicon layer or amorphous silicon layer and silicon nitride layer broader than the gate wirings to the entire part of the lower layer of the gate wirings. CONSTITUTION:There are the gate wirings 4 which connect the gate electrodes 1 to each other and the source wirings 5 which connect source electrodes 2 to each other and intersect with the gate wirings 4 as the wirings. The amorphous silicon layer 6 and the silicon nitride layer 7 are formed to TFT (thin-film transistor) parts and are formed to the entire part of the lower layer of the gate wirings 4 so as to be broader than the gate wirings 4. The gate wirings are thereby prevented from crossing the amorphous silicon layer 6 or the amorphous silicon layer 6 and the silicon nitride layer 7 and, therefore, the disconnection of the gate wirings 4 is prevented and the yield is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to top stagger type (hereinafter referred to as Tffi) amorphous silicon (hereinafter referred to as a-St) used in active matrix type liquid crystal displays, etc. ) relates to thin film transistor (hereinafter referred to as TFT) arrays.

[Prior Art] In recent years, research and development of a-3i TFT arrays has been carried out in various places with the aim of applying them to active matrix liquid crystal displays and the like.

3 to 5 show an example of the case where a-Si TFT is used in the active matrix type liquid crystal display.

In the figure, 1 is a gate electrode, 2 and 3 are source and drain electrodes each formed of an n-type silicon layer containing an appropriate amount of n-type impurities, 4 is a gate wiring connecting a plurality of the gate electrodes, and 5 is a gate electrode. A source wiring connecting the plurality of source electrodes and crossing the gate wiring, 6 an amorphous silicon layer, 7 a silicon nitride layer formed on the amorphous silicon layer 6, 8 a drain electrode 3; The pixel electrodes are connected, 9 is a gate insulating layer, and 10 is a light-transmitting insulating base.

As shown in FIG. 4, a gate electrode 1 and a source electrode 2
and a drain electrode 3 is formed sandwiching an amorphous silicon layer 6, a gate insulating layer 9, etc.
The one formed on the side is a top stagger (T) type a-3i
It is called TFT.

Normally, in a T-type a-3i TFT array, the gate wiring and source wiring are insulated by a gate insulating layer, but if only the gate insulating layer is used, insulation defects frequently occur between the gate wiring and the source wiring. In order to reduce insulation defects, an amorphous silicon layer 6 and a silicon nitride layer 7 are formed only at the intersection of the gate wiring 4 (upper layer side) and the source wiring 5 (lower layer side).

[Problems to be Solved] As shown in FIG. 5, conventionally, the amorphous silicon layer 6 and the silicon nitride layer 7 were formed only at the intersection of the gate wiring 4 and the source wiring 5. Crystalline silicon layer 6
Due to the difference in level at the end of the silicon nitride layer 7, the gate wiring 4 was disconnected, which significantly reduced the yield.

The present invention has been made to address the above-mentioned conventional problems, and an object of the present invention is to provide a T-type a-Si TFT array that does not cause disconnection of gate wiring.

[Means to solve the problem].

The present invention provides a top staggered amorphous silicon thin film transistor formed in an array, a gate wiring connecting the gate electrodes of the top staggered amorphous silicon thin film transistor, and a gate wiring connecting the source electrodes. In a top staggered amorphous silicon thin film transistor array having intersecting source wirings, an amorphous silicon layer or an amorphous silicon layer and a silicon nitride layer are formed on the entire lower layer of the gate wiring to be wider than the gate wiring. By doing so, the above problem is solved.

[Example] An example of the present invention will be described below with reference to the drawings.

In FIGS. 1 and 2, 1 is a gate electrode, 2 and 3 are source and drain electrodes formed of an n-type silicon layer, 4 is a gate wiring connecting the plurality of gate electrodes 4, and 5 is a gate electrode. This is a source wiring that connects the plurality of source electrodes and intersects with the gate wiring 4. Reference numerals 6 and 7 denote an amorphous silicon layer and a silicon nitride layer, respectively, which are formed in the TFT section, and are also formed in the entire lower layer of the gate wiring 4 to be wider than the gate wiring 4. 8 is a pixel electrode connected to the drain electrode 3, 9 is a gate insulating layer, and 1'0 is an insulating substrate.

In this example, an amorphous silicon layer 6 and a silicon nitride layer 7 are used.
is formed to be wider than the gate wiring 4 in the entire lower layer of the gate wiring 4, as shown in FIG. can be significantly reduced.

Note that only the amorphous silicon layer may be formed to be wider than the gate wiring in the entire lower layer of the gate wiring.

[Effects of the Invention] According to the present invention, since the gate wiring does not cross the step between the amorphous silicon layer or the amorphous silicon layer and the silicon nitride layer, disconnections in the gate wiring can be significantly reduced. and improve yield.

[Brief explanation of the drawing]

Figure 1 is a plan view showing one embodiment of the present invention, Figure 2 is a plan view showing one embodiment of the present invention;
The figure is a sectional view taken along the line ■-■ in Fig. 1, Fig. 3 is a plan view showing the conventional example, Fig. 4 is a sectional view taken along the IV-IV line in Fig. 3, and Fig. 5 is a sectional view taken along the line IV-IV in Fig. 3. 2) It is a sectional view taken along the line -V. 1... Gate electrode 2... Source electrode 3... Drain electrode 4... Gate wiring 5... Source wiring 6... Amorphous silicon layer 7... Silicon nitride layer FIG. Figure 2 Figure 3 Figure 4 Figure 5 J b '1025

Claims (1)

[Claims] A top staggered amorphous silicon thin film transistor formed in an array, a gate wiring connecting the gate electrodes of the top staggered amorphous silicon thin film transistor, and a source connecting the source electrodes and crossing the gate wiring. In a top staggered amorphous silicon thin film transistor array having a wiring, an amorphous silicon layer or an amorphous silicon layer and a silicon nitride layer are formed in the entire lower layer of the gate wiring to be wider than the gate wiring. Features a top staggered amorphous silicon thin film transistor array.