JPH01272236A - Signal detection system - Google Patents

Abstract

PURPOSE:To detect even a signal other than a preamble signal by providing a signal detecting circuit which continuously detects sign transition points of a digital signal demodulated at each time of power-on in a reception circuit and outputs a detection signal in case of the number of sign transition points larger than a prescribed value. CONSTITUTION:A receiver periodically turns on the power source of its reception circuit 2 only for a certain time T1 to wait for the reception input. When the reception input comes, the reception circuit 2 demodulates the reception input at each time of turning on the power source and outputs a digital signal. Since a signal detecting circuit 4 detects sign transition points of a series of digital signals for a time T2 longer than the time T1, the digital signal outputted by turning on the power source once does not suffice. Therefore, the signal detecting circuit 4 uses a series of digital signals, which are outputted by turning on the power source plural times, to detect sign transition points for the time T2 and discriminates whether the signal exists or not in accordance with the number of sign transition points. Thus, even a signal other than the preamble signal is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal detection method for a selective call receiver.

(Prior Art) When performing selective call communication between a base station and a plurality of receivers, so-called POC5AG ((British
) Post Office Code 5tandar
A code format called "dissationAdvisoryGroup" is used.

This code format is the code "1" as shown in Figure 2.

A preamble (7) consisting of repeating '0' plus multiple frames (A), (T)...
In each frame, a calling number unique to each receiver used to call each receiver is placed in a predetermined position.For example, the calling number of a receiver belonging to /164 is included in the frame in FIG. It is inserted at position "4". If there are no incoming radio waves, the receiver periodically turns on the power for a certain period of time, and detects the presence or absence of incoming radio waves within the on time. In the example shown in Figure 2 (B), part (7) is the power-on time (625 mS), and part (A) is the power-off time (1
000 mS), the receiver determines the presence or absence of the preamble shown in (7) of FIG. 2(A) within this power-on time. When the radio wave of the signal shown in Figure 2 (A) arrives and the receiver detects the preamble in the part (1) of Figure 2 (B), it is determined that there is a reception input and the receiver is currently on. The power supply is kept on for a certain period of time, and the synchronization code SC of the following frame (a) is searched. When the receiver detects the synchronization code SC, it temporarily turns off the power as shown in FIG. Detect your own machine's unique calling number. The receiver performs a series of operations such as displaying a call by making the speaker ring, etc., and receiving message data sent following the call number. If the receiver does not detect the calling number unique to the receiver, it turns on the power at the synchronization code SC of each subsequent frame and the position to which the receiver belongs, and continues searching for the calling number unique to the receiver.

(Problem to be Solved by the Invention) However, in the signal detection method for detecting the preamble described above, the preamble may be detected due to some reason, such as when the receiver approaches a place where the radio waves are weak at the moment the preamble is sent. When it was not possible to receive
Since the receiver repeatedly searches for a preamble until the next preamble is sent, the problem is that even if the receiver's own calling number is sent, it cannot detect the calling number. was there. This tendency becomes stronger as the number of selective calling subscribers increases because the probability of transmitting a preamble also decreases.

Further, since the time the receiver is powered on is short, malfunctions due to noise often occur when detecting signals.

The present invention eliminates the above-mentioned problems, allows signal detection for signals other than the preamble, and therefore allows selective calling to be detected even if the preamble is missed, and provides a signal detection method that is resistant to noise. The purpose is to

(Means for Solving the Problems) The present invention provides a signal detection method for a selective call receiver in which the power of the receiving circuit is periodically turned on for a time T while waiting for a reception input, and the receiving circuit demodulates the signal every time the power is turned on. The present invention is characterized by comprising a signal detection circuit that continuously detects code change points in a digital signal that is transmitted, and outputs a detection signal when the number of code change points in a time longer than the time T is equal to or greater than a predetermined value. This is a signal detection method.

(Operation) The receiver saves the battery while periodically turning on the power of the receiving circuit for a certain period of time and waits for a receiving input. When there is a reception input, the reception circuit demodulates the reception input every time the power is turned on and outputs a digital signal. However, since the signal detection circuit detects the code change point of a series of digital signals at time T2, which is longer than time T1, the digital signal output when the power is turned on once is not enough. Therefore, the signal detection circuit detects the sign change point at the time T2 using a series of digital signals output when the power is turned on a plurality of times, thereby improving the accuracy of detection. Further, since the presence or absence of a signal is determined based on the number of code change points of a digital signal, signal detection can be performed for signals other than preambles as well.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention,
J is a receiving antenna, 2 is a receiving circuit, 3 is a logic processing circuit,
4 is a signal detection circuit, and 5 is a power supply control circuit.

In FIG. 1, the receiving antenna 1 is a base station (not shown)
It receives radio waves emitted from. Receiving circuit 2
The demodulator demodulates the radio waves received by the receiving antenna l and outputs a digital signal. The digital signal is
As shown in Fig. 2 (N), it is composed of a brain amble and a plurality of frames, and each frame is divided into a plurality of groups corresponding to a synchronous code SC and each receiver. A selective call signal containing an individual number code assigned to each machine is inserted, and each receiver can call its own machine by comparing it with the individual number code stored in its own machine in advance. The logic processing circuit 3 detects, for example, the synchronous code SC shown in FIG. It detects the presence or absence of a digital signal output from the
Or, when the number of points where I'0'' changes (hereinafter referred to as changing points) is 27 bits or more, it is determined that a signal is present, and a detection signal is output.The pit rate of the digital signal is set to 51.
2 b/s, it will take 125 mS to check the change point of the continuous 64 bits. By the way, as will be explained later, during reception standby, the receiver waits for the arrival of radio waves while turning on the power to the receiver circuit 2 for a short period of time (for example, 62.5 mS). When it arrived,
The signal detection circuit 4 detects the signal during the power-on time of the receiving circuit 2 (6
It is not possible to check the change points of all the continuous 64-bit digital signals within 25 ms). Therefore, the signal detection circuit 4 checks the points of change for a total of 64 bits of the signal over a plurality of power-on periods. For example, if the signal detection circuit 4 checks the change points of a total of 42 bits of the digital signal just before turning off the power supply, and the number of change points is 13 bits, then the next time the power supply is turned on, The state will be maintained until the power is turned on, and the remaining memory will be
The changing point of a 2-bit (64-42=22 bits) digital signal is checked. If the result of the check is that the number of change points is 14 bits or more, the total with the number of 13 bits of the previous change point is 27 bits or more, so it is determined that there is a digital signal, and a detection signal is output. If it is below, the total will be 26 pits or less and no detection signal will be output.

The power supply control circuit 5 turns on the power of the receiving circuit 2 based on the detection signals from the signal detection circuit 4 and the logic processing circuit 3.
This is to turn it off.

Next, the operation of this embodiment will be explained with reference to the operation diagram of the power supply control circuit shown in FIG.

First, when radio waves are not being emitted from the base station,
Since no digital signal is output from the receiving circuit 2 shown in the figure, and therefore no detection signal is output from the signal detection circuit 4,
The power supply control circuit 5 is connected to the receiving circuit 2 as shown in FIG. 3 (4).
Turn on the power for a time of TI (e.g. 52.5m5),
Repeat the off period for T2 (for example, 1000 m5) and wait for the arrival of radio waves while saving the battery.

While waiting for reception, radio waves are emitted from the base station as shown in Figure 3 (C).
Suppose that a signal as shown in is sent, but the reception condition is poor in the part shown by the dotted line and cannot be received by the receiving antenna 1, but it can be received from the part shown by the solid line. The receiving circuit 2 receives the time TI(6) in the part (7) shown in FIG.
It is turned on for only 25 mS) to demodulate and output a digital signal. The signal detection circuit 4 detects the output signal (for example, 32
Check the number of changing points for a given value (for example, if the number of changing points is 27 for a digital signal of 64 bits).
), it is determined that there is no signal and no detection signal is output. As a result, the power supply control circuit 5 turns off the power supply of the receiving circuit 2 after Tl. At this time, the signal detection circuit 4
holds the power on the verge of being turned off. As shown in FIG. 3(B), after 1000 mS, the power supply control circuit 5 turns on the power to the receiving circuit 2 again in the part (A), and the receiving circuit 2 outputs a digital signal. Signal detection circuit 4
is the 32 bits (64 bits -
32 bits), the held state is continued and the number of changing points is checked, and when it reaches 27 or more, it is determined that there is a signal and a detection signal is output. Power control circuit 5
continues to turn on the receiving circuit 2 based on the detection signal, and the logic processing circuit 3 starts searching for the synchronous code SC shown in FIG. 3(C).

When the logic processing circuit 3 searches for the synchronous code SC, the power supply control circuit 5 switches the power supply of the receiving circuit 2 to (B).
If the group to which you belong is 4, for example, the signal is turned on at position 4 of the signal shown in (C). The logic processing circuit 3 checks the selective call signal outputted from the receiving circuit 2, and if it is called, it thereafter takes in data.

If it is not called, the power supply control circuit 5 thereafter repeatedly turns on the power of the receiving circuit 2 at the position of the synchronous code SC shown in FIG. 3(C) and the position of the group to which it belongs, and Logic processing circuit 3 checks the selective call signal.

FIG. 4 is a schematic diagram showing an embodiment of the signal detection circuit 4 shown in FIG. In FIG. 4, 1 is an input terminal into which the digital signal from the receiving circuit 2 shown in FIG. 1 is input;
12 is a code change point detection circuit that outputs a conversion pulse at the code change point of the digital signal; 13 is a clock regeneration circuit that regenerates a clock signal from the digital signal; and 14 is a phase-locked loop (PLL) circuit included in the clock regeneration circuit 3. J5 is a time slot generation circuit that outputs a pulse having a pulse width of ±τ (τ≦T, where 1/'r=bit rate) before and after the rising edge of the clock signal; A determination circuit 17 that determines whether or not the conversion pulse exists during a pulse output period from the time slot generation circuit J5 and outputs only the conversion pulse that exists during the period; 17 generates an inverted pulse of the clock signal; 18 is a determination circuit 16
a holding circuit for holding the output signal for a predetermined period; 19 is an M+1 stage shift register operated by the inverted pulse; 2;
0 is the data of the first stage of the shift register 19 and the M+1th stage data.
Logic circuit that compares the data in the row, 2 is logic circuit 2
a digital reversible counter capable of counting up to at least M, which performs addition or subtraction based on the comparison result of 0; 2;
2 is a digital comparator that compares the count value of digital reversible counter 2 with a preset value and outputs a detection signal indicating the presence or absence of a digital signal; 23 is an output terminal; 24
2 is a control input terminal to which a control signal from the power supply control circuit 5 shown in FIG.

Next, the operation of the signal detection circuit shown in FIG. 4 will be explained with reference to FIG. 5, which shows waveforms of various parts in FIG. 4.

When the digital signal of the NRZ code shown in FIG. 5 (7) is input to the input terminal 11, the code turning point detection circuit J2 detects the
A pulse shown in FIG. 5(a) is output for each code conversion point of the RZ code. On the other hand, the clock regeneration circuit J3 regenerates a clock signal of the same frequency synchronized with the clock signal on the transmitting side from the digital signal, and generates a clock signal from the time slot generation circuit 15.
and output to the inversion/P pulse generation circuit J7. FIG. 5(a) shows a clock signal reproduced by the clock reproduction circuit 13. Although various methods have been announced for the clock regeneration circuit J3, the input signal is differentiated to extract the transmitting side clock component, and its frequency and the master clock frequency nfc of the master clock oscillator 14 are divided by an n frequency divider. The frequency fc obtained by dividing by n is input to a PLL circuit to detect the phase difference, and the division ratio of the n frequency divider is controlled by the lead/lag of the phase, and the Tagata frequency fc of the n frequency divider is Generally, the phase is adjusted to synchronize with the transmitter clock frequency and output as a clock signal. Based on the clock signal, the time slot generation circuit J5 calculates the timing τ before and after the rising edge of the clock signal, as shown in FIG.
The judgment circuit generates a pulse with a time width of .

Send to. Based on the clock signal, the inversion pulse generation circuit J7 generates an inversion pulse at each falling point of the clock signal as shown in FIG.
The data is sent to the holding circuit 18 via.

The determination circuit J6 determines whether or not the switching pulse shown in FIG. is determined, and only the conversion/mother pulses in the period are output as shown in FIG. 5(3). Holding circuit 1
8 is composed of, for example, a set-reset clip-flop circuit, and the output of the determination circuit No. 5 is applied to the set terminal, and the inverted A' pulse from the inverted pulse generation circuit 17 is applied to the reset terminal via the gate circuit 25. . Therefore, the output of the holding circuit No. 8 is determined by the judgment circuit J6 as shown in FIG.
The waveform rises at the output pulse of and is held until the inverted pulse rises. In the shift register 19, when a pulse is being outputted from the holding circuit 18 for each inverted Noculus, data of "1" is written, and when it is not being outputted, data of ``0'' is sequentially written. The written data is shifted to the subsequent stage each time an inversion pulse is input, and the data written in the first stage is shifted to the M+1th stage by the subsequent M inversion pulses. The logic circuit 20 inputs the data of the first stage and the M+1st stage of the shift register 19, and performs the logical operation shown in FIG. That is, if the data in the first stage of the shift register 19 is A, and the data in the M+1st stage is B, then A=''
1", B="01, instructs the digital reversible counter 2) to operate in addition mode 0, A=MO", B-1
”, it instructs it to operate in subtraction mode, and in other cases, it instructs it to stop counting.The digital reversible counter 21 receives an inversion/cross input based on the instructions from the counting mode 9 from the logic circuit 20. Add or subtract each time.

Therefore, the count value of the digital reversible counter 2 always matches the number of data '11' among the data written in the second stage to the M+1th stage of the shift register 19.

The operation of each circuit of the signal detection circuit has been described above for the case where an inverted pulse is output from the gate circuit 25. However, when the inverted pulse is no longer output, the holding circuit J8, shift register 19, logic circuit 20, digital reversible Each circuit of the counting circuit 2 stops its operation and maintains the state on the verge of stopping.

Here, the r-) circuit 25 opens the r-t t seconds after the receiving circuit 2 shown in FIG. Start. Figure 8 shows this, (
A) shows the power-on timing of the receiving circuit 2, (B) shows the waveform of the control signal sent from the power supply control circuit 5 to the signal detection circuit 4, and (C) shows the r-to circuit that operates based on the control signal. Inverted No.J output from 25? This is the waveform of Lus.

The reason why the start of operation of the signal detection circuit 4 is delayed by t seconds from the start of operation of the reception circuit 2 as described above is as follows.

(a) Since the local oscillation circuit in the receiving circuit 2 is composed of a crystal oscillator, it takes time for the oscillation output to rise after the power is turned on.

(b) The receiving circuit 2 includes a pass band F wave device and a low pass band F wave device.
Since it includes a waver, it takes time for the signal to be output.

Therefore, even when the power is turned on, the receiving circuit 2 does not reach a normal state for a certain period of time and outputs a meaningless signal. Therefore, if the signal detection circuit 4 immediately uses the output signal, it will produce an erroneous detection result. Therefore, the time t required for the receiving circuit 2 to reach the normal state after the power is turned on
The operation of the holding circuit 18 of the signal detection circuit 4, the shift register J9, and other circuits is started after a delay of 20 seconds. Note that since there is no problem when the power is turned off, the supply of the inverted pulse is also stopped at the same time as the power of the receiving circuit 2 is turned off.

Next, the shift register 19, logic circuit 20,
The operation of digital reversible counter 21 will be explained in more detail below. Now, assume that the data in each stage of the shift register 19 and the count value of the digital reversible counter 21 are all "0".At this time, when a digital signal is input, a sign change point is detected, and the holding circuit J8 The shift register 19 outputs a pulse corresponding to the sign change point.Based on the timing of the inverted pulse, the shift register 19 outputs data of "1" when the signal is output, and outputs data of "1" when the signal is not output. “
Input "0" data and shift. Now, if data of 1'' is input to the first stage, the data A input to the first stage by the next inversion pulse = ``'1''
The logic circuit 20 reads out the data B=“0” inputted in the M+1st stage, and the data in the 1st to Mth stages are shifted to the next stage, and
The following data is input into the column. The logic circuit 20 performs the logical operation shown in FIG. 6 on the read data A-'1'' and B-'0'', and
instructs ``to add'' to . The digital reversible counter 21 is placed in addition mode according to the instruction, and adds 1 based on the inverted pulse. Therefore, digital reversible counter 2
The count value changes from 0 to 1, and the data at the second stage to the M+1st stage 1 of the shift register 19 corresponds to number 1, which is "1".Successively after the first data "1", If data ``1'' is input, shift register 1
The contents of 9 are 1" in the first row, "1" in the second row, and 0 in the other rows. The next inversion pulse sets the data A in the first row to "1" and the data in the second row is 0. The data B = "O" in the M+1st stage is read out to the logic circuit 20, and the data in the 1st to Mth stages are shifted to the next stage, and the next data is input to the 1st stage. be done. The logic circuit 20 performs a predetermined logical operation on the read data A-"1" and B="0, and instructs the digital reversible counter 2 to "add." The digital reversible counter 2 is set to the addition mode according to the above instruction, and is set to 1 based on the inverted pulse.
Add.

As a result, the count value of the digital reversible counter 2 becomes 2, and the data from the second stage to the M+1st stage of the shift register 19 match the equation 2, which is l". Conversely, the first data ``When data ``0'' is input after ``1'', data A becomes 'O' and data B also becomes 1. do not"
Even if the inverted pulse is input to the digital reversible counter 2, no addition is performed and the count value remains 1.

This corresponds to Equation 1 in which the data from the second stage to the M+1st stage of the shift register 19 is '1'. Furthermore, the data of each stage of the shift register 19 and the count value of the digital reversible counter 2 are all O#, and when data "0" is successively input to the first stage of shift register J9, data A in the first stage and data B in the M+1 stage become "0". "Yes, the logic circuit 20 instructs the digital reversible counter 2 not to count." Therefore, the count value of the digital reversible counter 2 remains O, and the number of data, which is 11, from the second stage to the M+1st stage is 0.
matches.

Next, all the data in each stage of the shift register 19 is '1'.
1, and the count value of the digital reversible counter 21 is M. Now data “1” is the first in shift register J9.
If it is input to the first stage, the next inverted pulse will cause the first
The data A = "1" inputted in the first stage and the data B = "1" in the M+1st stage are read out by the logic circuit 20, and the data in the first to Mth stages are respectively input to the next stage. The data is shifted and the next data is input to the first stage. The logic circuit 20 performs a predetermined logical operation on the read data A="1" and B="1" and instructs the digital reversible counter 2 not to add. The digital reversible counter 2 is placed in a non-counting mode according to the above instruction, and does not add even if an inverted pulse is input. Therefore, the count value M of the digital reversible counter 2 does not change, and the data from the second stage to the M+1st stage of the shift register 19 match the number M, which is "1". After that, the data “
Even if 1" is input, the count value remains M. Conversely, if data 0 is input to the first stage of the shift register 19, data A is 0 and data B is 0. 1"
Therefore, the logic circuit 2θ is connected to the digital reversible counter 2.
The count value of the digital reversible counter 2 becomes M-1. This is the second shift register 19.
The number M- where the data from the row to the M+1 row is 11
Matches 1. That is, 1 is placed in the first stage of the shift register 19.
” data is input, and from the M+1th stage
By adding or subtracting 1 to the count value of the digital reversible counter 21 every time the data of `` exceeds the limit, the count value is always changed so that the data from the 2nd stage to the M+1st stage of the shift register 19 is ``1''. ” to match a number.

The digital comparator 22 inputs the count value of the digital reversible counter 2, compares it with a preset reference value, and when the count value is greater than the reference value, outputs a digital signal "present" as a clock signal. Output based on the timing of - In the film, if the digital signal is a signal with random properties, the code turning point of the NRZ code is approximately 1/1 of the number of bits.
2, the digital comparator 22 inputs, for example, V3 (
If M is preset as shift register 22190 (number of stages - 1), if the digital signal is normal, the count value of digital reversible counter 2 will exceed V3, and a detection signal of digital signal "present" will be sent to output terminal 23. is output for each clock signal. On the other hand, if noise or a signal with a different period is input, the probability that the iR pulse will appear in the output of the determination circuit J6 is small, as shown in FIG. The number of 1″ data up to the M+1 stage also becomes smaller, the count value of the digital reversible counter 21 becomes P4/3 or less, and the digital comparator 22 does not output a detection signal of “present” digital signal. . Therefore, the presence or absence of a digital signal can be detected continuously and accurately.

By the way, in order to improve the efficiency of battery saving, it is necessary to make the power-on time T1 of the receiving circuit 2 shown in FIG. 1 during reception standby as short as possible (for example, 6 Z 5 ms). However, if the time Tl is shortened, the number of detection bits that the signal detection circuit 4 can detect within the time Tl also decreases (for example, at most 24 bits when the pit rate is 512 b/s).
As described above, the signal detection circuit 4 often performs erroneous detection due to noise and outputs a detection signal indicating that a signal is present even when there is no signal. When the logic processing circuit 3 receives the detection signal, the logic processing circuit 3 performs the process shown in FIG.
In the part (a), the operation to search for the synchronous code SC is started, and the power of the receiving circuit 2 is continuously turned on until the synchronous code SC is found, resulting in an increase in power consumption.

Therefore, in the embodiment shown in FIG. 1, in order to prevent the signal detection circuit 4 from malfunctioning due to noise, the number of detection bits is increased (for example, to 64 bits).

The signal detection circuit 4 detects a digital signal corresponding to the number of detected pits over a plurality of power-on timings, and although the signal detection operation is stopped during the power-off time, the signal detection operation is performed as if it were continuous. It was made to look like this.

(Effects of the Invention) As explained in detail above, according to the present invention, the number of detection bits is set to a value sufficient to prevent malfunctions due to noise,
Since the signal is detected for the demodulated signal for the number of detection bits over several short periods when the receiving circuit's power is periodically turned on, it is possible to prevent a decrease in the efficiency of service saving and to obtain an accurate signal. Detection can be performed.

Furthermore, since it is possible to detect signals other than the brain ampule, it is possible to accurately detect the calling signal even if the brain amble is missed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a conventional signal detection method, FIG. 3 is an explanatory diagram of the operation of the power supply control circuit shown in FIG. 1, and FIG. 4 is a diagram similar to the one shown in FIG. Figure 5 is a waveform diagram of each part of Figure 4, Figure 6 is a logic circuit operation table, Figure 7 is a waveform diagram of each part of Figure 4 when noise is input, Figure 8 is a block diagram of the signal detection circuit shown in Figure 5. 4 is an explanatory diagram of the operation of the gate circuit shown in FIG. 4. FIG. 1... Receiving antenna, 2... Receiving circuit, 3... Logic processing circuit, 4... Signal detection circuit, 5... Power supply control circuit, 11... Input terminal, 12... Code Turning point detection circuit, 13... Clock regeneration circuit, 14... Master clock oscillator, 5... Time slot generation circuit, 16... Judgment circuit, 17... Inverted pulse generation circuit, 18...・Holding circuit, No. 9...Shift register, 2
0...logic circuit, 2no...digital reversible counter, 2
2...Digital comparator, 23...Output terminal, 24...
...Control input terminal, 25...9-digit circuit. Patent Applicant: Oki Electric Industry Co., Ltd. Block Diagram of the Title: 100th Anniversary of Button No. 4 Button Output Method 2' Figure 2: Name: 1 5-source Control Shown in Figure 1 Diagram showing the operation of the mouth route. Gin 0 Taku 4 Figure p Each Kakumi skin shape Figure 7

Claims (1)

[Claims] 1. In a signal detection method for a selective call receiver in which the power of the receiving circuit is periodically turned on for a time T while waiting for a reception input, the digital signal demodulated by the receiving circuit each time the power is turned on. Continuously detect code change points, and set the time T
1. A signal detection method comprising: a signal detection circuit that outputs a detection signal when the number of code change points in a longer time than a predetermined value is greater than or equal to a predetermined value. 2. The signal detection circuit includes: a code change point detection circuit that outputs a conversion pulse at each sign change point of the digital signal; a clock regeneration circuit that reproduces a clock signal from the digital signal; and a clock regeneration circuit that reproduces a clock signal from the digital signal; a determination circuit that extracts only synchronized signals; a gate circuit that controls passage of the clock signal based on an external control signal; and a gate circuit that controls passage of the clock signal based on an external control signal;
an M+1 stage shift register in which data of "1" is written sequentially based on a clock signal from the gate circuit, and data of "0" when the data is not output; and a second stage to M+1 stage of the shift register. a counting means for counting the number of "1" data present until then based on a clock signal from the gate circuit, and comparing the counted value by the counting means with a preset reference value, and when the counted value is greater than or equal to the reference value. 3. The signal detection method according to claim 1, further comprising a digital comparator that outputs a detection signal for each clock signal from the gate circuit when the clock signal from the gate circuit is The data of the first stage and the M+1 stage of the shift register are read out for each signal, and when they are "1" and "0", addition is performed.
a logic circuit that outputs a signal instructing subtraction when "0" and "1" and stop counting in other cases; 3. The signal detection system according to claim 2, comprising a digital reversible counting circuit that performs addition, subtraction, or stopping counting. 4. The signal detection method according to claim 2, wherein the gate circuit starts passing the clock signal after a certain period of time has passed after the control signal is input, and ends passing the clock signal as soon as the control signal disappears. .