JPH01272134A - Gate array with test circuit - Google Patents

Abstract

PURPOSE:To improve the rate of fault detection by directly testing a gate by using a test circuit formed to a chip in the test of an integrated circuit device composed of a gate array and to shorten the time required for the test and reduce labor. CONSTITUTION:When PMOS transistors are tested, potential applied from a wiring 9 is brought to a low level. Consequently, all PMOS transistors are brought to an ON state, and all NMOS transistors are brought to an OFF state. An output to an output line 11 of a signal from a signal input line 10 is detected, thus testing the trouble of PMOS transistors. When the NMOS transistors are tested, potential applied from the wiring 9 is brought to a high level. Accordingly, all NMOS transistors are turned ON, and all PMOS transistors are turned OFF. The transmission of the signal is tested between an input signal line 14 and an output signal line 15, thus testing the trouble of the NMOS transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a gate array in which basic cells are arranged in advance on a chip.

(Prior art) In a gate array, basic cell rows and wiring areas are alternately formed on a chip in advance in a mask process, and a desired integrated circuit device is created by adding only the wiring design between the basic cells in a custom process. It was designed to be obtained.

A huge number of test patterns are required to test an integrated circuit device configured with a gate array. Creating test patterns requires a lot of time and effort.

Furthermore, in order to obtain a high failure detection rate, the effort required for this purpose is also large.

(Purpose) The present invention does not test an integrated circuit device constituted by a gate array by creating a test pattern.
The purpose is to directly test gates using a test circuit formed on a chip, thereby increasing the failure detection rate and reducing the time and labor required for testing.

(Configuration) The gate array of the present invention includes a test circuit. In the test circuit formed in the mask process, the MO of the basic cell row
The upper electrode of the polysilicon gate of the S transistor is formed extending to the wiring area, and the polysilicon wiring formed extending to the wiring area is connected to each adjacent diffusion region of the MOS transistor of the basic cell column. A first MOS transistor that applies a potential to each of the gate electrodes, and a second MOS transistor that controls the connection between the polysilicon wirings in the adjacent diffusion regions are formed.

When performing a test, the first MOS transistor turns on the MOS transistor of the basic cell column, and the second MOS transistor turns on the MOS transistor of the basic cell column.
adjacent M of a basic cell column by MOS transistors of
Connect the OS transistor. As a result, in the basic cell column, the MOS transistors to be tested are connected to form a series. By measuring the conduction of the MOS)-transistor array, failures in the elementary cell array can be detected.

Examples will be specifically described below.

FIG. 1 represents one embodiment.

1 is a basic cell column, and 2 and 3 are wiring areas. In the basic cell column 1, basic cells 2o are regularly arranged. In one basic cell 20, two PM○SMOS transistors and an NMOS transistor are formed. 4 is P
A P-type diffusion region serves as the source and drain of the MOS transistor, and numeral 5 indicates an N-type diffusion region that serves as the source and drain of the NMOS transistor. 6 is a gate electrode made of a polysilicon layer, and a pair of PMOS transistors, NM
Commonly provided to OS transistors.

The gate electrode 6 is formed to extend to one wiring region 2 .

In the wiring region 2 where the gate electrode 6 extends, the first
N-type well 7 to form an NMo5 transistor of
is formed in a band shape along the arrangement direction of the basic cell rows. The gate electrode 6 is connected to the well 7 through a contact hole in the glabella insulating film. On the well 7, a gate electrode 8 is formed of a polysilicon layer with a gate oxide film interposed between adjacent contacts with the gate electrode 6.
is formed.

A polysilicon wiring 9 for applying a potential is connected to the end of the well 7. By turning on the NMOS transistor formed by the well 7 and the gate electrode 8, the potential supplied from the wiring s9 is applied to all the gate electrodes 6.

In the PMOSMOS transistor of the basic cell row 1, a signal input line 1o made of a polysilicon layer is connected to the diffusion region 4 at the right end in the figure through a contact hole in the glabella insulating film, and a signal input line 1o made of a polysilicon layer is connected to the diffusion region 4 at the left end. A signal output line 11 made of a polysilicon layer is connected through a contact hole in the insulating film. A wiring 12 made of a polysilicon layer and extending to the wiring region 2 is connected to each adjacent diffusion region 4 other than the diffusion regions 4 at both ends thereof through a contact hole in the glabella insulating film.

A second NMOS transistor is also formed in the wiring region 2 by an N-type well 13 and a polysilicon gate electrode 8, and a wiring 1 connected to the adjacent diffusion region 4 is formed.
2 is connected via its second NMOS transistor.

Similarly, in the NMOS transistor of the basic cell row 1, a signal input line 14 made of a polysilicon layer is connected to the diffusion region 5 at the right end in the figure through a contact hole in the glabella insulating film, and the diffusion region 5 at the left end A signal output line 15 made of a polysilicon layer is connected to through a contact hole in an interlayer insulating film. Each adjacent diffusion region 5 other than the diffusion regions 5 at both ends has a wiring region 3.
A wiring 16 made of a polysilicon layer extending to
are connected through contact holes in the glabella insulating film.

Also in the wiring region 3, a second NMOS transistor is formed by an N-type well 17 and a polysilicon gate electrode 8, and a wiring 1 connected to the adjacent diffusion region 5 is formed.
6 is connected via its second NMOS transistor.

FIG. 2 shows an equivalent circuit diagram of the gate array at the stage where the master process in FIG. 1 has been completed.

A gate electrode 6 of the basic cell 20 is connected to a wiring 9 for applying a potential via a first NMOS transistor Q1. Between adjacent PMOS transistors of basic cell row 1 and N
The MOS transistors are connected through a second NMOS MOS transistor Q2.

Using the gate array of this example, a desired circuit is constructed by applying metal wiring in a custom process. If the gate indicated by the symbol 18 in FIG. 1 is an unused gate, there is no need to test the unused gate, so the source and drain of the gate 18 are short-circuited by the metal wiring 19 in the custom process. .

Next, the operation of this embodiment will be explained.

Apply metal wiring to configure an integrated circuit device.

The actual use mode or the test mode is switched by a signal from the gate electrode 8. When the signal on the gate electrode 8 is at a high level, it is a test mode, and when it is at a low level, it is an actual use mode.

If low level, gate electrode 8 and well 7.13.1
All of the NMOS transistors formed by 7 are turned off, resulting in the same state as if this test circuit did not exist.

Next, the test mode will be explained.

In the test mode, the gate electrode 8 is set to a high level. At this time, all the NMo5 transistors in the wells 7, 13, and 17 are turned on, and the potential applied to the wiring 9 is applied to all the gate electrodes 6 of the basic cell column 1. Also,
Since the second NMOS transistor is also turned on, all the PMOS transistors are connected by the wiring 12. All NMOS transistors are also connected within the basic cell column 1 via wiring 16.

When testing the PMOS transistor, the potential applied from the wiring 9 is set to low level. This allows PMOS
All transistors are turned on, and all NMOS transistors are turned off. Therefore, by detecting whether the signal from the signal input line 10 is output to the output line 11, it is possible to test for failure of the PMOS transistor. Since the gate provided with metal wiring 19 is short-circuited, no test is performed.

When testing the NMOS transistor, the potential applied from the wiring 9 is set to a high level. This turns on all NMOS transistors and turns off all PMOS transistors. By testing the signal transmission between the input signal line 14 and the output signal line 15, the NMOS transistor can be tested for failure.

Regarding the NMO8)-transistor as well, if there is an unused gate, the unused gate can be short-circuited with a metal wiring so that the unused gate is not tested.

In the embodiment, the first and second MOs formed in the wiring area
Although the S transistor is of N type, it can also be of P type.

(Effects) In the present invention, a test circuit is formed in advance in a master process using MOS transistors and polysilicon wiring formed in the wiring area, and gate failures can be tested after the metal wiring is completed, resulting in a high failure detection rate. can be obtained easily.

Further, metal wiring is not used in the test circuit formed in the mask process, and in the subsequent custom process, a desired circuit can be constructed using metal wiring as in the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing one embodiment, and FIG. 2 is a circuit diagram showing an equivalent circuit upon completion of the master process. 1... Basic cell row, 2, 3... Wiring region, 4.5... Diffusion region, 6... Gate electrode of basic cell, 7. 13.17... N-type well, 8... Gate electrode in wiring area, 12.1
6... Polysilicon wiring, Ql... First MOS transistor, Q2... Second MO
S transistor.

Claims (1)

[Claims] (1) Polysilicon gate electrodes of MOS transistors in the basic cell row are formed extending to the wiring region, and polysilicon wirings formed extending to the wiring region are connected to individual adjacent diffusion regions of the MOS transistors in the basic cell row. a gate array in which a first MOS transistor that applies a potential to each of the gate electrodes and a second MOS transistor that controls connections between polysilicon wirings in the adjacent diffusion regions are formed in the wiring region; .