JPH01283866A - Semiconductor memory and semiconductor device - Google Patents

Abstract

PURPOSE:To merely form a protective film in a later step and to shorten a forming period by forming a wiring layer, and connecting one of source, drain electrodes of a MOS transistor with conductive substance to write ROM data. CONSTITUTION:Bit lines 1, 2 are connected to the drain electrode of a MOS transistor with conductive substance 8 after the wiring layer of the bit lines 1, 2 is formed. Accordingly, ROM data is written in a state that formed immediately before a final step including the wiring layer except the connection of a memory cell, and then only a step of forming the protective film remains. Thus, a manufacturing period can be shortest. Further, a peripheral circuit can be operated in a state before the ROM data is written, and an operation test and a DC test can be performed in this state.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device comprising a MOS transistor and a wiring layer, and a connection structure between a MOS transistor or a wiring layer different from the wiring layer and the wiring in the semiconductor device. .

[Prior art 1] A mask ROM is a semiconductor memory device whose memory cells are composed of MOS transistors, and the structure of a mask ROM in which data is written using a photo-etching mask during the manufacturing process is based on the electronic material 1986.
January, pages 104-108 r4M Bitmask R
The structure is as shown in Figure 2 of ``OM and its Applications''.
Data writing using contact windows, diffusion layers, and ion implantation is known. In FIG. 2, the ion implantation method is shown as an example of a circuit configuration in which memory cells are connected in series and connected to a bit line, but (2) in FIG.
It is also possible to implant ions into the channel region of the MOS transistor in the structure shown in the diffusion layer method to increase the threshold voltage of the MOS transistor if it is an N-channel MOS transistor. Regardless of the data writing method, data is written depending on whether there is a current path from the bit line to the ground terminal via a MOS transistor, and whether the current is detected through the bit line or connected to a high voltage source. It detects the voltage determined by the resistance ratio with the load resistance, and detects binary information. The contact window method (1) in FIG. 2 is a method of determining whether or not to connect the aluminum bit line to the MOS transistor train through a contact window.
The device shown in FIG. 2 writes data depending on whether or not the aluminum bit line is connected. 1.2 is aluminum which is a bit line, 3 is a diffusion layer, 4.5.6 is a word line that selects a memory cell and is polycrystalline silicon which is the gate material of a MOS transistor, and 7 is a connection between aluminum and the diffusion layer. It is a contact hole, and is a diagram showing a state in which the aluminum 10 of the drain electrode portion of the MOS transistor and the aluminum 2, which is the bit line, are not connected, but other MOS transistors are connected.

Next, a conventional example of connection of wiring layers in a semiconductor device is shown in FIG. 3. In FIG. 3, 11.12 represents the outline of a pattern forming a functional block,
1 to 144 are first wiring layers, 131 to 134 are second wiring layers, and 15 are contact holes for connecting the first and second wiring layers. In Figure 3, 144
becomes 131, 143 becomes 132, 142 becomes 133, 1
41 is connected to 134. The MOS transistor portion of the semiconductor device is also connected to the wiring layer, and this portion also has the same structure as the example shown in FIG.

[Problem to be solved by the invention]

The above-mentioned method is known as a data writing method for a semiconductor memory device, but as mentioned in the above-mentioned paper, in the case of a mask ROM, the user places an order, that is, sends the ROM data, and then writes the photomask. An important issue is the period from fabrication to delivery of a semiconductor memory device to a user through a wafer process (in the paper, this is proven as TAT...turnaround time). Compared to this manufacturing lead time, the diffusion layer method is a step at the beginning of the wafer process and is very slow.The contact window method has the fastest lead time in the above paper, but even in this case, aluminum Two steps are required: first and protective film. In addition, when writing in the photoetching process shown in FIG. 2 when forming aluminum, the MO shown in FIG.
A space is required between the aluminum 1O of the S transistor train electrode and the aluminum 2 which is the bit line, which can be separated by photoetching.For example, a 2μm design rule requires a space of 2μm or more, making the memory cell larger, and as a result. Increasing the chip size increases the price, and when writing data in aluminum, which is the wiring layer shown in Figure 2, the wiring layer is also used for the peripheral circuit of the semiconductor memory device, so the ROM
Since the data writing pattern and the wiring layer of the peripheral circuit are included in the same photomask, the number of patterns on this photomask becomes extremely large, which increases the data preparation time for photomask production and also increases the number of patterns. This increases the probability of defective products due to defects during photomask production, resulting in delays in photomask production delivery and an increase in the price of photomasks.

On the other hand, in connection of the wiring layers of a semiconductor device as shown in FIG. The third layer requires changing the photomask backing for a total of three layers:
The explanation in the figure is an example of a general semiconductor device, but in a so-called gate array in which MOS transistors or functional elements are manufactured in advance on a wafer process and the user's functional specifications are created using wiring layers, the explanation in the three figures above is used. As explained previously, it is common to make a three-layer photomask, and the development cost for three photomasks is required. In addition, in terms of development delivery time, the wafer process requires four steps including the protective film process, which lengthens the wafer process.Furthermore, as mentioned above, there is a high probability of defective products in photomask production. For some reason, if the three photomasks are not placed sequentially in the wafer process order, the wafer process period will become even longer.

The present invention writes data in a semiconductor memory device in the final step after forming a wiring layer, and also in a semiconductor device, by using a single photomask after forming a wiring layer, a semiconductor memory device and a semiconductor device can be produced at a low price with a short lead time. The purpose is to obtain.

[Means to solve the problem]

A semiconductor memory device of the present invention includes a plurality of memory cells made of MOS transistors and peripheral circuits including input and output circuits, in which a MOS transistor including the memory cells is formed, and an insulator on the MOS transistors is provided. A wiring layer formed on the object and connected to the peripheral circuit through a contact hole, and the insulator on at least one of the source and drain electrodes of the MOS transistor that is the memory cell before or after the formation of the wiring layer. and at least one of the source and drain electrodes of the MOS transistor (MOS) transistor, which is the memory cell, and the wiring layer is connected through the opening. The wiring layer is characterized by comprising a conductive material different from that of the wiring layer.

Further, in the semiconductor device of the present invention, the semiconductor device includes a MOS transistor and a wiring layer formed on the MOS transistor via an insulator, in which the wiring layer and the MOS
an opening in the insulator that is opened before or after the formation of the wiring layer on the electrode of the transistor or on a wiring layer different from the wiring layer, the electrode of the MOI transistor or the actual wiring layer and the wiring; The semiconductor device is characterized by comprising a conductive material different from the wiring layer formed to connect the layers through the openings of the insulator.

〔Example〕

FIG. 1 is a plan view showing a memory cell portion of a semiconductor memory device according to an embodiment of the present invention. The embodiment shown in FIG. 1 has the same configuration as the conventional example shown in FIG.
The drain electrode of the transistor is connected with a conductive material 8 after the wiring layer of the bit line 1.2 is formed. FIG. 4 shows a cross-sectional structure of a portion indicated by a dashed line 9 in the embodiment of FIG. 1. In FIG.
An oxide film 16 is selectively formed to form an S transistor and a diffusion layer, and then a gate oxide film for a MOS transistor (not shown in FIG. 4) is formed.
The gate electrode of the OS transistor, for example, polycrystalline silicon is formed, and then the source and drain diffusion layers 3 of the MOS transistor are formed to form the MOS transistor. An oxide film 18 is formed to insulate and isolate the wiring layer and the source, drain, and gate of the MOS transistor from the oxide film 18 on the diffusion layer 3 in FIG. 4 and other peripheral circuits not shown in FIG. For the portion where the polycrystalline silicon used as the electrode or the gate electrode is used as a wiring layer, the insulating oxide film 18, which is a contact hole for connection, is opened, and then wiring layers 1 and 2 made of aluminum, for example, are formed. do. In this state, the MOS transistors, wiring layers, and their connections are completed, except for the memory cell portions shown in FIGS. 1 and 4, and the peripheral circuits of the semiconductor memory device perform their functions. The memory cell portion shown in FIGS. 1 and 4 is a zero-order semiconductor memory device that is not connected because the aluminum 1.2, which is the wiring layer, and the contact hole 7 for connection are located apart from each other as shown in the figure. Based on the data, a connection pattern 8 between the memory cell and the wiring layer 1.2, which is a bit line, is formed, and the final step is to form a protective film to complete the process. In the embodiment of the present invention shown in FIGS. 1 and 4, everything up to just before the final process, including the wiring layer, except for the connection of the memory cell part, is fabricated using the conventional general manufacturing process. There will be a process to write ROM data, and after that the only process will be a protective film.
It is possible to minimize the manufacturing delivery time. In addition, as mentioned above, the peripheral circuits can operate in the state before ROM data is written, and therefore operation tests and DC tests can be performed in this state. For example, if a wafer with a process abnormality is Since it is possible to detect the process abnormalities and to write ROM data except for products with process abnormalities, it becomes possible to manufacture semiconductor memory devices with stable manufacturing deadlines.

Further, as shown in FIG. 1, the conductive material 8 for connecting the memory cell, such as titanium, need only be formed at the connection portion, and therefore, it is possible to overlap the conductive material 8 by the amount of misalignment with the bit line in FIG. On the other hand, if the bit line is separated from the contact hole 7 by the alignment margin, it can be made separately when forming the bit line. When etching the connecting titanium, the semiconductor substrate may also be etched, so the contact hole 7 is made so as to be covered with the connecting titanium 19 which is not connected in FIG. As a result, in the direction in which the memory cell is connected to the bit line 1.2, and also in the direction in which it is not connected, only the alignment margin between aluminum, which is the bit line, and titanium, which is the connection layer, is sufficient.

FIG. 5 shows another embodiment of the present invention, in which the contact hole portion is covered with titanium for connection in the embodiment shown in FIG. 1, but only the connection portion between the bit line and the memory cell is covered. In this structure, a wiring layer for connection is formed in the bit line, and a contact hole for connection is opened after the bit line is formed. FIG. 6 shows the manufacturing process of the embodiment shown in FIG. 5, and FIG. 0(a), which shows the cross-sectional structure of the same part as FIG. 0th order (b) showing the state in which the oxide film 18 is formed.
This is a diagram in which a wiring layer 24 is formed on top, and the wiring layer 24 is made of a high melting point metal such as titanium, tungsten, or molybdenum. Although not shown in Figure (b), in the peripheral circuit, the wiring layer 24 may be formed after forming contact holes for connection between the wiring layer and the electrodes and wiring portions of the MOS transistors. As shown in FIG. 6, after the wiring layer 24 is formed, it is also possible to open a contact hole for connection in common with the memory cell. Furthermore, it is also possible to make the connection of a part of the peripheral circuit the same as the connection of the memory cell.
In C), a contact hole 7 is formed in the oxide film 18 over the drain region of the memory cell. At this time, the first
In the example shown in the figure, it was explained that it is necessary to separate the bit line from the contact hole by the alignment margin, but in Figures 5 and 6,
In the example shown, there is no need to consider the alignment margin between the contact hole and the bit line. For example, even if the contact hole and the bit line overlap, the contact hole is formed using the wiring layer as a mask, and the bit line and memory cell are connected. The memory cell and wiring layer 24 are connected to each other in the zero-order diagram (d), which will not be connected. This method uses a method to create a structure similar to the salicide structure, which is used as a method to reduce the resistance of semiconductors. Metal is formed on the entire surface of the semiconductor substrate, and the metal is in contact with the drain region of the MOS transistor through the contact hole 7. This is a method of selectively forming a metal silicide layer on the substrate or polycrystalline silicon by siliciding the metal in the part, and when etching this silicide layer, 88 According to the pattern shown in FIG. 6, a resist or the like is applied to simultaneously form the connection wiring layer shown in FIG. According to the embodiment of FIGS. 5 and 6, the contact hole 7
There is no need to consider the combined margin of bit lines 24 and 25,
It is only necessary to make a hole in the oxide film that is large enough to make a connection through the contact hole, and even for bit lines that are not connected, the wiring layer for connection is self-fabricated only in the opening with respect to the contact hole. Since it can be formed in a line, only the alignment margin between the bit line and the contact hole is required.

Next, an example of a wiring layer in a semiconductor device is shown in FIG. 7. The example shown in FIG. 7 is a plan view corresponding to the conventional example shown in FIG. Regarding the connection of layers, I think it can be understood that it can be manufactured in the same manner as in the embodiments of the semiconductor memory device shown in FIGS. 1 and 4.
In the figure, when switching the connections between wires 134 and 141, 132 and 143 to wires 134 and 143, or 132 and 141, this can be done by simply changing the connection layer 8, and as described above, it is possible to It is possible in the final process,
Manufacturing delivery time due to changes can be minimized. The structure of the connection part in the embodiment shown in FIG. 7 is the same as that in FIG. 1, and the structure of the embodiment shown in FIG. It can be understood that the structure is as follows.

The embodiment shown in FIG. 7 is an example showing a partial wiring connection change in a semiconductor device, and FIG. 8 shows an example in which wiring portions are connected in this structure.
27 is a circuit function block, 33.34 is a circuit block 2
6 input and output terminals, 28 to 32 are the second wiring layer,
33-37. 39-40 are the first wiring layers. 8th
In the embodiment shown in the figure, only the wiring of the circuit block 26 is connected, and the four circuit blocks 26 and 27 are connected.
It simply shows only the part surrounded by blocks. In Figure 8, the input or output terminal 3 of the circuit block
3 is connected from the first wiring layer to the second wiring layer 29 at a circle. Similarly, 29.36.31.
The input or output terminal 34 of the zero-order circuit block 26, shown connected to 32 via 40, is 28.35,
37 via 30.39.38.

In this way, two divided wiring layers and contact holes for connection are placed between the circuit blocks,
Based on the connection information, the first and second layers are
A semiconductor device is obtained by forming three connection layers.

Although the present invention has been described above based on the embodiments of the present invention, the present invention can be used to connect at least one of the source and drain electrodes of a MOS transistor, which is a memory cell, to the wiring layer, or between the wiring layers of a semiconductor device, after forming the wiring layer. It is characterized by making connections. In the embodiment, in a semiconductor memory device,
Although the connection between the source and drain diffusion layers of the MOS transistor and the wiring layer has been described, it is also possible to connect the source and drain diffusion layers after forming separate electrodes of polycrystalline silicon or the like.

[Effects of the Invention] As described above, in the semiconductor memory device according to the present invention, ROM data can be written by connecting at least one of the source and drain electrodes of a MOS transistor with a conductive material after forming a wiring layer. The only step after writing is the step of forming a protective film, making it possible to minimize the manufacturing delivery time. In addition, since it is possible to form the tangential layer of the wiring layer and connect peripheral circuits except for writing ROM data, it is possible to test the peripheral circuits and word lines and bit lines of the memory cell area before writing ROM data, which reduces manufacturing costs. It becomes possible to detect abnormal products during the process, and semiconductor memory devices can be manufactured with stable production deadlines. Also, R.O.
By connecting the connection based on the M data using a conductive material different from the wiring layer, it is possible to form a backbone using only the alignment margin between the conductive material and the wiring layer, or the alignment margin between the contact hole and the wiring layer, and the memory cell This can be realized without increasing the area. Furthermore, the photomask for writing ROM data only has a pattern that corresponds to the ROM data, so the delivery time for photomask production can be shortened and costs can be reduced.In addition to the short delivery time of the manufacturing process, from receiving an order to completing the semiconductor memory device, This can be done in a short period of time, and furthermore, it is possible to reduce costs.

On the other hand, in semiconductor devices, wiring is performed by connecting with a conductive material after the wiring layer is formed, so this can be done with a single photomask, which significantly reduces the cost of photomasks and reduces the development cost of semiconductor devices. Also, like semiconductor memory devices, it can be manufactured in a short period of time.

[Brief explanation of the drawing]

FIG. 1 is a pattern diagram of a memory cell portion of a semiconductor memory device representing an embodiment of the present invention, and FIG.
FIG. 4 is a pattern diagram of a memory cell portion showing an OM data writing method, and FIG. 4 is a sectional view taken along a dashed-dotted line 9 in FIG. 6(a) to (d) are cross-sectional views showing the manufacturing process of the embodiment shown in FIG. 5, FIG. 3 is a pattern diagram showing the wiring portion of the semiconductor device, and FIG. 7 is a diagram showing the wiring of the semiconductor device according to the present invention. The pattern diagram shown in FIG. 8 is a block wiring diagram showing an embodiment of the present invention of a semiconductor device realizing functions by wiring such as a gate array. 1.2.10...Wiring layer 3 which is a bit line...
...Diffusion layer 4.5.6...Word line 7...Contact hole 8.19...
... Connection layer 11.12 ... Circuit blocks 131 to 134 ... Second wiring layer 141 to 144
...First wiring layer 15... Contact hole 16.18... Oxide film 17... Semiconductor substrate 24.25... .・Bit line 20.21...Metal silicide layer 22.23.
...Connection metal 26.27...Circuit blocks 28 to 32.38...Second wiring layer 33 to 37.3
9.40 1st wiring layer and above Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Masatoshi Kamiyanagi (and 1 other person) No. 1 Figure 2 ■ No. 3 No. 5

Claims (2)

[Claims] (1) In a semiconductor memory device consisting of a plurality of memory cells consisting of MOS transistors and a peripheral circuit including input and output circuits, the MOS transistor including the memory cell is formed, and the MOS transistor is formed on an insulator on the MOS transistor. and a wiring layer connected to the peripheral circuit through a contact hole, and an opening made in the insulator over at least one of the source and drain electrodes of the MOS transistor, which is the memory cell, before or after the formation of the wiring layer. and the wiring layer, which includes data writing to the memory cell and is formed to connect at least one of the source and drain electrodes of the MOS transistor serving as the memory cell and the wiring layer through the opening. A semiconductor memory device comprising a conductive material. (2) In a semiconductor device comprising a MOS transistor and a wiring layer formed on the MOS transistor via an insulator, the wiring layer is formed on the wiring layer and the electrode of the MOS transistor or on a wiring layer different from the wiring layer. and the wiring layer formed to connect the electrode of the MOS transistor or the different wiring layer and the wiring layer through the opening of the insulator. A semiconductor device comprising different conductive materials.