JPH01270785A - Speed controller for motor - Google Patents

Abstract

PURPOSE:To suppress overshoot and undershoot by gradually altering a frequency in a state that the speed of a motor itself is controlled when a first constant speed state is switched to a second constant speed state. CONSTITUTION:A variable frequency divider 5 so controls the output frequency of a VOC 11 as to bring the signal from a frequency divider 3 which inputs a reference signal of a clock 1 in phase into coincidence with the output of a variable frequency divider 13 which inputs the output of the VCO 11. A driving signal controller 19 outputs a control signal to a driver 23 in response to the phase and frequency comparison results of the output of the VOC 11 and the pulse signal from a FG circuit 21. When a speed switching command is input, a CPU 15 gradually varies the frequency dividing number of the divider 13. Thus, an oversheet and undershoot can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a motor speed control device, and is suitable for controlling the speed of a motor for rotating a floppy disk, which is used by changing the rotation speed for each track, for example. This invention relates to improvements in speed control devices.

(b) Conventional technology In recent years, floppy disks have been equipped with three
90rpffi, 42Orpm, 470rpm, 5
For example, 100m within a predetermined time so that the speed remains at 30rpm.
There is a device that can be used by changing the rotation speed sequentially for 5 ec.

On the other hand, for example, in a brushless motor, a rotation drive signal is formed using a speed command signal of a predetermined frequency as a reference for speed control, and this is added to a drive filter to ensure a predetermined constant speed rotation.

Therefore, in the brushless motor, in order to change the rotational speed of the floppy disk mentioned above, as shown in FIG. 4, a speed command signal S1. St was switched, and the rotational drive signal was switched instantaneously.

Although two speed command signals S+ and Ss are shown for convenience, the number of speed command signals corresponding to the number of tracks can be switched.

(c) Problems to be Solved by the Invention However, in order to avoid instantaneous changes in the rotational speed, for example, when switching the speed command signal from S to S, a delay element is created in the motor speed control system. There is,
Since control is pulled to the rotational speed after switching, overshoot tends to occur in the motor rotational speed as shown in Figure 5, and the problem is that it takes time for the rotational speed to stabilize after switching. be. Note that FIG. 5 is a waveform diagram showing the speed command signal replaced with a DC level.

Conversely, if the speed command signal S1 is switched to 81, undershoot is likely to occur and similar problems occur.

The present invention has been made to solve these conventional drawbacks, and even if the frequency of the speed command signal is switched to change the rotational speed from the first constant speed state to the second constant speed state, the motor To provide a speed control device for a motor that is less likely to cause overshoot or undershoot and can quickly stabilize the speed to a constant speed state.

(d) Means for Solving the Problems In order to achieve such objects, the present invention forms a variable frequency dividing circuit that outputs a reference signal of a predetermined frequency from a clock and divides the frequency of the reference signal. However, from this variable frequency dividing circuit, the first main speed command, which is the reference of the first constant rotation speed, is output within the time period of change from the first constant rotation speed to the second constant rotation speed. automatically generating and sequentially outputting a second main speed command signal that serves as a reference for the second constant rotational speed through outputting a plurality of sub-speed command signals whose frequencies are sequentially changed from the signal; The drive signal control circuit compares the speed command signal from the variable frequency dividing circuit with a pulse signal of a frequency that can be output according to the rotational speed of the motor, and controls the rotation to suppress changes in rotational speed. It is configured to output a drive signal to the motor.

(e) Effect The present invention equipped with such a means is such that when the frequency of the speed reference serving as a reference for speed control is switched from the first constant speed state to the second constant speed state, the speed command signal is If the first main speed command signal cannot be switched to the second main speed command signal all at once, a sub speed command signal whose frequency is gradually changed is automatically generated and the second main speed command signal is finally output. Apply a rotational drive signal to the motor.

(f) Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a motor speed control device according to the present invention.

A clock signal generator 1 that outputs a reference signal of a predetermined frequency, for example, I MHz, is connected to a variable frequency divider circuit 5 via a frequency divider 3 that divides the frequency of this reference signal by 1/M.

The variable frequency divider circuit 5 is a phase comparator that compares the phase difference between the signal from the frequency divider 3 and the divided signal from the variable frequency divider 13 (described later) and outputs a voltage according to the phase difference. 7, a low-pass filter (LPF) 9 that removes high frequency components from the signal from the phase comparator 7, and a vColl that variably oscillates a frequency signal so as to reduce the DC signal according to the DC signal from the LPF 9. A variable frequency divider 13 that divides the oscillation signal from the VCOIL into 1/N and outputs self-divided signals with different frequencies to the phase comparator 7 by varying N.
and a control means for sequentially changing the frequency divider 13ON, for example, C
It is composed of PU15.

That is, this 6-just frequency divider circuit 5 can be used for, for example, the CPU 15.
, outputs a first main speed command signal S1 having a frequency that controls the first constant rotation speed shown in FIG. A plurality of auxiliary speed command signals al 1 , al +al whose divided frequencies are successively increased are sequentially output at predetermined time intervals within a period during which the second main speed command signal S having a frequency that controls the second main speed command signal S is output.

The number of sub speed commands A3 is not limited to three, and can be arbitrarily selected by the CPU 15, and within the time of change from the first main speed command A3 S1 to the second main speed command S,
At predetermined intervals, sub-speed commander numbers a,, a,, a,...
You can configure it to output .

Therefore, the means for changing the frequency division number in the variable frequency divider 13 is not limited to the CPU 15. Sub speed command signal a1. of the set frequency. a,,'a,・
It is sufficient if the configuration is such that the frequency is divided into . . . and output.

Note that the phase comparator 7, LPF 9, VColl, and variable frequency divider 13 constitute a PLL circuit that stabilizes the frequency of the main speed command signal S, , S, and the sub speed command signal a H, a l ) 'L s. are doing.

The oscillation signal from the VColl is connected to the drive signal control circuit 19 via a frequency divider circuit 17 that divides the frequency to, for example, 1/2580.The zero frequency divider circuit 17 also has the same PLL circuit configuration as the variable frequency divider circuit 5. It has become.

A pulse generator circuit (FG circuit) 21 is connected to the drive signal control circuit 19 and outputs a pulse signal having a frequency corresponding to the rotational speed of the motor 25.
The frequency-divided output from the FC circuit 21 and the pulse signal from the FC circuit 21 are compared in phase and frequency, and the pulse signal from the FG circuit 21 is controlled to a predetermined value and a drive signal is output. It is connected to the circuit 23.

The drive circuit 23 is connected to a drive coil of the brushless morph 25, for example.

In the motor speed control device having such a configuration, when a speed switching command is issued, the CPU 15 determines the frequency division number in the frequency divider 13 and sequentially changes the frequency division number.

Therefore, as shown in FIG. 2, the main speed command signal S1 is followed by the sub speed command signal a1. alvan is output from vCOll, and finally the main speed command signal S is output.

Therefore, the drive signals applied to the motor 25 are the main speed command signals S, , S and the sub speed command signals a1, a Ht
As can be inferred from Fig. 3 in which a @ is replaced with a DC level, the main speed command signals SI to S.

During this period, the side speed command signals al+atvas are gradually added, and the drive signal applied to the motor 2S changes little by little.

At that time, for example, since the change from the main speed command signal Sl to the sub speed command signal a1 is small, the servo function is activated by the signal from the FG circuit 21, and the change occurs sequentially without overshooting, and finally the main speed command signal It switches to the speed command signal S.

Note that when switching from the second main speed command signal S to the first main speed command signal S, the second main speed command signal S2, the sub speed command signal ag tag, a l % of the first main speed command signal The speed command signals are output in the order of S1.

When the constant speed state is the first, second, third, fourth, fifth, etc., the above-described operation is repeated.

(G) As described in detail of the invention, the motor speed control device of the present invention applies speed control to the motor 25 itself when switching from the first constant speed state to the second constant speed state. Since the rotational drive signal is controlled by automatically generating the speed command signal al, @*1ms, i whose frequency is gradually changed, overshoot and angular drive are less likely to occur, and a constant speed state can be maintained quickly. This makes it possible to maintain good rotational stability.

Therefore, erroneous control can be suppressed. It is particularly suitable for a motor speed control device that uses the rotational speed results to ensure a constant rotational speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a motor speed control device according to the present invention, FIG. 2 is a waveform diagram showing a speed command signal from the variable frequency dividing circuit in FIG. 1, and FIG. Figure 2 is a diagram in which the speed command signal has been replaced with a DC level, Figure 4 is a waveform diagram showing the speed command signal in a conventional motor speed control device, and Figure 5 is a diagram in which the speed command signal of the 4th ryJ has been replaced with a DC level. It is a diagram. 1... Clock, 3... Frequency divider, 5... Variable turbidity circuit, 7... Phase comparator, 9... LPF, 11...
・vCO113...Variable frequency divider, 15...CPU,
17... Frequency dividing circuit, 19... Drive signal control circuit, 2
1... FG circuit, 23... Drive circuit, 25...
·motor. Applicant: Sanyo Electric Co., Ltd. and one other representative Patent attorney Takuji Nishino (one other person) Figure 1 Figure 2

Claims (1)

[Claims] (1) a clock that outputs a reference signal of a predetermined frequency; A second main speed, which serves as a reference for the second constant rotation speed, is obtained through the output of a plurality of sub-speed command signals whose frequencies are sequentially changed from the first main speed command signal, which serves as a reference for the high rotation speed. A variable frequency divider circuit that sequentially outputs command signals; and a control circuit that compares the speed command signal from the variable frequency divider circuit with a pulse signal of a frequency corresponding to the rotational speed of the motor, and controls to suppress changes in the rotational speed. 1. A motor speed control device comprising: a drive signal control circuit that outputs a rotational drive signal to the motor;