JPH01270482A - Color difference signal processor - Google Patents

Abstract

PURPOSE:To minimize the number of parts and to simplify a constitution by sharing the processing circuit of two color difference signals of a MUSE system. CONSTITUTION:A digital MUSE signal delayed by a delaying circuit 1 and the signal not delayed by the circuit for 1H of 1125 horizontal scanning line systems are alternately written through latch circuits 2 and 3 to a 1H memory 4 of 525 horizontal scanning line systems. The memory 4 is read by the clock of 2.8MHz, a time extension is executed and it is inputted through a latch 5 to 1H memories 6 and 7. When a switch 10 is at a lower side, the signal 1H-delayed by a memory 6 and the signal not delayed are added by an adder circuit 9 and made 1/2-fold. And thus, an R-Y signal is outputted. When the switch 10 is at an upper side, the signal 2H-delayed by the memories 6 and 7 and the signal not delayed are added, made 1/2-fold, the signal and the signal 1H-delayed by a memory 6 are inputted to the circuit 9 and a B-Y signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color difference signal processing device for high-definition TV signals and the like transmitted by the MUSE method.

[Summary of the invention]

In the present invention, two color difference signals are processed and separated by a common circuit.

[Background technology]

In recent years, television broadcasting has been carried out using the high-definition system, which can display higher-quality images than the conventional NTSC system, and the band of this high-definition TV signal is compressed using the Muse system and broadcast to each home via satellite. It is proposed to do so.

According to this Muse method, a single color (C) signal is time-axis compressed line-sequentially and time-division multiplexed with a luminance (Y) signal. This method is called TCI (Time Compressed
This is called the "Integration" method. In this system, the C signals are R-Y and B-Y color difference signals, and these are transmitted alternately for each LH.

The high-definition signal transmitted using the Muse method is the same as the conventional N
Although it cannot be received directly by a TSC TV receiver, it can be received by performing some processing, such as reducing the number of horizontal scanning lines using a vertical filter.

In such a conventionally proposed receiving device, dedicated processing circuits are provided for each of the two color difference signals in order to separate them.

[Problem to be solved by the invention]

However, since conventional devices are equipped with dedicated processing circuits for each to separate and extract the two color difference signals, the number of parts not only increases, but the configuration becomes complicated and costs increase. There are drawbacks.

The present invention was developed in view of the above situation, and is intended to realize a low-cost color difference signal processing device with a small number of parts, a simple configuration, and a low cost.

[Means to solve the problem]

The color difference signal processing device of the present invention delays a first TV signal in which a first color difference signal and a second color difference signal are inserted alternately for each LH to obtain a second TV signal. a delay circuit; a first latch circuit driven by one edge and the other edge of a first clock having a first frequency and supplying the first TV signal and the second TV signal to the same line; A second delay circuit delays the signal supplied to the same line by the first latch circuit by 1H, and a second delay circuit delays the output of the second delay circuit by 1H.
a third delay circuit that delays; a first addition circuit that adds the input to the second delay circuit and the output of the third delay circuit;
a switch that selects the input to the second delay circuit and the output of the first addition circuit using a first clock; and a second addition circuit that adds the output of the second delay circuit and the output of the switch;
A second latch circuit that latches the output of the second adder circuit at one edge and the other edge of a second clock of a second frequency, and separates and outputs the first color difference signal and the second color difference signal. Equipped with.

[Effect]

The first TV signal and the second TV signal are introduced into a common S path by the positive and negative edges of the high frequency first clock. The common line includes second and third delay circuits and a first delay circuit.
and a second adder circuit are connected to a switch driven by the first clock, so that, for example, R-Y
and B-Y color difference signals are processed. A latch circuit driven by a low frequency second clock separates the two color difference signals from this processing circuit.

Therefore, the two color difference signal processing circuits are shared, making it possible to reduce the number of parts and reduce costs.

〔Example〕

FIG. 1 is a block diagram of a color difference signal processing device according to the present invention. In the figure, reference numeral 1 denotes a delay circuit, which delays the input digitized Muse TV signal by LH (LH of 1125 horizontal scanning lines in the high-definition system) and outputs the delayed signal. The delayed TV signal is latched by the latch circuit 3.

On the other hand, signals that are not delayed by delay circuit 1 are sent to latch circuit 2.
latched by latch circuits 2 and 3.

They are driven by the positive and negative edges of a clock with a frequency of 5 and 6 MHz, respectively. The outputs of the latch circuits 2 and 3 are integrated into a common line and written into a 1H memory 4 (525 horizontal scanning line system in the NTSC system). Since the write clock of the memory 4 has twice the frequency (11 MHz) of the clocks of the latch circuits 2 and 3, the data of the signal delayed by 1H and the data of the signal not delayed are alternately written into the memory 4.

Data written in the memory 4 is read out using a clock having a frequency of 2.8 MHz. Therefore, time axis expansion is performed here.

The data read from the memory 4 is sent to the LH memory (525 lines) 6, 7 and the adder circuits 8, 9 via the latch circuit 5.
．． The signal is input to a processing circuit consisting of a switch 10. Writing and reading are performed on the memory 6.7 using a clock of 5 and 6 MHz, and switching of the switch 10 is performed using a clock of 5.6 MHz.

When the switch 10 is switched to the lower side in the figure, the signal delayed by 1H by the delay circuit 6 and the signal that is not delayed are input to the adder circuit 9 and are added at a level of 1/2. As a result, the adder circuit 9 outputs the R-Y color difference signal.

On the other hand, when the switch 10 is switched to the upper side in the figure, the output of the delay circuit 7 which further delays the signal delayed by 1H by the delay circuit 6 and the signal not delayed by the delay circuit 6 are at 1/2 level each. are added by the adder circuit 8. Then, the output of the adder circuit 8 and the output of the delay circuit 6 are added by the adder circuit 9 at each level of 172. In this manner, the adder circuit 9 outputs the B-Y color difference signal at this time.

The output of the adder circuit 9 is replaced by a switch 11 which outputs a blanking level signal at a predetermined timing.
The signal is input to the latch circuit 12.13 via the latch circuit 12.13. 2.8M
Latch circuit 12 driven by the positive edge of the Hz clock
More B-Y signal.

The RY signal is outputted from the latch circuit 13 driven by the negative edge.

〔effect〕

As described above, according to the present invention, at least a part of the circuit for processing the two color difference signals BY and RY is shared, so the number of parts can be reduced.

The configuration can be simplified. Furthermore, cost reduction becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a color difference signal processing device according to the present invention. 1...1H delay circuit 2.3...Latch circuit 4...1H delay circuit 5...Latch circuit 6.7...1H delay circuit 8.9...Addition circuit 10.11...・Switch 12, 13... Latch circuit patent applicant Pioneer Corporation

Claims (1)

[Claims] A first TV signal in which a first color difference signal and a second color difference signal are inserted alternately every 1H is delayed by 1H to produce a second TV signal.
A first delay circuit that outputs a V signal, and is driven by one edge and the other edge of a first clock having a first frequency, and supplies a first TV signal and a second TV signal to the same line. a first latch circuit, a second delay circuit that delays the signal supplied to the same line by the first latch circuit by 1H, and a third delay circuit that delays the output of the second delay circuit by 1H; a first addition circuit that adds the input to the second delay circuit and the output of the third delay circuit; and the input to the second delay circuit and the output of the first addition circuit using a first clock. a switch to select; a second adder circuit that adds the output of the second delay circuit and the output of the switch; A color difference signal processing device comprising: a second latch circuit that latches at an edge of the color difference signal and separately outputs a first color difference signal and a second color difference signal.