JPH0126567B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital-to-analog conversion device for converting a digital signal into an analog signal.

[Prior art] Digital-to-analog converter (hereinafter referred to as D/A
Generally, when converting an n-bit digital input signal into a corresponding analog signal, a conversion device (abbreviated as a conversion device) uses n switch circuits to weight the conversion amount for each bit, and then The basic configuration is to add analog signals at the output stage. In such a D/A converter, several methods have been considered for weighting the conversion amount, but currently the configuration shown in Figure 1 or 2 is often used as a high-speed operation type. ing.

Here, FIG. 1 shows a current addition type D/A converter that weights the operating current value of a constant current source circuit that constitutes a switch circuit, and FIG. By connecting a resistor of R to the switch circuit for one switch circuit and a resistor of 2R to the other switch circuits, and a resistor of R between the output terminals of adjacent switch circuits, a "ladder-shaped" structure is created in which each bit is given a binary weight when viewed from the output terminal. R-2R
This is a D/A converter. In the figure, V+ is the highest power supply voltage, V- is the lowest power supply voltage, V _REF is the reference power supply voltage applied to one transistor of the differential pair that makes up the current switching circuit, A _OUT is the analog signal output terminal, and D ₁ ~D _o is a digital signal input terminal, n is the number of conversion bits, I is an operating constant current, and R is a load resistance. The operation is shown in both Figures 1 and 2 using the input terminal.
By turning on and off the differential pair of transistors that constitute the current switching circuit, depending on the "1" or "0" of each bit of the parallel digital signal (n bits) applied to D ₁ to _{D o} , Each bit is converted into a binary weighted current value, and the sum of these values is obtained from the output terminal A _OUT .

By the way, as shown in Figures 1 and 2,
Conventionally, among the differential pair transistors in the current switching circuit that make up the switch circuit, the load condition of the transistor on the side not connected to the analog output terminal A _OUT is unrelated to the weighting operation, and the number of elements is reduced. The reason for this is that a configuration in which it is directly connected to the highest potential V+ has always been used. However, the cause of glitch noise, which is a characteristic unique to D/A converters, is the delay time between switch circuits corresponding to each bit.
It is well known that this is related to differences and variations in input/output characteristics such as rise time and fall time. Therefore, in Figures 1 and 2, the unbalanced collector loads of both transistors that make up the differential pair of the current switching circuit mean that the on/off operation of each switch circuit in response to the digital input signal is This will cause a difference in the input/output characteristics of
There was a drawback that the D/A conversion operation was always accompanied by glitch noise.

[Purpose of the invention]

An object of the present invention is to reduce glitch noise, which is an inherent characteristic of a D/A converter, and
The objective is to realize high-speed D/A conversion with high accuracy.

[Summary of the invention]

The main point of the present invention is to connect the same load to the negative signal output terminal of each switch circuit in the D/A converter, or to connect a pseudo load equivalent to the load of the positive signal output terminal. The input/output characteristics of each switch circuit are made uniform by connecting them to signal output terminals, etc., and the generation of glitch noise is suppressed.

[Embodiments of the invention]

FIG. 3 shows an embodiment of the present invention, in which 1 is R-
The 2R type resistor network 2 is a switch circuit with a differential pair transistor configuration that opens and closes according to digital signal information. I is the operating constant current, V+ is the highest power supply voltage, V- is the lowest power supply voltage, A _OUT is the analog signal output terminal, and V _REF is one transistor of the differential pair that constitutes the current switching circuit in the switch circuit. The reference power supply voltage to be applied, D ₁ to _{D o} are digital signal input terminals, D ₁ is the highest bit, D ₂ is the second bit, D _o is the lowest bit, and D _o-1 is adjacent to D _o . It is one bit higher. Note that n is the number of conversion bits.

In Figure 3, R connected to output terminal A _OUT
-2R type resistor network 1 is “ladder-shaped” as shown in the figure.
This is the circuit configuration of a so-called R-2R type D/A converter, and the output current of the adjacent switch circuit 2 using the same constant current value is 2 between the upper bit and the lower bit. A one-to-one weighted result will be obtained at the output terminal A _OUT . The R-2R resistor network 1 connected to the output terminal A _OUT is used as a collector load on the side to which V _REF is input among the differential pair transistors constituting the switch circuit 2, and is a binary parallel resistor network 1. The structure is such that an analog output signal corresponding to a digital input signal can be obtained.

On the other hand, among the differential pair transistors constituting the switch circuit 2, the collector load of the transistor on the side to which the digital signal is input is also the R-
A circuit network having exactly the same configuration as the 2R type resistor network is used, and this point is different from the conventional R-2R type D/A converter shown in FIG. This measure has the effect of preventing the generation of glitch noise without affecting the direct current characteristics of the D/A conversion operation. In other words, glitch noise occurs when the outputs of several switch circuits with different input and output characteristics operate in a complementary manner, and the ideal state occurs when the input and output characteristics completely match, and glitch noise is at its minimum. becomes. Therefore, in the circuit configuration shown in FIG. 3, by completely matching the collector loads of both transistors of the differential pair constituting the switch circuit 2, the output during on/off operation according to the digital input signal can be adjusted. Since the rise time and fall time can be matched as a characteristic, differences in input and output characteristics such as delay time, rise time and fall time between each bit are eliminated, and this is a measure to improve the cause of glitch noise generation. .

FIG. 4 shows another embodiment according to the present invention, in which 1 is R-
2R type resistor network and equivalent load resistance, 2 is a switch circuit. The feature of this circuit configuration is that R-
Focusing on the fact that the load impedance at each branch point of the 2R resistor network is 2/3R, we set 2/3R as the collector load on the side that inputs the digital signal among the differential pair transistors that make up the switch circuit 2. This means that a resistive load is connected.

In the configuration shown in FIG. 4, since the collector loads of both transistors of the differential pair constituting the switch circuit 2 are extremely similar, the difference in characteristics of rise and fall times can be reduced. Therefore, similar to the circuit configuration shown in FIG. 3, this can be a very effective measure to prevent glitch noise from occurring.

Figures 3 and 4 show the case of the R-2R type D/A converter, but the current addition type D/A converter shown in Figure 1
In the circuit configuration of the converter, the analog signal output terminal is commonly connected to the collector of the differential pair transistors of the switch circuits for each bit on the side to which the reference voltage is input. Further, an external load is connected to this analog signal output terminal and used when extracting an analog signal. Therefore, by connecting an equivalent circuit with the same conditions as this load as the collector load on the side to which the digital signal is input of the differential pair transistors constituting the switch circuit, the results shown in FIGS.
The same effect of suppressing glitch noise generation as explained with the D/A converter shown in the figure can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, D/
By setting the collector loads of both differential pair transistors constituting the switch circuit corresponding to each bit of the A converter to the same condition, the output characteristics of the rise time and fall time of the switch circuit can be made equal, and each switch It is possible to prevent unnecessary glitch noise from occurring when adding up the outputs of the circuit. This reduction in glitch noise increases the accuracy of the D/A converter and results in an increase in conversion speed. Furthermore, according to the present invention, it can be used alone as a high-performance D/A converter without using a glitch noise removal circuit or a sample-and-hold circuit, so it is advantageous for economicalization, and the effect is extremely large. I can say it.

[Brief explanation of drawings]

Fig. 1 is a basic circuit diagram of a conventional current addition type D/A converter, Fig. 2 is a basic circuit diagram of a conventional R-2R type D/A converter, and Figs. 3 and 4 are according to the present invention. FIG. 2 is a diagram showing an embodiment of an R-2R type D/A converter. 1...R-2R type resistor network, 2...Switch circuit, _D1 to D _o ...Digital signal input terminal,
A _OUT ...Analog signal output terminal, V _REF ...Reference voltage input terminal, V+...Highest power supply voltage, V-...
Lowest power supply voltage, I... Constant operating current, R... Resistor.

Claims (1)

[Claims] 1. It has n switch circuits and n current sources corresponding to n-bit digital input signals applied in parallel, and each switch circuit is constituted by a differential pair element. By applying a digital input signal to one gate terminal of the dynamic pair element and a reference voltage to the other gate terminal, one output terminal of each differential pair element receives a weighted signal corresponding to each bit. In a digital-to-analog conversion device that obtains a level output, synthesizes the level output, and outputs an analog signal corresponding to a digital input signal, a differential pair element constituting each of the switch circuits has a side that outputs the analog signal. 1. A digital-to-analog conversion device, characterized in that a load having the same load condition or equivalently the same load condition as the load of the analog signal output terminal is added to the other output terminal corresponding to the output terminal.