JPH01265577A - Josephson field effect transistor - Google Patents

Abstract

PURPOSE:To make a superconductive critical current small so as to render an ON-OFF ratio small by a method wherein at least one or more semiconductor hetero-structures are provided to a Josephson field effect transistor. CONSTITUTION:A superconductor electrode 102 and a gate electrode 103 are formed on a barrier layer 104. The barrier layer 104 is formed of a semiconductor whose band gap is larger than that of a well layer 105. A hetero-junction is formed at the interface between the barrier layer 104 and the well layer 105. Impurity, which is to serve as a donor or a acceptor, is doped to the barrier layer 104 more than the well layer 105 in concentration. Carriers generated from donors or acceptors inside the ionized barrier layer 104 are made to move to the well layer 105 side and change into a two-dimensional electron gas. The two-dimensional electron gas is high in mobility independently of a Coulomb scattering. By these processes, a superconductive critical current grows small and an ON-OFF ratio becomes small.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a Josephson field effect transistor (hereinafter referred to as JO
(denoted as FET).

[Prior Art] Since the concept of the JOFET was proposed in the early 1970s, research has been progressing on the JOFET, attracting attention for its high speed and simple circuit configuration. The conceptual diagram is shown in Fig. 2. FIG. 4(a) is a conceptual diagram of the OFF state, and FIG. 6(b) is a conceptual diagram of the ON state. 201 is a semiconductor, 102 is a superconductor electrode, 202
is a region where electron pairs called Cooper pairs seep out from the superconductor electrode 102, and the distance from the edge of this region to 102 is called the coherence length (ξ). semiconductor 20
When the carrier concentration in 1 is small, ξ is small, and the same figure (
As shown in (a), the pair of Coopers do not overlap in the semiconductor 201, but when the carrier concentration is large, ξ increases, and as shown in (b) of the same figure, the pair of Coopers overlaps in the semiconductor 201, and the left and right superconductors A superconducting current flows between the electrodes 102. A JOFET controls the carrier concentration in this semiconductor by the potential applied to the gate.

The conventional JOFET was developed by Kawabe et al. (Solid State Physics V.

1.22 1987. As shown in p. 117), etc.
There was only one layer of semiconductor that connected the superconductor electrodes.

[Problem 1 to be solved by the invention However, the conventional JOFET has a problem that the superconducting critical current Ic is small and the oNZOFF ratio of JoFEi itself is small.

The present invention is intended to solve the above problems, and its purpose is to provide a JOFE with a large IC and 0N10FF ratio.
The goal is to realize T.

[Means for Solving the Problems] In order to solve the above problems, the JOFET of the present invention is characterized by having at least one semiconductor heterostructure.

[Example] Figure 1 shows a Peter structure JOFE in an example of the present invention.
A cross-sectional view of T is shown. In the figure, 101 is an arbitrary substrate, 102 is a superconductor electrode, 103 is a gate electrode, and 104 is a superconductor electrode.
is a semiconductor thin film (barrier layer), and 105 is a semiconductor thin film 1! (well layer). A semiconductor having a larger band gap than the well layer 105 is used for the barrier layer 104, and 104 and 10
A heterojunction is formed at the interface of 5. In addition, barrier layer 1
Impurities serving as donors or acceptors are added to the well layer 105 at a higher concentration than the well layer 105 (modulation doping). Similar to the principle of a high mobility transistor (HEMT), carriers generated from ionized donors or acceptors in the barrier layer 104 move to the well layer 105 side and become a two-dimensional electron gas. This two-dimensional electron gas has high mobility because it is not subjected to Coulomb scattering by ionized donors or acceptors in the barrier NlO4. Further, by increasing the impurity concentration added to the barrier layer 104, the carrier concentration of the two-dimensional electron gas can be increased. Takayanagi et al. (Solid State Physics Vol. 1.20 198
5. p, 939), ξ of a two-dimensional electron gas is blank constant h, carrier mobility μ, surface carrier concentration Ns, Boltzmann constant k, temperature T, and charge arrangement e.
, where mo is the effective mass of the carrier, it is expressed by the following equation.

ξ= (b"μNs/2kTem") 1'2 Also, according to Hiraki et al. (Proceedings of the 48th Japan Society of Applied Physics Academic Conference, Fall 1987, Proceedings 19a-H-3), the IC has a channel length (
superconductor layer [102 spacing], superconducting critical temperature T
c, the scale song coefficient is 01, C2=L/2ξ, t
If = T / T c, it is expressed by the following formula.

From the above two equations, it can be seen that the heterostructure JOFET of the present invention, which allows large μ and Ns, has a larger IC than the conventional JOFET.

For example, the substrate 101 has a semi-insulating (S, 1.)G
aAs, the superconductor electrode 102 is made of TclOOK class material, which has been actively developed in recent years, and the Tc of this system is also 10.
0, the barrier N104 is GaAlAs, the well layer 105 is
When GaAs is used for , and L=0.degree. 2 .mu.m, Ic=20 .mu.A is calculated at T=77. As a result,
JOFET that did not operate at conventional nitrogen temperature (77K)
However, by using the present invention, the possibility of operation at nitrogen temperatures has been shown. It is considered that it would be even more advantageous to use a heterostructure such as InAs, which has a larger μ and a smaller m″ than GaAs.

FIG. 3 shows MISS (Met
al-■nsulator-3emic.

conductor-3emiconductor) structure J
A cross-sectional view of an OFET is shown. In this figure, the same symbols as in FIG. 1 represent the same things as in FIG. 1.

301 is an insulating film made of SiO2, A1203, or the like. The operating principle is the same as that of the heterostructure JOFET shown in FIG. 1, and utilizes the fact that the two-dimensional electron gas generated at the interface with the barrier layer 104 of the well N105 has high mobility and high carrier concentration. In the structure of this embodiment, compared to the embodiment in FIG.
It is possible to improve the F ratio.

FIG. 4 shows a double heterostructure J in an embodiment of the present invention.
A cross-sectional view of an OFET is shown. In this figure, the same symbols as in FIG. 1 represent the same things as in FIG. 1.

In this embodiment, barriers W are provided above and below the well Jli105.
1104 is provided. With this kind of structure, it will be well J!
Two-dimensional electron gas is formed at the upper and lower interfaces of 105, and Ic becomes even larger.

FIG. 5 shows a superlattice structure JOFE in an embodiment of the present invention.
A cross-sectional view of T is shown. In the figure, the same symbols as in FIGS. 1 and 3 represent the same things as in FIGS. 1 and 3. By forming the semiconductor into a superlattice structure, the effective carrier concentration can be further increased. In addition, in the structure of this example, since the superconductor electrode 102 exists on the wall surface of the semiconductor superlattice layer, ξ with respect to the potential applied to the gate electrode 103
It is only necessary to consider the change in the direction between the superconductor electrodes, and since the superconductor electrode 102 is also in direct contact with the well layer 105, the IC becomes larger. In such a structure, after forming and patterning a semiconductor superlattice layer, a superconductor thin film is formed and the superconductor thin film on the semiconductor superlattice layer is removed by a lift-off method or the like, and then the gate insulating film 301 and the gate electrode 103 are formed. All you have to do is form. Furthermore, if the period of the semiconductor superlattice is shortened, not only will IC be improved when a single crystal semiconductor is used, but it is also possible that a JOFET using a non-single crystal semiconductor will be realized. This has great significance for the future of JOFET.

FIG. 6 shows a cross-sectional view of a superlattice structure JOFET in which the gate electrode is on the substrate side in an embodiment of the present invention. In this figure, the same symbols as in FIG. 1 represent the same things as in FIG. 1.

The advantage of this embodiment is that L can be controlled only by the patterning accuracy of the superconductor thin film, and it is effective for forming a superlattice structure JOFET with L of submicrons.

[Effects of the Invention] As described above, by using the present invention, a JOFET with a thick IC (a large ON10FF ratio) was realized.

[Brief explanation of the drawing]

FIG. 1 shows a heterostructure FF state 1 in an embodiment of the present invention. Figure (b) is a conceptual diagram of the ON state. FIG. 3 shows the MISS structure JOF in the embodiment of the present invention.
A cross-sectional view of ET. FIG. 4 shows a double heterostructure J in an embodiment of the present invention.
Cross-sectional view of OFET. FIG. 5 shows a superlattice structure JOFE in an embodiment of the present invention.
A cross-sectional view of T. FIG. 6 is a cross-sectional view of a superlattice structure JOFET in which the gate xi is on the substrate side in an embodiment of the present invention. 101... Any substrate 102... Superconductor electrode 103... Gate electrode 104... Semiconductor thin film (barrier layer) 105... Semiconductor thin film (well layer) Applicant Agent for Seiko Epson Corporation Patent attorney Masayoshi Kamiyanagi (1 other person) 101... Arbitrary substrate 102... Superconductor electrode 103... Gate electrode 104... Semiconductor thin film (barrier layer) 105... Semiconductor thin film (well layer) Figure 1 (a) Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A Josephson field effect transistor having at least one semiconductor heterostructure.