JPH01265576A - Ceramic superconductive transistor - Google Patents

Ceramic superconductive transistor

Info

Publication number
JPH01265576A
JPH01265576A JP63093842A JP9384288A JPH01265576A JP H01265576 A JPH01265576 A JP H01265576A JP 63093842 A JP63093842 A JP 63093842A JP 9384288 A JP9384288 A JP 9384288A JP H01265576 A JPH01265576 A JP H01265576A
Authority
JP
Japan
Prior art keywords
superconducting
ceramic
transistor
semiconductor
superconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63093842A
Other languages
Japanese (ja)
Inventor
Noboru Ebara
江原 襄
Terue Kataoka
照榮 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP63093842A priority Critical patent/JPH01265576A/en
Publication of JPH01265576A publication Critical patent/JPH01265576A/en
Pending legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To obtain an excellent superconductive transistor by a method wherein a semiconductor layer, which is formed at the grain boundary of a ceramic superconductor through a heat treatment, is interposed between the superconductors at an extremely small space, and the transistor is controlled in characteristics through the kind and the amount of additive elements. CONSTITUTION:A semiconductor channel extremely short in length consists of the thickness of a semiconductor ceramic particle interface separated at a grain boundary 3 of a ceramic superconductor particle 4, where the semiconductor channel denotes the channel of a field effect ceramic superconductive transistor. The grain boundary 3 is separated off when a crystal grain between the interfaces 3 is made to grow, and the interface 3 is made not to be superconductive but semiconductive in a compositional ratio and controlled in a semiconductivity by mixing 1% or so of an additive such as SiO2 or Bi2O3 other the composition of a superconductor and making it separate off at the particle interface. The property is controlled through the kind and the amount of an additive element. By these processes, an excellent superconductive transistor can be obtained.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 を介在させ粒界の導電度を制御するセラミック超電導ト
ランジスタに関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a ceramic superconducting transistor in which the conductivity of grain boundaries is controlled by intervening grain boundaries.

〈従来の技術〉 超高速動作の特徴をもつ超電導素子に、増幅特性をもた
せる超電導トランジスタの開発が行なわれている。開発
されている超電導トランジスタは、超電導体とSi又は
InAsなどの半導体との接合を設け、超電導電子の近
接効果による拡がりを半導体中のキャリヤ濃度を高くし
て拡大する電界効果型トランジスタ、又は超電導ベース
により、ベース抵抗減少で高速度化をはかるバイポーラ
トランジスタなどがあった。
<Prior Art> Superconducting transistors are being developed to provide amplification characteristics to superconducting elements that are characterized by ultra-high-speed operation. The developed superconducting transistors are field-effect transistors, or superconducting base transistors, in which a junction is created between a superconductor and a semiconductor such as Si or InAs, and the spread of superconducting electrons due to the proximity effect is increased by increasing the carrier concentration in the semiconductor. As a result, there were bipolar transistors that achieved higher speed by reducing base resistance.

〈発明が解決しようとする問題点〉 従来のトランジスタは、Si、又は、InAsなどの半
導体と接合を作るため、超電導体にNb又は、その化合
物などが用いられ、その臨界温度Tcは20に以下であ
り、液体ヘリウムで冷却していた。又、電界効果型トラ
ンジスタを作製するときは、液体ヘリウム温度に於いて
もSiなどのチャンネル長はμm以下になシ、高度な製
造技術が必要になっていた。
<Problems to be solved by the invention> In conventional transistors, Nb or a compound thereof is used as a superconductor to form a junction with a semiconductor such as Si or InAs, and its critical temperature Tc is below 20°C. It was cooled with liquid helium. Furthermore, when manufacturing a field effect transistor, the channel length of Si or the like must be less than .mu.m even at liquid helium temperatures, which requires advanced manufacturing technology.

更に、上記の極低温の液体ヘリウム冷却をさけ、セラミ
ック超電導体を使用する超電導体トランジスタにすると
、そのコヒーレント長はnm以下であり、チャンネル長
も10nm程度という極めて短いものになシ、至難な技
術を要求されることになる。更に、セラミック超電導体
と、従来のSi又は、I nAsなどとの接合作成技術
が確立されていないという問題も残っている。
Furthermore, if we avoid the cryogenic liquid helium cooling described above and create a superconductor transistor using a ceramic superconductor, its coherence length is less than nm, and the channel length is extremely short, about 10 nm, which is an extremely difficult technology. will be required. Furthermore, there remains the problem that a technique for forming a bond between a ceramic superconductor and conventional Si or InAs has not been established.

本発明は、上記の超電導トランジスタがもつ問題点を解
消し、櫃端な精密加工の必要がなく取扱も比較的容易な
セラミック超電導トランジスタを提供するものである。
The present invention solves the problems of the above-mentioned superconducting transistors, and provides a ceramic superconducting transistor that does not require extensive precision processing and is relatively easy to handle.

〈問題点を解決するための手段〉 本発明の目的を達成させるため、超電導体としてTcの
高いセラミック超電導体を用いその超電導粒子間に形成
される粒界に半導体特性をもたせるものである。又、上
記半導体粒界の厚さは、そこに超電導粒子から近接効果
で浸み出す超電導電子を制御用のゲート電極の電圧によ
フ拡げて粒界にその超電導体電子のチャンネルを形成で
きる長さにしている。゛ セラミック超電導体は、均一な超電導体になるよう作製
しても、焼成などの工程後は超電導結晶粒子のまわりに
粒界が形成される。超電導粒子の1わりに半導体粒界を
形成するときも、超電導体原料に添加する元素及びその
量と焼成条件を調整することにより、粒界の半導体特性
と、その厚さを制御することができるので、その調整に
より前記の特性をもつ半導体粒界をもつ超電導体にする
ことができる。
<Means for Solving the Problems> In order to achieve the object of the present invention, a ceramic superconductor with a high Tc is used as the superconductor, and the grain boundaries formed between the superconducting particles are given semiconductor characteristics. In addition, the thickness of the semiconductor grain boundary is set to a length that allows superconducting electrons leaking from the superconducting particles due to the proximity effect to be spread by the voltage of the control gate electrode to form a channel for the superconducting electrons at the grain boundary. I'm looking at it. ``Even if a ceramic superconductor is manufactured to be a uniform superconductor, grain boundaries are formed around superconducting crystal grains after steps such as firing. When forming semiconductor grain boundaries instead of superconducting particles, the semiconductor properties of the grain boundaries and their thickness can be controlled by adjusting the elements added to the superconductor raw material, their amounts, and the firing conditions. By adjusting the superconductor, a superconductor having semiconductor grain boundaries having the above-mentioned characteristics can be obtained.

以上の超電導体に適当な間隔でソー7とドレーン電極を
設け、その間を制御するゲーム電極を設けることにより
、電界効果超電導トランジスタを形成することができる
A field effect superconducting transistor can be formed by providing the above superconductor with a saw 7 and a drain electrode at appropriate intervals, and providing a game electrode for controlling the gap therebetween.

〈作 用〉 電界効果型セラミック超電導トランジスタの極めて短い
半導体チャンネル長を、七ラミック超電導体粒子の粒界
に析出させる半導体セラミック粒界の厚さで構成するも
ので、セラミック超電導体の原料に添加する元素の種類
と量、その焼成条件により、その半導体粒界の厚さと特
性を制御することができる。
<Function> The extremely short semiconductor channel length of the field-effect ceramic superconducting transistor is made up of the thickness of the semiconductor ceramic grain boundaries that are precipitated at the grain boundaries of the heptalamic superconductor particles, and it is added to the raw material of the ceramic superconductor. The thickness and characteristics of the semiconductor grain boundaries can be controlled by the type and amount of elements and firing conditions.

従って、特別な精密技術を用いることなく、極めて短い
半導体チャンネル長のセラミック超電導トランジスタに
することができる。
Therefore, a ceramic superconducting transistor with an extremely short semiconductor channel length can be obtained without using any special precision technology.

く実施例〉 本発明の実施例を図面を参照して説明する。Example Embodiments of the present invention will be described with reference to the drawings.

第1図は本発明を電界効果型超電導トランジスタ9に適
用ときの概要構成断面図であり、このトランジスタ9の
正面図が第2図である。
FIG. 1 is a schematic cross-sectional view of the structure when the present invention is applied to a field-effect superconducting transistor 9, and FIG. 2 is a front view of this transistor 9.

トランジスタ9は、面積が10  XIOで、厚す0.
5  のn型シリコン(Si)単結晶基板1の表面にス
パッタリングで約100^の安定化ジルコニア(YSZ
)膜2を作製した。
Transistor 9 has an area of 10XIO and a thickness of 0.
Stabilized zirconia (YSZ) of approximately 100^ is deposited on the surface of an n-type silicon (Si) single crystal substrate 1 of
) Membrane 2 was produced.

一方、構成元素の硝酸塩などを還元する共沈法で合成し
たY B a 2 Cu30y−aの微粉末を溶剤など
でペースト状にし、前記の基板1の中央部に、厚さ約1
μm、幅0.5ffで長さ約10ff塗布した。
On the other hand, a fine powder of YB a 2 Cu30y-a synthesized by a coprecipitation method that reduces the constituent elements such as nitrates is made into a paste with a solvent etc., and it is placed in the center of the substrate 1 to a thickness of about 1 mm.
The film was coated with a width of 0.5 ff and a length of about 10 ff.

塗布後は約200℃の低温で溶剤をとばした上、空気中
で930°07時間の焼成を行い、焼成後は380℃で
4時間保持する温度制御も含めて徐冷を行った。
After coating, the solvent was evaporated at a low temperature of about 200°C, and then baked in air at 930°C for 7 hours. After baking, slow cooling was performed, including temperature control at 380°C for 4 hours.

セラミック高温超電導体を焼成法で作製すると、超電導
粒子と、その粒子を囲む粒界が形成される。
When a ceramic high-temperature superconductor is produced by a firing method, superconducting particles and grain boundaries surrounding the particles are formed.

この粒界はそのなかの結果粒子が成長するとき析出され
超電導性でなく半導体性の組成比にするか超電導体の組
成以外の添加元素、例えば5i02又は、雲1203を
1例程度混入して粒界に析出させ、半導体特性を制御す
ることができる。添加元素の5i02に微量のMnを添
加しておいてもよい。
These grain boundaries are precipitated when the grains grow, and either the composition ratio is changed to semiconducting rather than superconducting, or an additional element other than the superconducting composition, such as 5i02 or cloud 1203, is mixed into the grain. It is possible to control semiconductor properties by precipitating in a field. A trace amount of Mn may be added to the additive element 5i02.

以上のように、セラミック超電導体の作製条件と添加元
素の種類やその量、又は超電導体を構成する元素の組成
比を変化することで、粒界の厚さ又は、その特性を制御
することができる。
As described above, it is possible to control the thickness of grain boundaries or their characteristics by changing the manufacturing conditions of ceramic superconductors, the type and amount of added elements, or the composition ratio of elements constituting the superconductor. can.

本実施例の方法により作製したYBa2Cu307−δ
を走査型トンネル電子顕微鏡(STM)で計測した1例
が第5図である。
YBa2Cu307-δ produced by the method of this example
FIG. 5 shows an example of measurement using a scanning tunneling electron microscope (STM).

この図は、鏡面研磨したサンプルの表面からトンネ/I
/電流100 pAを保つようフィードバック電圧で制
御して走査したマツプである。
This figure shows tunnel/I from the surface of a mirror-polished sample.
This is a map scanned under control using a feedback voltage to maintain a current of 100 pA.

第5図の曲線の高低はサンプルの局所的な抵抗値に対応
している。図のAは超電導を示す領域であり、Bの領域
は室温に於ける抵抗値がA領域より約3桁大きい半導体
特性をもった領域であり、Cの粒界部もB領域とほぼ同
じ半導体であることが判明した。
The height of the curve in FIG. 5 corresponds to the local resistance value of the sample. In the figure, A is a region that exhibits superconductivity, and region B is a region with semiconductor characteristics whose resistance value at room temperature is about three orders of magnitude higher than that of region A, and the grain boundary region of C is a semiconductor that is almost the same as region B. It turned out to be.

作製した超電導膜は第1図に示したように厚さが約1μ
m程度で厚さ方向は1個の結晶粒子から構成され、又、
その結晶粒子の横方向の粒径も膜厚とはソ同じであり、
かつ隣接する粒子とは、外部からの制御電圧の印加によ
り、超電導電子による電流を流すことができる約10n
mの厚さの半導性で粒界を介して接続していた。
The fabricated superconducting film has a thickness of approximately 1μ as shown in Figure 1.
It is composed of one crystal grain in the thickness direction, and
The grain size in the lateral direction of the crystal grains is also the same as the film thickness,
And the adjacent particles are approximately 10nm, which allows current to flow due to superconducting electrons by applying a control voltage from the outside.
They were connected through grain boundaries with a semiconducting layer having a thickness of m.

作製した超電導膜は、その中央部にチャンネル8になる
約50μmを除き金(Au )の蒸着で、ソース電極5
−とトレイン電極5′を形成した。以上のように形成し
た電極の上にCVDなどによりシリコン酸化膜、又は、
シリコン窒化膜の絶縁膜6で覆い更にアルミニウム(A
Ij)のシールド電極7を蒸着してトランジスタ9を作
製した。
The fabricated superconducting film has a source electrode 5 formed by vapor deposition of gold (Au) in the center except for the approximately 50 μm area that will become the channel 8.
- and a train electrode 5' were formed. A silicon oxide film is formed by CVD or the like on the electrode formed as above, or
It is covered with an insulating film 6 of silicon nitride film and further covered with aluminum (A
A transistor 9 was fabricated by depositing the shield electrode 7 of Ij).

作製した超電導トランジスタ9は、第3図の構成の測定
回路で測定した。図で超電導トランジスタ9を臨界温度
Tc以下に保つため、液体窒素LNの入ったデユア−瓶
10の中へ入れ77Kに保った。ゲート電極になるシリ
コン基板に2vまでの可変電圧源VGを接続し、ソース
電極5とドレーン電[5’ にはそれぞれ−2vと+2
Vの電源を接続した。
The manufactured superconducting transistor 9 was measured using a measuring circuit having the configuration shown in FIG. In the figure, in order to keep the superconducting transistor 9 below the critical temperature Tc, it was placed in a dual bottle 10 containing liquid nitrogen LN and maintained at 77K. A variable voltage source VG up to 2V is connected to the silicon substrate that will become the gate electrode, and -2V and +2V are applied to the source electrode 5 and drain voltage [5', respectively.
V power supply was connected.

以上の測定回路で得た特性は第4図のようになった。図
から明らかなように、超電導体トランジスタ9は、ゲー
ト電圧により、そのチャンネルを流れる電流を制御する
トランジスタ動作を示した。
The characteristics obtained with the above measurement circuit are as shown in FIG. As is clear from the figure, the superconducting transistor 9 exhibited transistor operation in which the current flowing through its channel was controlled by the gate voltage.

第4図では、ゲート電圧を印加しない0のときドレイン
電流が約200μAとなり、常温での抵抗値許算と異な
るが、これは低温での半導性粒界の導電度の低下、実効
導電膜厚が薄いこと、及び半導性粒界と超電導結晶の間
のエネルギーギャップなどの影響によるものと考えられ
る。
In Figure 4, when the gate voltage is not applied and the drain current is 0, the drain current is approximately 200 μA, which is different from the resistance value tolerance at room temperature. This is thought to be due to the thin thickness and the energy gap between the semiconducting grain boundary and the superconducting crystal.

以上の実施例の特性は、本超電導トランジスタの超電導
膜の元素組成、及び、その作製方法の改良により、その
特性、制菌性など改善できると考える。又、超電導膜な
どの微細加工の技術を確立して、高密度の集積化も可能
な実用的超電導トランジスタにすることができる。
It is believed that the characteristics, antibacterial properties, etc. of the above embodiments can be improved by improving the elemental composition of the superconducting film of the present superconducting transistor and its manufacturing method. In addition, by establishing microfabrication technology for superconducting films, it is possible to create practical superconducting transistors that can be integrated at high density.

〈発明の効果〉 本発明の超電導体トランジスタは、超電導体の間に極め
て微小な間隔で介在させるべき半導体層を、セラミック
超電導体の粒界に熱処理などで析出し形成した半導体層
を使用するものである。この析出して形成する半導体層
の密度、厚さ及び半導体としての特性は、その作製条件
又は、その超電導体に添加した異種元素の数や量で制御
することができる。
<Effects of the Invention> The superconducting transistor of the present invention uses a semiconductor layer that is formed by depositing a semiconductor layer, which should be interposed between superconductors at extremely small intervals, at the grain boundaries of a ceramic superconductor by heat treatment or the like. It is. The density, thickness, and semiconductor properties of the semiconductor layer formed by precipitation can be controlled by the manufacturing conditions or the number and amount of different elements added to the superconductor.

従って、極端な精密加工技術を用いることなく超高速で
動作し、かつ、増幅特性をもつことができる超電導トラ
ンジスタを構成することができる。
Therefore, it is possible to construct a superconducting transistor that operates at ultra high speed and has amplification characteristics without using extreme precision processing techniques.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のセラミック超電導トランジスタの概要
断面図、第2図は本発明の実施例の正面図、第3図はそ
の測定回路図、第4図はその超電導トランジスタの特性
図、第5図は超電導セラミック表面のSTMによる抵抗
値分布測定図である。 1はシリコン基板、 2はysz、@縁膜、 3は粒界
、 4は超電導結晶粒子、 5と5′はソースとドレイ
ン電極、 6は絶、縁膜、 7はシールド電極、 8は
チャンネル、 9は超電導トランジスタである。 代理人 弁理士  杉 山 毅 至(他1名)碍号 2
  図 セラ三−274@導トランジス90槙パ父ゝ9
声優93車トランジスタ 第3g 測定回路 n
Fig. 1 is a schematic sectional view of a ceramic superconducting transistor of the present invention, Fig. 2 is a front view of an embodiment of the present invention, Fig. 3 is a measurement circuit diagram thereof, Fig. 4 is a characteristic diagram of the superconducting transistor, and Fig. 5 The figure is a diagram showing resistance value distribution measured by STM on the surface of a superconducting ceramic. 1 is silicon substrate, 2 is ysz, @edge film, 3 is grain boundary, 4 is superconducting crystal grain, 5 and 5' are source and drain electrodes, 6 is insulation, edge film, 7 is shield electrode, 8 is channel, 9 is a superconducting transistor. Agent: Patent attorney Takeshi Sugiyama (and 1 other person), number 2
Figure Cera 3-274 @ conductor transistor 90 Makipa father 9
Voice actor 93 car transistor 3g measurement circuit n

Claims (1)

【特許請求の範囲】 1、超電導セラミック粒子の粒界を半導体セラミックで
構成し、前記半導体セラミック粒界への超電導電子の拡
がりを制御することを特徴とするセラミック超電導トラ
ンジスタ。 2、前記セラミック超電導粒子の間の半導体セラミック
粒界層が、そのセラミック超電粒界での超電導電子のコ
ヒーレント長の、少なくとも2倍以上の厚さをもつこと
を特徴とする請求項1記載のセラミック超電導トランジ
スタ。 3、前記超電導トランジスタを構成する粒界をもった超
電導体層の厚さは、前記セラミック超電導粒子の粒径程
度にしたことを特徴とする請求項1、又は、2記載のセ
ラミック超電導トランジスタ。
[Scope of Claims] 1. A ceramic superconducting transistor characterized in that the grain boundaries of superconducting ceramic particles are made of semiconductor ceramic, and the spread of superconducting electrons to the semiconductor ceramic grain boundaries is controlled. 2. The semiconductor ceramic grain boundary layer between the ceramic superconducting particles has a thickness that is at least twice the coherent length of superconducting electrons at the ceramic superconducting grain boundaries. Ceramic superconducting transistor. 3. The ceramic superconducting transistor according to claim 1 or 2, wherein the thickness of the superconducting layer having grain boundaries constituting the superconducting transistor is approximately equal to the grain size of the ceramic superconducting particles.
JP63093842A 1988-04-15 1988-04-15 Ceramic superconductive transistor Pending JPH01265576A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63093842A JPH01265576A (en) 1988-04-15 1988-04-15 Ceramic superconductive transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63093842A JPH01265576A (en) 1988-04-15 1988-04-15 Ceramic superconductive transistor

Publications (1)

Publication Number Publication Date
JPH01265576A true JPH01265576A (en) 1989-10-23

Family

ID=14093652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63093842A Pending JPH01265576A (en) 1988-04-15 1988-04-15 Ceramic superconductive transistor

Country Status (1)

Country Link
JP (1) JPH01265576A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2666175A1 (en) * 1990-08-21 1992-02-28 Thomson Csf SUPERCONDUCTING FIELD EFFECT TRANSISTOR.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2666175A1 (en) * 1990-08-21 1992-02-28 Thomson Csf SUPERCONDUCTING FIELD EFFECT TRANSISTOR.

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