JPH01264012A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain pull-up or pull-down of a potential of a signal line to an object potential within a specified time by connecting a gate of a MOSFET directly and a source thereof via a resistor to a power terminal or a ground terminal and connecting a drain to a signal terminal subject to pull-up or pull- down. CONSTITUTION:When MOSFETs 14, 15 are both nonconductive, a current flowing to a resistor 11 is zero and a voltage drop across the resistor 11 is lost, then the potential difference between the gate and source of a MOSFET 12 is zero, that is, the MOSFET 12 is conductive. As a result, the level of the signal terminal 13 is pulled up to the power potential. Since the impedance between the signal terminal 13 and the power terminal 17 is the resistance of the resistor 11 by decreasing the conduction resistance of the MOSFET 12 in this case since the MOSFET 12 is conductive and the potential change at the signal terminal 13 is according to the CR time constant consisting of the resistor 11 and the parasitic capacitance. Thus, the potential of the signal line is pulled up or down.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a circuit that pulls up or pulls down a signal terminal within a semiconductor integrated device.

[Conventional technology]

Conventionally, this type of pull-up/pull-down circuit has been constructed by connecting one end of a constant resistor 26, 30 of several kilo ohms to several hundred kilo ohms to the gate circuit 28, 32, and connecting the other end to the gate circuit 28, 32, as shown in FIGS. It was configured to be connected to a power source.

[Problem to be solved by the invention]

The conventional pull-up and pull-down circuits described above are composed of constant resistors, so if the resistance value of the resistor is as low as several kilohms, the current flowing through the resistor is large, and multiple When resistors are connected in parallel, the combined resistance of these resistors becomes small and a large current may flow in the signal bus.In addition, in CMO8 semiconductor integrated devices, power supply leakage current occurs during DC testing. The disadvantage is that it cannot be measured accurately.

Also, if the resistance value of the resistor is high, from tens of kilohms to hundreds of kilohms, the OR time constant will become large, and the potential of the signal line such as the signal bus may not be pulled up or down to the target potential within the specified time. There is a drawback.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes one resistor and one MO
The gate of the MOSFET is connected directly, the source is connected to a power supply terminal or a ground terminal via a resistor, and the drain is connected to a signal terminal of a gate circuit to be pulled up or pulled down in a semiconductor integrated device. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1 and 2 are circuit diagrams showing embodiments of a pull-up circuit and a pull-down circuit according to the present invention, respectively, and FIGS. 3 and 4 are circuit diagrams showing the pull-up circuit and pull-down circuit shown in FIGS. 1 and 2, respectively. FIG. 2 is a circuit diagram of a specific embodiment of the circuit for a CMO8 semiconductor integrated circuit.

In Figure 3, MOSFET 12 is a depletion type P
It is a channel MO3FET, and the resistor 11 has a resistance value such that when the potential of the signal terminal 13 becomes 0, the MO8FET 12 becomes a non-conducting state, that is, a high resistance state.

First, when the P-channel MOSFET 14 is in a conductive state and the N-channel MOSFET 15 is in a non-conductive state, the signal terminal 13 and the power supply terminal 17 are at the same potential, so the MOSFE
Even though T12 is in a conductive state, no current flows between the source and drain.

Next, MOSFET 14 is in a non-conducting state, MOSFET 1
5 becomes conductive, as the potential of the signal terminal 13 decreases, the current flowing between the source and drain of the MOSFET 12 tends to increase, but due to the voltage effect of the resistor 11, the source potential of the MOSFET 12 decreases to the gate potential. Therefore, the current flowing through the resistor 11 and the MOSFET 12 does not increase because the source and drain of the MO8FET 12 are in a high impedance state, that is, the power supply terminal 17 and the signal terminal 13 are in a high impedance state. At this time,
Since the power supply terminal 17 and the signal terminal 130 are in a high impedance state, a transient change in the potential of the signal terminal 13 is caused by
The OR time constant determined by the source-drain resistance and parasitic capacitance of MOSFET 15 is followed.

Furthermore, MOSFET15 is in a non-conducting state, MOSFET1
When MOSFET 4 becomes conductive, MOSFET 12 operates in the opposite manner to the above case and becomes conductive. However, since the potential difference between the source and drain of MOSFET 12 becomes smaller, the current flowing through resistor 11 and MOSFET 12 does not increase. At this time, since the resistor 11 is inserted between the source of the MOSFET 12 and the power supply terminal 17,
The impedance between the power supply terminal 17 and the signal terminal 13 is M
Equal to the resistance between the source and drain of OSFET14,
Therefore, the potential change of the signal terminal 13 follows an OR time constant determined from the source-drain resistance and parasitic capacitance of the MOSFET 14.

Furthermore, when both MOSFETs 14 and 15 become non-conductive, the current flowing through the resistor 11 becomes O, and the voltage drop due to the resistor 11 disappears, so the potential difference between the gate and source of the MOSFET 12 becomes 0, that is, the MOSFET 12 becomes conductive. . As a result, the signal terminal 13 is pulled up to the power supply potential. In this case, since the MOSFET 12 is in a conductive state, the impedance between the signal terminal 13 and the power supply terminal 17 becomes the resistance value of the resistor 11 by reducing the conduction resistance of the MOSFET 12, and as a result, the potential change of the signal terminal 13 is The OR time constant determined by the resistor 11 and parasitic capacitance is followed.

In the case of FIG. 4, the same operation as that of FIG. 3 is performed.

〔Effect of the invention〕

As explained above, in the present invention, the gate of the MOSFET is connected directly, the source is connected to the power supply terminal or the ground terminal via a resistor, and the drain is connected to the signal terminal to be pulled up or pulled down. Since the impedance between the signal terminal and the power supply terminal or the ground terminal when a signal is applied is the same as the impedance when the MOSFET and resistor of the present invention are not connected, the transient change in the potential of the signal terminal is The effect is the same as when there is no pull-up circuit or pull-down circuit according to the present invention.

Furthermore, when no signal is applied to the signal terminal and the signal terminal is pulled up or pulled down, the impedance between the signal terminal and the 1i source terminal or ground terminal is equal to the resistance of the resistor used in the present invention. By selecting a sufficiently small resistance value, the CR time constant of the signal terminal can be reduced.

Furthermore, the present invention has the effect that when the current flowing through the pull-up circuit or pull-down circuit attempts to increase, the impedance of the pull-up circuit or pull-down circuit is set to a high impedance state, so that a large current does not flow.

[Brief explanation of the drawing]

FIGS. 1 and 2 are circuit diagrams of embodiments of a pull-up circuit and a pull-down circuit according to the present invention, respectively, and FIGS. 3 and 4 are circuit diagrams of the pull-up circuit and pull-down circuit shown in FIGS. 1 and 2, respectively. 5 and 6 are circuit diagrams of a pull-up circuit and a pull-down circuit, respectively, according to the prior art. 1.17, 24.25...Power terminal, 2,8゜11.22,26.30...Resistor, 3,12
・・・・・・Depletion type P channel MO3FET
, 4゜6.13,19,27.31...Signal terminal, 5゜10.28.32...Gate circuit, 7
．． 21... Depletion type N channel MO8
FET, 9°16, 23.29... Ground terminal,
14.18...Enhancement type P-channel MO8FET, 15°20...Enhancement type N-channel MO8FET. Agent Patent attorney Oto Uchihara, 32

Claims (1)

[Claims] It has one resistor and one MOSFET, MOSFET
A semiconductor integrated circuit characterized in that the gate of T is connected directly, the source is connected to a power supply terminal or a ground terminal through a resistor, and the drain is connected to a signal terminal of a gate circuit to be pulled up or pulled down.