JP2975452B2 - Test circuit for ESD protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for an electrostatic discharge protection circuit connected to an input signal application terminal of a semiconductor integrated circuit. 2. Description of the Related Art Conventionally, an electrostatic discharge protection circuit is connected to an input signal application terminal of a semiconductor integrated circuit to protect an internal circuit such as a semiconductor integrated circuit when static electricity charged to an operator is discharged. However, since the protection circuit itself is connected to the inside of the input signal application terminal, it is not possible to test the normal operation of the protection circuit itself from outside the integrated circuit after the connection. Therefore, it has been desired to develop a technology that can be tested with a simple configuration.

[0002]

2. Description of the Related Art Devices using semiconductors are known to easily fail due to the phenomenon of electrostatic breakdown.
It is necessary to increase the electrostatic breakdown strength. The human body is easily charged and can reach several thousands of volts depending on the environment. When the charging energy is discharged instantaneously through the human body and the resistance of the device, fusing of the electrodes of the semiconductor element or destruction of the oxide film occurs. MOS large-scale integrated circuits are particularly vulnerable to electrostatic breakdown, and have a withstand voltage of several tens of volts. Therefore, a protection circuit is inserted between the input signal application terminal of the integrated circuit and the internal circuit to absorb overvoltage. FIGS. 5 and 6 show a conventional technique as a protection circuit. FIG. 5 shows a combination of a resistor and a MOS FET. Reference numeral 1 denotes an input signal application terminal, for example, an input pad, 2 denotes a connection terminal to an internal circuit, 3 denotes an FET, and 4 denotes a resistance element. Therefore, the left side of the terminal 1 is outside the device. In FIG. 4, when a high negative voltage is applied to the terminal 1, the drain-source state becomes conductive, a current flows instantaneously from the ground to the terminal 1 via the resistor 4 and the FET 3, and Absorbs voltage. In the case of FIG. 4, when the high voltage applied to the terminal 1 is positive, the operation as the protection circuit cannot be performed.

FIG. 6 shows a modification of the circuit shown in FIG.
Reference numerals 3 and 5 show FETs having different conductive types. That is, FET3 is N-type, FET5 is P-type,
In the case of FIG. 6, even if the high voltage applied to the terminal 1 is positive, the absorbing operation can be performed as in the case of the negative voltage. That is, terminal 1
This is because the FET operates individually when the high voltage is negative and when it is positive.

In addition to the configurations shown in FIGS. 5 and 6, the protection circuit includes a configuration in which a resistor is simply inserted, a configuration using a pn diode, and a combination of a resistor and a pn diode.

[0005]

In the circuits shown in FIGS. 5 and 6, when the device is completed, only the input terminal 1 is connected to the outside. Test normality cannot be evaluated. For a user, if a device using a semiconductor is connected close to an input terminal, if the protection circuit is defective, the device will be destroyed even at a momentary high voltage. The protection circuit may be defective when the transistor is not manufactured as a transistor due to a defective transistor structure at the time of manufacture, or when the operation of the transistor is incomplete due to a defective contact between an electrode and a connection line.

Although the configuration examples of the protection circuit other than those shown in FIGS. 5 and 6 are extremely simple, the operation as the electrostatic breakdown protection circuit may be insufficient.

An object of the present invention is to improve the above-mentioned drawbacks, and to test the operation state of the protection circuit with a simple configuration even after a device with an electrostatic breakdown protection circuit is completed, by using a simple configuration. It is an object of the present invention to provide a test circuit capable of rejecting the above.

[0008]

FIG. 1 is a diagram showing the principle configuration of the present invention. In FIG. 1, 1 is an input signal application terminal, 6 is a conduction control circuit for an electrostatic discharge protection circuit,
7-2 is a control signal application terminal, 8 is a semiconductor integrated circuit, 9 is ground, 10 is an electrostatic breakdown protection circuit, and 11 is a power supply. Input signal application terminal 1 of semiconductor integrated circuit 8, ground 9 and power supply 1
The present invention has the following configuration in the electrostatic breakdown protection circuit 10 that is inserted between the two and is configured by a transistor circuit. That is, a conduction / non-conduction control circuit 6 for the electrostatic breakdown protection circuit 10 is provided.
7-2, the potential of the input signal application terminal 1 is measured, and the normality of the electrostatic discharge protection circuit 10 is tested.

[0009]

In the circuit shown in FIG. 1, the control signal application terminals 7-1 and 7-2
The conduction control circuit 6 is controlled by the signal applied to
Controls non-conduction. When the protection circuit 10 is controlled, if the potential at the terminal 1 is measured by means (not shown), it can be determined whether the protection circuit 10 is a normal circuit. That is, the normality of the electrostatic discharge protection circuit 10 can be tested. ESD protection circuit 10
However, since only the continuity control circuit 6 is provided in advance, a signal used for another circuit can be used as the control signal.
It can be simply implemented as a test circuit. ESD protection circuit 1
If 0 operates normally, the semiconductor integrated circuit 8 can be prevented from being destroyed even if an abnormally high voltage is applied to the terminal 1.

[0010]

FIG. 2 is a diagram showing in detail a conduction / non-conduction control circuit 6, an electrostatic breakdown protection circuit 10, and control signal application terminals 7-1 and 7-2 in FIG. 1 as an embodiment of the present invention. . 2, 3 is an N-type FET, 5 is a P-type FET, 6 is a conduction / non-conduction control circuit, 7-1 is a test signal application terminal as a control signal, 7-2 is a data application terminal as a control signal, Reference numeral 10 denotes an electrostatic discharge protection circuit, 11 denotes a power supply, 12 and 14 denote NAND circuits, and 13 denotes an inverter. FIG. 3 shows an operation waveform diagram of the circuit shown in FIG. In FIG. 2, test signal terminals
Apply a test signal “L” to the data signal terminal 7-2.
No matter which of “H” and “L” is applied to the FETs, both the FETs 3 and 5 are turned off. As shown in the waveform diagram A of FIG.
The potential at the connection point of No. 5 is in the undefined state Z. Since this connection point is the input signal application terminal, when the potential of the input signal application terminal is measured by another measuring instrument, the potential is not "L" or "H" but in an indeterminate state. In this manner, one of the tests of the electrostatic discharge protection circuit 10 constituted by the FETs 3 and 5 is performed. This is the state shown in FIG. 6 of the prior art.

Next, as shown in a waveform diagram B of FIG. 3, when the test signal is set at "H" level and "L" is applied to the data signal terminal 7-2, the P-type FET 5 is turned on, and the N-type FET is turned on.
3 is turned off, and the terminal 1 becomes "H". Next, when "H" is applied to the data signal terminal 7-2, the conduction of the FETs 3 and 5 is reversed, and the terminal 1 becomes "L".

FIG. 4 shows a case where the configuration of another embodiment of the present invention is applied to the circuit shown in FIG. In FIG. 4, reference numeral 15 denotes an N-type FET, which is a switch for switching connection between the power supply 11 and the ground 9. FET1 turned off when "L" is applied as a test signal to terminal 7-1
5 turns on the FET 3 with the gate at “H”.
Next, when “H” is applied to the gate of the FET 15 and the FET 15 is turned on, the gate of the FET 3 is “L” and thus turned off. By observing the on / off change of the FET 3 at the terminal 1 as a potential change, the FET 3 can be tested.

[0013]

As described above, according to the present invention, the normality of the operation of the electrostatic breakdown protection circuit can be input by incorporating a control circuit for conducting / non-conducting the electrostatic breakdown protection circuit as a test circuit. It is possible to check from the signal application terminal. Since a test signal of the test circuit can be used by diverting a signal used for another circuit, only a small number of circuits may be provided as the test circuit. Therefore, the reliability of an internal circuit such as a semiconductor integrated circuit can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is an operation waveform diagram of the circuit of FIG. 2;

FIG. 4 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional technique.

FIG. 6 is a diagram showing a configuration of another conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input signal application terminal 6 Control circuit for electrostatic breakdown protection circuit 7-1, 7-2 Control signal application terminal 8 Semiconductor integrated circuit 9 Ground 10 Electrostatic breakdown protection circuit 11 Power supply

Continuation of the front page (56) References JP-A-2-105074 (JP, A) JP-A-62-268143 (JP, A) JP-A-1-171239 (JP, A) JP-A-62-149162 (JP, A) (A) JP-A-3-19359 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 G01R 31/28 H01L 21/66 H01L 21/822

Claims (1)

(57) [Claims] An input signal application terminal of a semiconductor integrated circuit (8)
In the ESD protection circuit (10), which is inserted between (1) and the ground (9) and the power supply (11) and is composed of a transistor circuit,
A conduction / non-conduction control circuit (6) for the electrostatic breakdown protection circuit (10) is provided, and control signals (7-1) (7-2) are provided to the control circuit (6).
A test circuit for an electrostatic discharge protection circuit, comprising: measuring a potential of the input signal application terminal (1) when a voltage is applied, and testing the normality of the electrostatic discharge protection circuit (10).