JPH0126225B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a television camera that uses a so-called microcomputer to correct video signals and remotely control a VTR with a simple configuration. When used together with a camera control device, the camera can easily control the camera's image using signals from the device. This allows signal standardization. For example, when adjusting the white balance of a television camera, a white subject is photographed, and the levels of the color difference signals (R-Y) and (B-Y) at that time match the level of the video signal during the blanking period. The level of the luminance signal Y in the color difference signal is adjusted as follows. When a TV camera is used one-on-one with a VTR, the video signal is sent from the camera to the VTR in addition to the video signal.
Control signals such as start/stop of the VTR are supplied, and control signals such as standby are supplied from the VTR to the camera. In that case, all of these signal lines are combined into one cable and connected to the camera at once using a multi-pin connector. On the other hand, there are cases in which a plurality of cameras as described above are prepared and a camera control device is used to take pictures while switching between the cameras. In that case, the synchronization signal, subcarrier phase, pedestal level, brightness level, chroma level, etc. must match between each camera, and control signals for this purpose are supplied to each camera from the control device. . All of the signal lines for this purpose are bundled into one cable and connected to the camera. That is, the contents of the transmitted signals differ depending on whether the camera is connected to a VTR or a control device, and the operations performed by the camera are also different accordingly. Furthermore, in such a device, when recording a video signal by fading it in and out, conventionally, the level of the video signal was manually adjusted and a VTR control switch was operated at the same time. However, in this method, two operations are performed at once, which makes the operations complicated and there is a risk of erroneous operations. Also, fade-in
There were drawbacks such as the fade-out time being inconsistent. In view of these points, the present invention is designed to perform these operations with a simple configuration using a microcomputer. An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1 is a camera, 2 is a VTR, 3
is a camera control device. Furthermore, 4 is a subject, and the light from this subject 4 is squeezed 1
0 is supplied to the image pickup tube 12 through the lens 11. Further, horizontal and vertical synchronization signals are supplied from the synchronization signal generator 13 to the image pickup tube 12 . A video signal is then taken out from this image pickup tube 12. Furthermore, this video signal passes through the process circuit 14 to the output terminal 1.
It is output to a. This output terminal 1a is connected to the VTR through the video signal lines 5a and 6a of the cable 5 or 6.
2 or the input terminal 3a of the control device 3. Furthermore, in the camera 1, correction of the video signal and the like are performed using a microcomputer. That is, 15 is a microcomputer, and this computer 15 has a central processing circuit (CPU) 5.
1, a read-only memory (ROM) 52 in which operating programs for the CPU 51 are written, a random access memory (RAM) 53 for storing data, etc., an input/output circuit 54, and the like. And CPU51, ROM52, RAM5
3 and 3 are the address bus line 55, data bus line 56, and control bus line 5, respectively.
Connected at 7. In addition, the CPU 51 and the input/output circuit 5
4 are connected by a data bus line 55 and a control bus line 56. Note that these are composed of one-chip LSI. Then, a color difference signal (R-
Y) and (B-Y) are supplied to contacts a and b of the selector 16. Further, a voltage signal from a volume 17 for setting fade-in and fade-out times is supplied to contact c of the selector 16. This selector 16 is switched by a signal from the microcomputer 15. The signal from this selector 16 is then supplied to a hold circuit 18, and the signal from this hold circuit 18 is supplied to a comparison circuit 19. Further, the contents of an arbitrary address in the RAM 53 of the computer 15 are supplied to the DA conversion circuit 20 to be converted into an analog signal, and this signal is supplied to the comparison circuit 19. This comparison output is supplied to the computer 15. Furthermore, the contents of an arbitrary address in the RAM 53 of the computer 15 are transferred to the selector 2 through the DA conversion circuit 20.
1, and this selector 21 is switched by a signal from the microcomputer 15.
The signals obtained at the contacts a to i of this selector 21 are respectively supplied to hold circuits 22a to 22i, the signals from the hold circuits 22a to 22f are supplied to the process circuit 14, and the signals from the hold circuits 22g and 22h are supplied to the process circuit 14. Synchronous signal generator 13
A signal from the hold circuit 22i is supplied to the control circuit of the iris 10. Further, a signal corresponding to the vertical blanking period from the synchronizing signal generator 13 is supplied to the computer 15, and during this signal period, the values of the hold circuits 22a to 22i are refreshed by interrupt processing. In addition, the white balance setting switch 23 and
A control switch 24 for remotely controlling the VTR 2 is connected to the computer 15. Furthermore, a signal from the computer 15 is supplied to the indicator 25. Further, in the control device 3, control signals such as a synchronization signal, a subcarrier phase, a pedestal level, a brightness level, a chroma level, etc. are outputted to a terminal 3b. This terminal 3b is connected to the terminal 1b of the camera 1 through the control line 6b of the cable 6.
A signal from this terminal 1b is supplied to the computer 15. Note that by using a digital serial signal as the control signal, a large number of control signals can be transmitted through one control line. In other words, as shown in FIG. 2, such a serial signal includes, for example, a start signal of 2 or more consecutive high potentials, followed by a 4-bit identification code, followed by a 3-bit address code, and 9 bits. It consists of a bit data code. The identification code is used to determine the type of data such as analog signals and switch switching signals, and the address code is used to determine the content of the data such as pedestal level adjustment and chroma level adjustment. The data code is read.
Note that the data code can be expanded or contracted as necessary. Also, reading of the serial signal is performed by interrupt processing. Furthermore, in the computer 15, the switch 2
A signal is generated in connection with the operation of 4, which signal is applied to the trigger terminal of the T-type flip-flop 26. The signal obtained at the output terminal of flip-flop 26 is output to terminal 1c, and the potential at terminal 1c is supplied to computer 15. This terminal 1c is connected to the terminal 2c of the VTR 2 through the line 5c of the cable 5. This terminal 2
c is connected to the system control circuit 27. The signal from the terminal 2c is then supplied to the system control circuit 27 to control the start/stop of the VTR 2. Furthermore, the terminal 1c is connected to the terminal 3c of the control circuit 3 through the line 6c of the cable 6. This terminal 3c is connected to the tally switch 28. When the tally switch 28 is turned on, the terminal 3c is brought to a high potential. Here, when terminal 1c is connected to VTR 2, terminal 2c is connected to system control circuit 2.
Since the terminal 3c is connected to the input side of the tally switch 28, its impedance is high, and when connected to the camera control circuit 3, the impedance is low because the terminal 3c is connected to the output side of the tally switch 28. This terminal 1c is connected to the computer 15. The following programs are stored in the ROM 52. The process will be explained below according to the flowchart shown in FIG. In the figure, when the power is turned on, the impedance of terminal 1c is first detected in step [1], and if it is low impedance, the control device mode flag F is set to "1" in step [2], In this case, the flag F is set to "0" in step [2]. Next, in step [4], initial settings of switches, memory, etc. are performed. Further, in step [5], flag F is determined, and when F=1, in step [6], the interrupt processing for reading the serial signal is enabled. Then, in step [7], it is determined whether or not the white balance has been adjusted. If the white balance has not been adjusted, the switch 23 is turned on in step [8].
It is determined whether the switch 23 is pressed or not, and when the switch 23 is pressed, the process proceeds to the automatic white balance adjustment routine [100]. This routine [100] is structured as shown in FIG. That is, when the routine [100] is called, the selector 16,
21 is switched to the RY side (contact a). Next, in step [102], a reference digital value, for example "80" (numbers in "" indicate hexadecimal values), is output and set in the hold circuit 22a through the DA conversion circuit 20. Furthermore, in step [103], the sampling pulse corresponding to the blanking period is set to selector 1.
6. Then, in step [104], the level of the signal from the hold circuit 18 is stored in the first memory address of the computer 15. Note that in this memory, the contents of the first memory address are read out through the DA conversion circuit 20, the output voltage and the input level are compared in the comparator circuit 19, and the contents of the first memory address are read out so that they match. This is done in such a way that it is corrected. Next, in step [105], a sampling pulse corresponding to the image period is supplied to the selector 16. Then, in step [106], the level of the signal from the hold circuit 18 is stored in the second memory address of the computer 15. Therefore, the level of the video signal during the blanking period is stored in the first memory address of the computer 15,
The level of the video signal during the image period is stored in the second storage address. Then, in step [107], the following calculation is performed: (contents of the second memory address) - (contents of the first memory address). Furthermore, if the result of the above calculation is positive in step [108], the value obtained by subtracting that value from "80",
When it is negative, the contents of the second memory address are replaced with the value obtained by adding that value to "80". Then, in step [109], the contents of the second memory address are output and set in the hold circuit 22a through the DA conversion circuit 20. Therefore, a potential corrected based on the above calculation result is set in the hold circuit 22a, and thereby the level of the luminance signal ΔYr added to the color difference signal RY is adjusted, so that the level of the luminance signal ΔYr added to the color difference signal RY is adjusted. The level is brought closer to the level of the blanking period. Further, in step [110], it is determined whether the contents of the second memory address are within a predetermined controllable range. When it is out of range, that is, when the contents of the second memory address overflow and become "00" or "FF" (F = 15), an error is displayed on the indicator 25 in step [111]. , the adjustment of the color difference signal RY is bypassed and the process proceeds to step [120] of adjusting the color difference signal B-Y. On the other hand, if it is within the range, step [112]
The contents of the first memory address are output at DA
The signal is supplied to the comparison circuit 19 through the conversion circuit 20 and compared with the level of the color difference signal RY. Then, in step [113], the comparison output is determined, and if the level of the color difference signal R-Y is large, the content of the second memory address is subtracted by "1" in step [114], and the level of the color difference signal R-Y is is small, the second
The contents of the storage address are incremented by "1". Further, in step [116], it is determined how many times the above-mentioned operation has been repeated, and if it is, for example, 15 times or less, the process returns to step [109]. When the 16th judgment is made in step [116], the process proceeds to step [120]. If the initial value is within the controllable range, the adjustment will be completed within 16 times. Furthermore, in step [120], the selectors 16 and 21 are first switched to the BY side (contact b),
Thereafter, the same adjustment as described above is performed for the color difference signal B-Y using the first and third storage addresses. When the adjustment of the color difference signal B-Y is completed, the process returns to the main routine. Further steps

The flag F is determined in [9], and when F=0, switch 2 is turned on in step [10].
4 is pressed or not, and when the switch 24 is pressed, the program proceeds to the routine [200] for controlling the VTR 2. This routine [200] is structured as shown in FIG. That is, when the routine [200] is called, first in step [201] the selectors 16,
21 is switched to contact c, and the voltage set by volume 17 is AD converted and sent to computer 15.
is read into the fourth memory address of . Next, in step [202], it is determined whether the read voltage is greater than or equal to a predetermined value. If the value is below the predetermined value, step [203]
A trigger signal is supplied to the flip-flop 26. Furthermore, in step [204], a digital value such as "FF" that maximizes the gain of the fade-in/fade-out gain control circuit built in the process circuit 14 is input to the computer 15.
This digital value is output and set in the hold circuit 22c via the DA conversion circuit 20, and then returned to the main routine. If it is determined in step [202] that the potential is greater than a predetermined value, the process proceeds to step [205], where it is determined whether the output signal of the flip-flop 26 is at a high potential. When the output signal is at a low potential, the fade-in program from step [206] onwards is executed. That is, in step [206], the digital value "0" that minimizes the gain of the gain control circuit is set in the fifth memory address, and this digital value is outputted and sent to the hold circuit 2 through the DA conversion circuit 20.
It is set to 2c. Next, in step [207], a trigger pulse is supplied to the flip-flop circuit 26. Further, in step [208], a delay of (contents of the fourth memory address)×N (ms) is performed. Thereafter, in step [209], "1" is added to the contents of the fifth memory address, and this digital value is output and set in the hold circuit 22c through the DA conversion circuit 20. Further, in step [210], it is determined whether the contents of the fifth memory address have become "FF" or not, and if not, the process returns to step [208]. When the content of the fifth memory address becomes "FF", the process returns to the main routine. Further, when the output signal is at a high potential in step [205], the fade-out program in step [211] and subsequent steps is executed. That is, in step [211], a delay of (contents of the fourth memory address)×N (ms) is performed. Thereafter, in step [212], the contents of the fifth memory address are subtracted by "1", and this digital value is output and supplied to the hold circuit 22c through the DA conversion circuit 20. Further, in step [213], it is determined whether the contents of the fifth memory address have become "00" or not, and if not, the process returns to step [211]. When the content of the fifth memory address becomes "00", the process proceeds to step [203], a trigger signal is supplied to the flip-flop 26, and "FF" is set to the fifth memory address in step [204].
A voltage corresponding to this is set in the hold circuit 22c and returned to the main routine. Furthermore, in step [11] other subroutines,
Interrupt processing etc. are performed and the process returns to step [7]. Therefore, in this circuit, when the camera 1 is powered on, it is automatically determined whether the connected device is the VTR 2 or the control device 3, and the camera 1 is placed in that mode. Furthermore, switch 23 while photographing a white subject.
When turned on, white balance adjustment is performed. When the adjustment of the color difference signal B-Y is completed, the correction signals for white balance adjustment of the color difference signals R-Y and B-Y are stored in digital values at the second and third memory addresses of the computer 15, respectively. is remembered in Furthermore, when the switch 24 is turned on while the VTR 2 is stopped, a digital value that minimizes the level of the video signal is set in the fifth memory address, and then the signal at the VTR control terminal 1c is set to a high potential. . Then, the contents of the fifth memory address are increased every time set by the volume 17. On the other hand, if the switch 24 is turned on while the VTR 2 is being driven, the volume 17
The contents of the fifth memory address are decreased every time set in , and after the digital value is minimized, the VTR
The signal at the control terminal 10 is brought to a low potential. Further thereafter, the contents of the fifth memory address are returned to the maximum value.
These digital values are then sequentially output, for example, during the vertical synchronization signal period, and are output to the hold circuits 22a,
By setting 22b and 22c, white balance, fade-in, and fade-out can be performed. Further, the control signal from the control device 3 is transferred to the camera 1 as a serial digital signal and stored in each memory address of the computer 15, and these digital values are also sequentially output during the period of the vertical synchronization signal and are sent to the hold circuits 22d to 22i. is set, and each part of the camera 1 is controlled. In this way, various adjustments are made in the television camera, but according to the present invention, since a microcomputer is used, complex adjustments can be easily made using only a program, and the circuit configuration can be simplified. can.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of an example of the present invention, Figures 2 to 5
The figure is a diagram for explaining the same. 1 is a television camera, 2 is a VTR, 3 is a camera control device, 5 and 6 are cables, 15 is a microcomputer, 23 is a white balance setting switch, and 24 is a switch for controlling the VTR 2.

Claims (1)

[Claims] 1. An imaging means, a video correction circuit for correcting a video signal from the imaging means, a storage circuit, a central processing circuit driven according to a program from the storage circuit, a VTR and a camera control device are selectively connected. and an external terminal connected to the image correction circuit, and the central processing circuit receives a signal from the image correction circuit, generates a first correction signal, and supplies the first correction signal to the image correction circuit. 1 operation mode;
a second operation mode in which the output of the operating section of the camera body is supplied to generate a control signal, and the control signal is supplied to the VTR via the external terminal; and a signal from the camera control device is supplied to the external terminal; and a third operating mode in which the second correction signal is supplied to the video correction circuit, and the second correction signal is supplied to the video correction circuit.