JPH01261914A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain control whether to execute the delay of an input signal by controlling the switching states of fifth and sixth transistors to be similar in a circuit where P type and N type transistors are connected in prescribed positions. CONSTITUTION:The P type and N type MOS transistors Q5 and Q6 are switch- controlled by a delay control signal C. Since an inverter I10 supplies an inversion signal to the gate of Q6, the switching states of Q5 and Q6 always become similar. When the signal C is in a zero level, Q5 and Q6 are in turn-off state. At such a case, the rise and fall of the input signal are both delayed and the inversion output is outputted to a terminal T2 as an output signal. When the signal C is in a one level on the other hand, Q5 and Q6 are in on state and therefore, Q1 and Q4 become equivalent to a state where the terminal T2 is directly connected. Consequently, the logical level of the terminal T2 is decided by the switching states of Q1 and Q4 and the input signal is promptly outputted from the terminal T2. Thus, whether to execute delay or not can be controlled with respect to the input signal having effective meaning for logics '0' and '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit used for adjusting the temporal relationship between input signals.

(Prior Art) Generally, in a system including a microprocessor, there are two signals, such as a data write control signal and a read control signal, which are valid at either logic "1" or "0", and data signals and address signals. Both signals such as logic "1" and "o" having valid meanings are handled. When such signals are exchanged between a microprocessor and a peripheral device, the temporal relationship between input signals is adjusted within the peripheral device in order to stabilize its operation.

For example, when a microprocessor writes or reads data to or from a peripheral device, the control signal A and address signal B from the microprocessor are sent as A' and B' within the peripheral device, as shown in Figure 5. The timings are adjusted as shown.

This is the set-up time T1 from when the address signal is switched to the time when the control signal changes to the active state, that is, the "0" level, and the set-up time T1 from the time when the control signal changes to the inactive state, that is, the "1" level. This is to ensure a sufficient hold time T2 until switching. If sufficient set-up time T1 and hold time T2 are not ensured in this way, malfunctions such as data writing or reading twice will occur.

The address signal B from the microprocessor is delayed by T by a delay circuit provided inside the peripheral device to become an internal address signal B'. Further, only the falling edge of the control signal A is delayed by the time T1+T. This delay only for the falling edge is performed by a circuit consisting of a normal delay circuit and an AND gate provided inside the peripheral circuit.

By adjusting the temporal relationship between human input signals in this way, it is possible to prevent malfunctions such as double write or double read operations, but at the same time, it is possible to prevent malfunctions such as double write or double read operations. The "0" level period of A is T-(Tl + T2), which is very short.

In order to lengthen the effective period during which operations are actually executed while securing sufficient set-up time T1 and hold time T2, only the signal switching during hold of address signal B is delayed, and the signal during set-up is delayed. There is no need to delay the switching. If this is done, the set-up time Tl can be secured by delaying the fall of the control signal by Tl instead of Tl + T2, so the effective period of operation can be increased to T-Tl.

However, when using a gate circuit to delay the control signal A, only either the falling edge or the rising edge of the control signal can be delayed.
This circuit cannot be applied to the address signal B in which both 0'' have valid meanings. Therefore, conventionally, the entire address signal has been delayed by a time uniquely determined by a delay circuit.

(Issue 8 to be solved by the invention) This invention was made in view of the above-mentioned circumstances. Conventionally, the delay of a signal that has a valid meaning for both logic "0" and "1" was uniquely delayed, but It is an object of the present invention to provide a semiconductor integrated circuit that can improve the problems that could not be achieved and inhibit delay operation as necessary.

[Structure of the Invention] (Means and Effects for Solving the Problems) A semiconductor integrated circuit according to the present invention has a signal input terminal to which an input signal is supplied, and an input signal supplied to this signal input terminal that is delayed by a predetermined time. and a delay circuit connected in series between a first power supply potential supply terminal and a signal output terminal, one gate being connected to the input terminal and the other gate being connected to the output of the delay circuit. first and second transistors of one conductivity type are connected in series between the signal output terminal and a second power supply potential supply terminal, one gate is connected to the input terminal, and the other gate is connected to the delay circuit. third and fourth transistors of a second conductivity type coupled to the output and connected in parallel to the one of the first and second transistors whose gate is connected to the output of the delay circuit; a fifth transistor connected in parallel to the one of the third and fourth transistors whose gate is connected to the output of the delay circuit; The present invention is characterized by comprising means for controlling the switches by supplying a control signal to the gates of the fifth and sixth transistors so that the switch states of the transistors are the same.

In this semiconductor integrated circuit, the fifth
By controlling both the transistor and the sixth transistor to be on, the logic level of the output terminal can be determined solely by the switch state of the transistor whose gate is connected to the signal input terminal, regardless of the output of the delay circuit. Therefore, the input signal can be output without delay. Well, the fifth
When both the transistor and the sixth transistor are controlled to be in the off state, the logic level of the signal output terminal changes only after the delay time by the delay circuit has elapsed since the input signal changed.

Therefore, it becomes possible to prohibit the delay operation of the human input signal as necessary.

Further, instead of the fifth and sixth transistors, a first transistor is connected in series between the first power supply potential supply terminal and the signal output terminal, and the gate of one transistor is connected to the signal input terminal. fifth and sixth transistors of a conductivity type, connected in series between the second power supply potential supply terminal and the signal output terminal, and a gate of one transistor being connected to the signal input terminal; a second conductivity type; seventh and eighth transistors, such that the other of the fifth and sixth transistors and the other of the seventh and eighth transistors have the same switch state. Even if a control signal is supplied to the gates of these transistors to control the switches, the same effect as in the above structure can be obtained, and the same effect can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. Signal input terminal T to which external input signals are supplied
A delay circuit 1o is connected to I. The delay circuit 1o delays the input signal by a predetermined time and outputs the delayed signal.

This delay circuit IO is connected to the inverter 1 as shown in the figure, for example.
1 to I4 and capacitors c1 to c4.

P-type MOS is connected between the power supply vcc terminal and signal output terminal 12)
Transistors Ql and Q2 are connected in series, the gate of transistor Q1 is connected to input terminal T1,
The output of the delay circuit IO is connected to the gate of the transistor Q2. Similarly, signal output terminal T2 and ground VSS
N-type MO8) transistors Q3 and Q4 are connected in series between the terminals. The gate of transistor Q3 is connected to the output of delay circuit 10, and the gate of transistor Q4 is connected to signal input terminal Tl.

A P-type MO8) transistor Q5 is connected in parallel to the transistor Q2. That is, one end of the transistor Q5 is connected to the connection node between the transistors Q1 and Q2, and the other end is connected to the signal output terminal T2. In addition, transistor Q3 has an N-type MO8) connected in parallel with this.
A transistor Q6 is connected. That is, one end of the transistor Q6 is connected to the signal output terminal T2, and the other end is connected to the connection node between the transistors Q3 and Q4.

These transistors Q5 and Q6 are switch-controlled according to the delay control signal C, but the control signal C is directly supplied to the gate of the transistor Q6, and its inverted signal is supplied to the gate of the transistor Q5 via an inverter 1.10. so that the switch states of transistors Q5 and Q6 are always the same.

When the delay control signal C is at “0” level, the transistor Q
5 and Q6 are both off. In this state, the input signal input to the signal input terminal T1 is at "O" level.
When it changes to 1″ level, at that point the transistor Q1
changes from on to off, and transistor Q4 changes from off to on. Then, when a predetermined delay time by the delay circuit 10 has elapsed, the transistor Q2 turns from on to off.
Also, transistor Q3 changes from off to on.

As a result, the potential of the output terminal T2 is discharged through the transistors Q3 and Q4 and changes from the "1" level to the "0" level.

Further, when the input signal changes from the "1" level to the "0" level, both transistors Q1 and Q2 are turned on after the delay time of the delay circuit 10 has elapsed. As a result, the signal output terminal T2 is connected to the transistor Ql.
,' are charged through Q2 and change from "0" to "1" level.

In this manner, when the delay control signal C is at the "0" level, both the rise and fall of the input signal are delayed, and the inverted output thereof is outputted from the terminal T2 as an output signal.

On the other hand, when the delay control signal C is at the "1" level, both transistors Q5 and Q6 are on. For this reason,
Transistors Q1 and Q4 are equivalent to being directly connected to signal output terminal T2. Therefore, the logic level of the signal output terminal T2 is determined only by the switch states of the transistors Q1 and Q4, and the inverted signal of the input signal is immediately outputted from the signal output terminal T2 without being delayed.

In this way, this circuit can switch between outputting the human input signal with a delay or without delay using the delay control signal C. Therefore, by changing the delay control signal C from "1" to "0" at the timing shown in FIG. Only the change can be delayed by T2.If the setup time of input address signal B is not delayed in this way, the setup time T1 can be secured by only delaying the fall of control signal A by T1. Therefore, by adjusting the temporal relationship between input signals using this circuit, the effective period during which data writing or reading operations are actually performed can be made T-Tl, which can be made longer by T2 than in the past. It becomes possible.

FIG. 3 shows a second embodiment of the invention, in which the output of the delay circuit 10 is the transistor Ql on the power supply terminal side.
, Q4, and transistors Q5 and Q6 are connected in parallel to transistors Ql and Q4, respectively.

Even with such a configuration, execution of the delay can be controlled by the delay control signal C, and the delay can be prohibited when unnecessary.

FIG. 4 shows a third embodiment of the present invention, in which, in addition to the configuration shown in FIG. 1, each gate is connected to a signal input terminal Tl.
P-type MOS transistors Q7 and N connected to
A type MOS transistor Q8 is provided. Further, the transistor Q7 is connected in series with the transistor Q5 and is connected between the power supply Vcc terminal and the signal output terminal 12,
Transistor Q8 is connected in series with transistor Q6, and is connected between signal output terminal T2 and ground VSS terminal.

In this circuit, when the delay control signal C is set to the "1" level to inhibit the delay of the input signal, the transistor Q7. Charging of signal output terminal T2 via Q5 or signal output terminal T2 via transistor Q6゜Q8
A discharge occurs.

With such a configuration, the arrangement of the transistors becomes symmetrical, which has the advantage of facilitating pattern design.

[Effects of the Invention] As described above, according to the present invention, it is possible to control whether or not to delay an input signal that has a valid meaning for both logic "0" and "1". This makes it possible to inhibit the input signal delay operation as necessary.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a timing chart illustrating the case where the temporal relationship between input signals is adjusted in the circuit shown in FIG. 1, and FIG. 3 and 4 are circuit diagrams showing other embodiments of the present invention, respectively, and FIG. 5 is a timing chart illustrating a conventional circuit in which the temporal relationship between input signals is adjusted. Ql, Q2. Q5. Q7...P-type MOS transistor, Q3. Q4. Q[i, Q8...N-type MOS transistor, 10...delay circuit, 110...inverter. Patent attorney Takehiko Suzue (cOu)

Claims (2)

[Claims] (1) A signal input terminal to which an input signal is supplied, a delay circuit that delays the input signal supplied to this signal input terminal by a predetermined time and outputs the signal, and is connected in series between the first power supply potential supply terminal and the signal output terminal. first and second transistors of a first conductivity type, one gate of which is connected to the input terminal and the other gate of which is connected to the output of the delay circuit; third and fourth transistors of a second conductivity type connected in series between power supply potential supply terminals, one gate connected to the input terminal and the other gate coupled to the output of the delay circuit; a fifth transistor connected in parallel to the one of the first and second transistors whose gate is connected to the output of the delay circuit; and a fifth transistor whose gate is connected to the output of the delay circuit among the third and fourth transistors; The fifth and sixth transistors are connected in parallel with the sixth transistor connected to the output of the circuit so that the switch states of the fifth and sixth transistors are the same. 1. A semiconductor integrated circuit comprising means for controlling a switch by supplying a control signal to a gate. (2) A signal input terminal to which an input signal is supplied, a delay circuit that delays the input signal supplied to this signal input terminal by a predetermined time and outputs the signal, and is connected in series between the first power supply potential supply terminal and the signal output terminal. first and second transistors of a first conductivity type, one gate of which is connected to the signal input terminal and the other gate of which is connected to the output of the delay circuit; are connected in series between the power supply potential supply terminals, one gate is connected to the signal input terminal,
third and fourth transistors of a second conductivity type, the other gates of which are connected to the output of the delay circuit; one transistor connected in series between the first power supply potential supply terminal and the signal output terminal; fifth and sixth transistors of a first conductivity type, the gates of which are connected to the signal input terminal; and the gates of one of the transistors are connected in series between the second power supply potential supply terminal and the signal output terminal; are connected to the signal input terminal; the other of the fifth and sixth transistors and the seventh and eighth transistor; 1. A semiconductor integrated circuit comprising means for supplying a control signal to the gates of these transistors to control the switches so that the switch states of the other transistors are the same.