JPH0126189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a static induction thyristor (hereinafter abbreviated as SI thyristor).

Static induction type transistors and thyristors are
It is a new semiconductor device based on an operating principle different from that of conventional transistors or thyristors, and has attracted particular attention in recent years due to its excellent performance.

Static Induction Transistor
Transistor (hereinafter abbreviated as SIT) is a unipolar transistor with a short channel structure that dramatically reduces the series resistance from the intrinsic gate to the source electrode, which essentially controls current within the channel region, and is similar to a triode vacuum tube. It can exhibit unsaturated current-voltage characteristics. In principle, the series resistance in the channel that causes negative feedback is extremely small, and a potential barrier can be formed in the current path using only the gate voltage, and this potential barrier can be controlled using the gate voltage and drain voltage. be. Therefore, while a potential barrier exists in the channel and the carrier density on the source side can be approximated to infinity, the drain current basically increases exponentially with respect to the gate voltage and the drain voltage.

Subsequent research and development has led to the realization of devices that effectively utilize minority carrier injection from the gate region by forward biasing the gate region. That is, by injecting minority carriers from the gate region into the channel region near the source using a short channel structure with low series resistance, it is possible to lower the potential barrier and extract majority carriers from the source. When the amount of carriers extracted from the source approaches its limit, it begins to exhibit saturation characteristics similar to bipolar transistors.

An SI thyristor that applies these principles is basically a pn (more correctly pin, pπn, or pvn) diode with a gate structure similar to SIT in at least one region, and is called a gated diode. Indicates the power characteristic. In other words, conventional PNP thyristors act on each other in positive feedback.
While it can be interpreted as a composite structure of a transistor and an npn transistor, an SI thyristor is
It can be interpreted as a composite structure of an SIT and a diode, and although carriers of both polarities contribute to conduction, the basic principles of their operating mechanisms are different.

SI thyristors have the same advantages as SIT, such as high input impedance and high-speed, large-current operation, but there is still much potential for their performance to be improved.

An object of the present invention is to provide an SI thyristor with an improved structure and particularly suitable for high current operation.

According to one embodiment of the present invention, the impurity density in the central part of the channel region of the second conductivity type surrounded by the gate region of the first conductivity type is set to be lower than the impurity density in the outer part. There is. With this configuration, when the channel region surrounded by the gate region is made into a depletion layer, the central part where the impurity density is low has a relatively flat potential profile because there are few charges to be ionized, and the outer part has a relatively flat potential profile because there are many charges to be ionized. It has a relatively steep potential profile. Therefore, when controlling the potential barrier formed by the depletion layer to transport charges from one main electrode to the other, the width of the portion that should become an effective channel with a low potential becomes wider. Therefore, in a structure with the same distance between gates, the maximum allowable current increases.

Embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same numbers indicate corresponding parts, but the dimensions are arbitrary and some parts are exaggerated.
To facilitate understanding, a conventional SI thyristor will be explained prior to the embodiments of the present invention.

An example of a conventional surface-type junction gate SI thyristor is shown in FIGS. 1a and 1b. A is a cross-sectional view, and b is a top view. In the cross-sectional view of FIG. 1a, an n ^- type region (epitaxial layer) is formed on a p ⁺ type silicon substrate 11.
13 is formed. It is obvious that a p ⁺ type region may be provided on an n ⁺ type substrate. This forms a basic p ⁺ n ^- diode structure. n ^-type region 1
A shallow n ⁺ type region 12 and a relatively deep p ⁺ type region 14 are formed on the upper part of the semiconductor device 3 by diffusion, ion implantation, selective etching, selective growth, or the like. That is,
n ^- type region 13 which is the cathode region of p ⁺ n ^- diode
A SIT structure, which is a simplified drain structure, is formed inside. The n ⁺ type region 12 is the source of the n-channel SIT and serves as the cathode of the SI thyristor. The p ⁺ type region 14 is the gate region of the n-channel SIT, and serves as the gate region of the SI thyristor. The p ⁺ -type gate region 14 has a high impurity density so that the resistivity is as low as possible without adversely affecting the performance of the device due to redistribution of impurity density due to heat treatment process, generation of strain in the crystal, etc. It is desirable to have one. The n ^- type region 13', which serves as a channel region and is sandwiched between the p ⁺ type gate region 14, forms a boundary with the gate region (pn
The depletion layer extending from the junction surface is chosen to have a width and impurity density such that it can form a potential barrier across the channel region. Impurity density is usually
It is selected within the range of 10 ¹⁰ to 10 ¹⁶ cm ^-3 . The impurity density and thickness of the n ⁺ type region between the p ⁺ type region 14 and the p ⁺ type region 11 are set mainly in consideration of the forward blocking voltage.

p ⁺ type region 11, n ⁺ type region 12, p ⁺ type region 14
On top is a low resistivity electrode 2 made of materials such as aluminum, molybdenum, other metals or polysilicon.
1, 22, and 24, respectively, and a protective film 15 made of an oxide film, nitride film, other insulating film, or insulating composite film is provided on the surface without electrodes. n ⁺
The type source region 12 and the p ⁺ type gate region 14 are elongated in the vertical direction in the figure so as to increase the current value. Furthermore, a large current can be achieved by increasing the number of channels. FIG. 1b shows a simplified top view.

The electrodes 22 and 24 are comb-shaped and face each other, and are electrically connected to the source region 12 and the gate region 14 at the tooth portions of the combs, respectively. Each gate region 14 except the outermost two is common to the channels at both ends, and a pair of opposing gate regions 14 defines one channel region 13'.

The potential distribution for electrons between the gates when the channel region 13' is depleted (pinch-off) due to the gate voltage including the built-in potential between the gate region 14 and the channel region 13' is shown below. Shown in Figure 1c. Since the impurity density in the gate region 14 is much higher than that in the channel region, it can be approximated that there is no potential gradient within the gate region 14.

The slope of the potential gradient formed in the channel region 13 depends on the impurity density of the channel region, and becomes steeper as the impurity density is higher and becomes gentler as the impurity density is lower. Most of the electrons traveling from the source region to the anode region flow through the portion 13'' where the potential gradient is lowest.

The first potential distribution for electrons between the source region 12, which becomes the cathode, and the p ⁺ region 11, which becomes the anode, when a forward voltage is applied between the two regions.
Shown in Figure d.

In the channel region 13', the potential is raised due to the influence of the gate potential, forming a saddle shape. This saddle point is called the intrinsic gate point, and the potential at the saddle point, that is, the potential barrier V ^* _G , is controlled by the gate potential to control the current caused by electrons. In this figure, holes existing in the anode are more likely to reach the higher the potential, but as long as the potential barrier of the p ⁺ n ^-junction remains on the front surface of the positive type, they do not enter the hole 13 and are blocked. If the potential barrier V ^* _G becomes less than the same level as the thermal energy, a large amount of electrons will flow into the source region 1.
2 towards the anode region 11.

pn between the n ^- type region 13 and the p ⁺ type anode region 11
The inflowing electrons accumulate in the hole barrier created by the junction, and as a result it becomes negatively charged, so the barrier to holes disappears, holes are injected from the p ⁺ region of the anode, and the device quickly turns on. Become. When the potential barrier at the p-n junction disappears in this way, a large amount of holes flow from the p ⁺ type anode region to the n ^-
It flows into the mold area 11. Since the potential distribution for holes is an inversion of the potential distribution for electrons, a large amount of injected holes flow in the opposite direction to the electrons.

The p ⁺ -type gate region 14 has a potential comparable to or somewhat lower than that of the channel region for holes, so that even if there is an electron-hole interaction, a portion of the holes will flow to the gate region. When cutting off the current, the p ⁺ type gate region 14 is reverse biased.
Then, the potential barrier ^* _G increases and blocks the electron flow.

At this time, the cathode and anode are electrically separated, but the holes existing in the p ⁺ type region 13 flow into the p ⁺ type gate region 14 whose potential has been lowered, and the intrinsic gate region near the intrinsic gate point and the p ⁺ The current is cut off when there are no more holes in the n ^- type region between the type anode regions.

FIG. 2a shows an improved example of an embodiment of the present invention.
Shows SI thyristor. For simplicity, only one channel is shown in the figure. The n ^-- type region 18, which has a lower impurity density than the n ^- type channel region 13, is replaced with an n ⁺
The novel point is that it is provided in contact with the n-type cathode region 12, and the intrinsic gate region is formed in this n ^- type region 18. The potential distribution for electrons between the gates is shown in FIG. 2b. The n ^- type region 13, which has a relatively high impurity density, generates a large potential difference by being ionized (depleted layer), and the n ^- type channel region 18, which has a low impurity density, generates only a small potential difference even when it is ionized. For example, if the potential difference generated in the channel region 18 under turn-on conditions is designed to be approximately equal to thermal energy, the effective channel width can be made approximately the same as the width of the channel region 18. When turning off, the potential of the channel rises quickly and the current is cut off quickly. At the same time, n ^--
Since the type region 18 has a lower potential for holes than the n ^- type region 13, in the operation mode in which the p ⁺ type gate region 14 is forward biased and turned on, the holes injected from the p ⁺ type gate region 14 are
They gather in the n ^-- type region 18 and work effectively to extract electrons from the n ⁺ type source region 12.

Potential difference generated within n ^- region 13 and n ^-- type region 18
Although the potential difference generated within can be determined in principle by solving Poisson's equation, it is preferable to further determine the optimum conditions experimentally. n ^--type area 18
Although shown as having the same cross-sectional area as n ⁺ type region 12, it will be clear that the dimensions of both may be modified as appropriate. The key point of this embodiment is to provide an ultra-low impurity density region adjacent to the source high impurity density region.

Although a structure in which the gate region, source region, etc. have a substantially rectangular cross section is illustrated, there is no difference in the structure obtained by ordinary diffusion. This is because, although analysis becomes difficult, it is sufficient to find the optimal conditions experimentally.
It will be obvious that all conductivity types may be reversed. The structures illustrated throughout all the embodiments are illustrative and not restrictive.

A modification of the structure of FIG. 2 is shown in FIG. In the n ^-- type region 18, the source region 12 is not adjacent to each other but is separated from the source region 12. It is effective in widening the effective channel width and is suitable for products manufactured by ion implantation.

As described above, the SI thyristor according to the present invention widens the effective channel width by providing an impurity gradient in the channel region, thereby facilitating large current operation. Surrounding the gate region of the opposite conductivity type with a region having relatively high impurity density is effective in reducing the gate current and increasing the forward blocking voltage.

[Brief explanation of drawings]

Figures 1a to d are cross-sectional views, top views, and horizontal and vertical potential distribution diagrams of a conventional SI thyristor, and Figures 2 a and b are cross-sectional views and horizontal potential distributions of an SI thyristor according to an embodiment of the present invention. The distribution diagram, FIG. 3, is a sectional view of another embodiment of the present invention. 11... Anode region, 12... Cathode region, 1
3...n ^- type semiconductor region, 14... gate region, 18
...Ultra-low impurity density semiconductor region.

Claims (1)

[Claims] 1. First conductivity type high impurity density anode region 11
a second conductivity type low impurity density channel region 13 formed above the anode region; a second conductivity type high impurity density cathode region 12 formed above the channel region; A pair of gate regions 14 of the first conductivity type with high impurity density formed in between and a depletion layer extending from the gate region at an intermediate position between the pair of gate regions are formed inside the channel region. An electrostatic induction thyristor characterized by comprising a small number of ultra-low impurity density semiconductor regions 18 of a second conductivity type and having an impurity density lower than that of the channel region, which are arranged near a pinch-off position. 2. The electrostatic induction thyristor according to claim 1, wherein the ultra-low impurity density semiconductor region is in contact with the cathode region.