JPH01261865A - Lateral type bipolar transistor - Google Patents

Abstract

PURPOSE:To improve current amplification factor without increasing size, by forming a collector layer whose effective diffusion depth is made one half or more of the depth from a semiconductor region surface to the upper surface of a buried layer. CONSTITUTION:The overlapping amount from the substrate 1 surface of the upper surface of a buried layer 2 is made, e.g., about 1mum, so that the depth (b) from the surface of a semiconductor region 10 to the upper surface of the buried layer 2 is made about 3mum. A lateral type PNP bipolar transistor 70 is formed in the N-type semiconductor region 10 being an epitaxial layer, and its P-type collector layer 20 is formed in a ring-shape which completely surrounds an emitter layer 30. Its effective depth (a) is made 2mum or more by diffusion. The emitter layer 30 is preferably arranged at a position shifted a little from the center, and has the same P-type as the collector layer, and its depth is made, e.g., about 1mum by diffusion. The depth of the collector layer 20 is (a), and the depth from the surface of the semiconductor region 10 to the upper layer of the buried layer 2 is (b), and the ratio (a) to (b) is set to 0.5. Thereby, the current amplification factor of a parasitic transistor is reduced as far as about 1, and the current amplification factor is increased up to about 200.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a horizontal bipolar transistor suitable for incorporation into an integrated circuit, more precisely a lateral bipolar transistor having one conductivity type on a semiconductor substrate of the other conductivity type. with a buried layer of the other conductivity type at the bottom.

This invention relates to a semiconductor region that is formed into a semiconductor region that is surrounded by a separation layer of one conductivity type and is junction-separated from a semiconductor substrate, using this semiconductor region as a base region.

[Conventional technology]

As is well known, bipolar transistors in electronic circuits incorporated in integrated circuit devices, etc.
Transistors with pn and pnp shapes are required, and the npn (npn) transistor has a vertical structure, but in order to standardize the manufacturing process for both types of transistors as much as possible,
The p-transistor usually has a lateral structure. However, it has been known that horizontal bipolar transistors are slightly inferior to vertical bipolar transistors in terms of characteristics such as current amplification factor, and that parasitic transistors are more likely to occur. FIG. 6 shows a typical structure of this lateral bipolar transistor.

In the example shown in FIG. 6, the buried layer 2 is diffused in a strong n-type at a predetermined location on the surface of a p-type semiconductor substrate l for an integrated circuit, and then
growing a relatively high resistance epitaxial layer 10 in the shape of
Separation layer 4 from the surface with strong p-type? The epitaxial layer 10 surrounded by the epitaxial layer 10 is diffused deeply to reach SSi2, and the epitaxial layer 10 surrounded by it is separated from the substrate into a junction-separated semiconductor region, and within this semiconductor region 10, a lateral-structured PNP transistor 80 is formed using the semiconductor region 10 as a base region. built into it.

For this purpose, both the central emitter layer 6 and the collector 117 surrounding it from the surface of the n-type semiconductor region 10 are diffused with p-type, and the base connection layer 8 in this example connects the collector layer 7 from the outside. It is diffused in a strong n-type to surround it. Emitter layer 6. The collector layer 7 and the base connection layer 8 are each provided with electrodes 16a+7a+8a for terminal purposes, and the cono PNP transistor is normally used with its emitter terminal 6a connected to a positive power supply.

The collector current of this horizontal bipolar transistor 80 flows from the emitter layer 6 to the collector layer 7 via the base region 10, but as can be seen from the figure, there is also a p-type emitter layer 6. A pnp parasitic transistor is formed, consisting of an n-type base region 10 and a p-type separation layer 4 or substrate 1, through which a type of leakage current, designated tp in the figure, flows. As can be easily seen, this parasitic transistor shares the base region 10 with the lateral transistor 80, and its current amplification factor is of course lower than that of the main transistor 80, but it can be so high that there is not much of a difference. Therefore, a considerable current t
p can flow into the parasitic transistor. When viewed from the transistor 80 in the main body, this current tp is nothing but a leakage of its emitter current, and the current amplification factor is thereby reduced.

In general, the current amplification factor of a transistor is inversely proportional to the total amount of impurities called the Gummel number in its base region, so to reduce the current amplification factor of this parasitic transistor, the current ip
The amount of impurities in the base region 12 within the range where the current flows can be increased, but in the structure shown in FIG. The only option is to increase the size considerably and increase the distance between the emitter layer 6 and the separation layer 4.

The lateral bipolar transistor 81 shown in FIG. 7 can solve this problem. As you can see by comparing it with Figure 6, this conventional example! This corresponds to the case where the diffusion depth of the base connection layer 8 in Figure R6 is increased until it reaches the buried layer 2 to form a wall layer 5, and the base connection layer 8 is diffused into this wall layer 5. In this structure, the wall layer 5 with a high impurity concentration is interposed in the path through which the aforementioned current tp flows,
This allows the current amplification factor of the parasitic transistor to be lowered.0For example, when the impurity concentration of the epitaxial layer as the base region 10 is lXl0" atoms/d, the width is 6 μm and the impurity concentration is 5X10Iff atoms/c4
When the wall layer 6 is inserted, the Gummel number of the base region of the parasitic transistor increases by about 100 times, so that the current amplification factor can be reduced to about 1/10C. Note that the remaining portions of this FIG. 7 are the same as those of the previous FIG. 6.

[Problem to be solved by the invention]

Although the horizontal bipolar transistor having the above-described wall layer structure can effectively reduce the current amplification factor of the parasitic transistor, it is more expensive and tends to be larger in size than the structure shown in FIG. In addition, there remains the problem that the current amplification factor is not improved much.

The reason why it is expensive is that, as is easily understood, providing a wall layer increases the number of manufacturing steps.

Furthermore, as shown in FIG. 7, since the wall layer 5 with a high impurity concentration is interposed between the collector layer 7 and the separation layer 4, the distance between the collector layer 7 and the separation layer 4 is increased accordingly. If the voltage is not increased, the withstand voltage value of the transistor will decrease. For example, the distance between the collector layer 7 and the base connection layer 8 must be larger than the distance between the collector layer 7 and the buried layer 2. Therefore, in order to maintain the necessary withstand voltage value, which varies depending on the design, the area in which the transistor is built usually increases by about 1.5 times.Furthermore, although the current amplification factor of the parasitic transistor decreases, As shown in Fig. 7, from the emitter layer 6, 1i1F
A path for the current ip flowing through J4 or the substrate 1 still exists, and it is considered that the current amplification factor does not increase much due to emitter current leakage caused by this path.

An object of the present invention is to solve these problems and obtain a lateral bipolar transistor that can improve the current amplification factor without increasing the size.

(!Means for solving IB) According to the present invention, the above object is achieved by providing a semiconductor substrate of one conductivity type on a semiconductor substrate of the other conductivity type as described at the beginning, and a semiconductor substrate of the other conductivity type being provided on the bottom of the semiconductor substrate of the other conductivity type. a base region as a semiconductor region having a buried layer of 9 and surrounded by a separation layer of one conductivity type; an emitter layer of one conductivity type diffused from the surface of the base region; A lateral bipolar transistor comprising a collector layer that is surrounded by a collector layer that is diffused from the surface of the semiconductor region, and whose effective diffusion depth is at least half the depth from the surface of the semiconductor region to the top I of the buried layer. achieved.

Note that the semiconductor region referred to in the above structure may be an epitaxial layer as in the past, especially in the case of an integrated circuit.The base connection layer for connecting this semiconductor region as a base region to a base terminal is conventionally As mentioned above, the collector layer is provided so as to surround it from the outside, but in the present invention, this is not particularly necessary, and it is better to concentrate it on one place on the surface of the semiconductor region and provide it in a simple shape, which will reduce the area in which the transistor is built. The ratio of the above-mentioned effective depth of the collector layer to the depth from the surface of the semiconductor region to the top surface of the buried layer, which is desirable for reducing the Even if the collector layer is in contact with the top surface of the buried layer, there is no problem as long as the voltage used by the transistor is as low as 5 V. However, in this case, the collector layer should not completely surround the emitter layer. is desirable in providing the base connection layer as described above.

In implementing the present invention, especially when incorporating it into an integrated circuit, the diffusion process of the semiconductor layer for the lateral bipolar transistor according to the present invention is common to the diffusion process of the semiconductor layer for other transistors in order to streamline the manufacturing process. It is desirable to
In this sense, it is advantageous to simultaneously diffuse the collector layer of the lateral bipolar transistor according to the invention with the base layer of the vertical bipolar transistor, in particular the outer base layer in the case of a double base structure. Furthermore, if the counterpart transistor is a field effect transistor, it is advantageous to diffuse the collector layer of the lateral bipolar transistor according to the invention at the same time as the diffusion of its well.

Furthermore, instead of making the diffusion depth of the collector layer of the lateral bipolar transistor according to the present invention deeper than that of the conventional one as described above, the thickness of the buried layer thereunder is increased to make the effective depth of the semiconductor region shallower in advance. If this is done, the diffusion depth of the collector layer can be kept at the same level as in the conventional case.

[Effect]

As mentioned above, the conventional reason why the current amplification factor of lateral bipolar transistors has not increased is that the emitter current passes through the semiconductor region laterally from the emitter layer and leaks into the isolation layer or substrate. By making the collector layer deeper than before and bringing it close to the top surface of the buried layer, the leakage path of emitter current in the semiconductor region is blocked or narrowed, thereby eliminating or reducing leakage current. As a result, the leakage current that conventionally flowed into the separation layer or substrate flows into the collector layer and becomes an effective collector current, so in the present invention, the emitter current utilization efficiency is much better than in the past, and the current amplification factor is increased. Improved several times more. According to the results of experiments and prototypes, parasitic The current amplification factor of the transistor can be reduced to a very low value, and the current amplification factor of the bipolar transistor itself can be improved.

Since the current amplification factor can be improved simply by increasing the depth of the collector layer, the present invention eliminates the need to increase the size of the transistor unlike the conventional means of providing a wall layer. If the base connection layer is concentrated in one place in the semiconductor region instead of the conventional structure in which it surrounds the collector layer from the outside, the area required to build a transistor can be reduced by about one-fourth. I can do it.

〔Example〕

Hereinafter, some embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the structure of a typical embodiment of a lateral bipolar transistor according to the present invention.

In FIG. 1, a p-type base [1, a strong n-type buried layer 2.
The n-type semiconductor region or epitaxial layer 110 and the strong p-type isolation layer 4 may be the same as conventional ones, for example, the specific resistance of the substrate 1 is about 20Ω1, and the impurity concentration of the buried layer 2 is about 5×10” atoms/d. , epitaxial layer 10
has a depth of 4 am and an impurity concentration of lXl0” atoms/d
The impurity concentration of the separation layer is 5 x 10” atoms/cj
It is said to be before and after. Note that the so-called rise of the upper surface of the buried layer 2 from the surface of the substrate 1 is, for example, approximately 1 μm, and therefore the illustrated depth b from the surface of the semiconductor region 10 to the upper surface of the buried layer 2 is approximately 3 μm. Ru.

Horizontal pnp bipolar transistor 7 in this example
0 is formed in the n-type semiconductor region O, which is an epitaxial layer, and the p-type collector layer 20 is formed in the emitter layer 3.
It is formed in an annular shape so as to completely surround 0 as shown in the figure, and is diffused much deeper than usual so that its effective depth a is 2 μm or more in this example. The impurity concentration varies depending on the design, but is usually between 10I & 10
The emitter layer 30 is preferably selected between 19 atoms/d.
In the present invention, it is preferable to arrange it at a position slightly shifted from the center of the semiconductor region 10 as shown in the figure, and it is p-type like the collector layer and is formed at a depth of, for example, 1 μm as in the conventional case.
Xl0" atoms are diffused at a concentration of around 74 atoms. When the diffusion impurity Il! IJt! It is desirable to diffuse 21 to the same depth and the same concentration as the emitter layer.

The base connection layer 11 is arranged outside the collector layer 20, but unlike the conventional annular shape, in this example it is provided in a concentrated form at one location on the surface of the semiconductor region 10 as shown. The base connection layer 11 is of course n-type, but its diffusion depth and impurity concentration may be the same as those of the emitter layer 30 to the collector connection layer 21 as in the prior art. On the emitter layer 30 and the base connection layer 11, electrode films 22, 31 and 12 made of, for example, aluminum are provided for connection with the outside, respectively, as shown.

Figure 2 is a diagram showing the current amplification factor h□ of the lateral bipolar transistor configured as above and its parasitic transistor.The collector current 1c is plotted on a logarithmic scale on the horizontal axis. The point indicated by in corresponds to the rated current of the horizontal bipolar transistor. The line marked with A in the figure is the current amplification factor of the transistor body, and its scale is taken on the vertical axis on the left, and the line marked with B The line with the symbol is the current amplification factor of the parasitic transistor, and its scale is taken on the right vertical axis. In addition, the parameters shown for each line include the collector layer 20 described above.
The ratio of the depth a to the depth b from the surface of the semiconductor region 10 to the top surface of the buried N2 is k wa a / b. Further, in the figure, the characteristics according to the present invention are shown by solid lines, and the characteristics according to the prior art are shown by broken lines.

As can be seen from the figure, in the case of the conventional technology, the value of the parameter is about 0.1, and the current amplification factor of the parasitic transistor is 1.
The current amplification factor of the lateral bipolar transistor is about 50 at best, but by setting the parameter @0.5 based on the present invention, the current amplification factor of the parasitic transistor drops to about 1. Accordingly, the current amplification factor of the lateral bipolar transistor is increased to approximately 200.

This is because the present invention reduces emitter current leakage to the separation layer or substrate, lowers the current amplification factor of the parasitic transistor, and accordingly reduces the emitter current utilization efficiency. This is thought to be the result of a significant improvement in

As can be seen from the figure, if the value of the parameter is set to 1, the current amplification factor of the parasitic transistor can be almost eliminated. This corresponds to the case where the depth is deepened until it touches the . In this case, the withstand voltage value of the lateral bipolar transistor is of course lower, but according to the prototype results, it does not reach zero, and even when the impurity concentration in the collector layer is quite high, it has a value of about 5V, and when the impurity concentration is lowered. If carefully selected, a withstand voltage value of about 15V can be obtained, and it has sufficient practicality as a horizontal bipolar transistor with a high current amplification factor for low voltage use. However, in this case, the potential applied to the base connection layer 11 can be applied to the inside of the collector layer 20 by cutting a part of the ring of the collector layer so that the emitter layer is not completely surrounded by the collector layer. It is necessary to guide it to the semiconductor region 10. If the value of the parameter is less than 1, the diffusion of the collector layer according to the present invention is much deeper than the conventional one, and the radius of curvature of the bottom tip becomes larger, so the withstand voltage value of the bipolar transistor is actually higher than the conventional one, about 50 V. It is easy to manufacture products that can withstand the operating voltage of .

3 to 5 show different embodiments of the invention in cross-section. FIG. 3 shows that within an integrated circuit a horizontal I
)fip) An example is shown in which a Langistaph 0 is fabricated together with a vertical IIpn transistor 72 of double-base structure shown on the right side of the figure, which is again connected to another junction-isolated n-type transistor 72. The p-type double base outer base layer 40 is fabricated in the semiconductor region 10 and is diffused to the same depth and impurity concentration at the same time as the collector layer 20 of the lateral transistor 70 . Similarly, the p-type inner base layer 41 of the vertical transistor 72 is co-diffused with the emitter layer 30 or collector connection layer 21 of the same conductivity type of the lateral transistor 70. Conversely, the n-type base connection layer 11 of the lateral transistor 70 is co-diffused with the emitter layer 42 and collector connection layer 43 of the same conductivity type on the vertical transistor 72 side. As is well known, this vertical transistor 70 with a double base structure is used for high withstand voltages, and in this way, the lateral bipolar transistor according to the present invention, together with a high withstand voltage vertical bipolar transistor, can be manufactured in a relatively small amount. It can be built into an integrated circuit without increasing the number of steps.

FIG. 4 illustrates the method of fabricating a lateral bipolar transistor according to the invention for an integrated circuit of the so-called 81MO5 or 810MO3 type.The lateral transistor 70 on the left side of FIG. 0 is the same as in FIG. It is assumed that an n-channel field effect transistor 73 and a p-channel field effect transistor 74 are formed in a semiconductor region 10 that is junction-isolated separately on the right side of the figure. Also in this embodiment, the collector layer 2 of the lateral transistor 70
0 is a diffusion process for the well 50 of the n-channel field effect transistor 73, which is also p-type, and is simultaneously diffused to the same depth and impurity concentration. Further, after providing the gate 51 for the field effect transistor on the surface of the semiconductor region 10, the collector connection layer 21 and the emitter layer 3o of the lateral transistor F0 are connected to the pair of source/drain layers 52 of the P channel field effect transistor 74. Similarly, the base connection layer 11 of the lateral transistor 70 can be diffused simultaneously with the pair of source/drain layers 53 of the n-channel field effect transistor 73 in the same n-type.

As can be seen from FIG. 0, the lateral transistor 71 shown on the left side of FIG. 5 has a slightly different structure than the previous one. The buried layer 3 below the region 1° has a larger rise from the surface of the substrate 10 than before, for example, about 2 μm, and therefore the effective depth of the semiconductor region 10 is made shallow, for example, about 277 m. As a result, the depth of the collector layer 20 of the lateral transistor 71 can be made shallower than before, for example, around 1.5 μm, and the diffusion thereof can be simplified.

On the other hand, the NPA transistor 72 shown on the right side of the figure is a normal vertical bipolar transistor, and the buried layer 2 under the semiconductor region 10 in which it is formed is diffused with the same rise as before. In order to make the rises of buried layers 2 and 3 different from each other in this way, it is sufficient to use different types of impurities for them. For example, arsenic or antimony is used for buried layer 2, and phosphorus is used for buried layer 3. By using as an impurity, the amount of diffusion into the semiconductor region 10 from the buried layer 3 can be increased as shown in the figure at the same heating temperature and time.

In this embodiment as well, the collector layer 20 of the horizontal transistor 71 and the base layer 60 of the vertical transistor 72 can be simultaneously diffused, and similarly the base connection layer 11 of the horizontal transistor 71 can be diffused into the epitaxial middle layer 60 on the side of the vertical transistor 72.
1 and collector connection layer 61 at the same time. Although it is possible to diffuse the emitter layer 30 of the lateral transistor 71 in this example at the same time as the collector layer 20, etc., it is preferable to increase the impurity concentration as separate diffusion.

As can be seen from the above embodiments, the present invention is not limited to these embodiments, and can be implemented in various specific or modified forms to achieve the desired effects.

〔Effect of the invention〕

As is already clear from the above description, in the present invention, a semiconductor substrate of one conductivity type is provided on a semiconductor substrate of the other conductivity type,
A horizontal bipolar device is formed in a semiconductor region which has a buried layer of the other conductivity type at the bottom and is surrounded by a separation layer of one conductivity type and is junction-separated from the semiconductor substrate, using this semiconductor region as a base region. The transistor includes this base region, an emitter layer of one conductivity type diffused from the surface of the semiconductor region, and an emitter layer diffused from the surface of the semiconductor region substantially surrounding the emitter layer, the effective diffusion depth of which is diffused from the surface of the semiconductor region. Half the depth from the surface of the semiconductor region to the top surface of the buried layer
Since it is configured with the above collector layer,
Almost all of the emitter current that can flow from the central emitter layer through the semiconductor region serving as the base region to the isolation layer or substrate is absorbed by the collector layer that substantially surrounds the emitter layer and is used as an effective collector current. Therefore, the present invention reduces the current amplification factor of the parasitic transistor that tends to occur in this type of transistor to a very low value, and also significantly improves the efficiency of using the emitter current of the main transistor, making the current amplification factor lower than that of the conventional transistor. can be improved several times over.

The lateral bipolar transistor according to the present invention, which achieves such effects, has an essentially simpler structure and can shorten the manufacturing process, as well as reduce its size, compared to a conventional structure with a wall layer. Because it is possible to
It can be manufactured at low cost. Furthermore, if the base connection layer does not surround the collector layer, the area of the semiconductor region required for fabricating it can be reduced by about four steps compared to a conventional ordinary lateral bipolar transistor. Furthermore, as can be seen from the examples, when fabricating the lateral bipolar transistor according to the present invention into an integrated circuit, simultaneous diffusion with semiconductor layers for other transistors can be easily carried out, and there is no need to particularly increase the number of fabrication steps. It is possible to incorporate lateral transistors with high current amplification factors into integrated circuits without any problems.

In addition, the lateral transistor according to the present invention is essentially suitable for high withstand voltage, and in combination with its high current amplification factor, the lateral bipolar transistor, which is comparable in performance to the vertical bipolar transistor, can be incorporated into integrated circuit devices, etc. This is made possible by the present invention.

[Brief explanation of the drawing]

1 to 5 relate to the present invention, FIG. 1 is a cross-sectional perspective view showing one embodiment of a lateral bipolar transistor according to the present invention, and FIG. 2 is a current amplification factor characteristic line illustrating the effects of the present invention. 3 to 5 are cross-sectional views of integrated circuits showing different embodiments in which lateral bipolar transistors according to the present invention are incorporated into integrated circuits. 6 and 7 relate to the prior art, and FIGS. 6 and 7 are cross-sectional perspective views of lateral bipolar transistors in different conventional examples. In FIG. 6, 1: semiconductor substrate, 2, 3: buried layer, 4: Separation layer, 5: Wall layer, 6:
Emitter layer, 7: Collector layer, 88 Base connection layer, 10
8 semiconductor region or epitaxial layer, 111 base connection layer, 12+ electrode film, 20: collector layer, 21: collector connection layer, 22: collector connection layer, 30: emitter layer, 31+ electrode film, 40: outer base layer, 41: Inner base layer, 42: Emitter layer, 43: Collector connection layer, 50
: well, 51+gate, 52.53: source/drain layer, 60: base layer, 61: emitter layer, 62: collector connection layer, To, 71: horizontal bipolar transistor, 72+vertical bipolar transistor, 73; n
Channel field effect transistor, 74: P channel field effect transistor, 80.81: Conventional lateral bipolar transistor, A: Current amplification factor of lateral bipolar transistor, B+ Current amplification factor of parasitic transistor, a: Depth of collector layer, b : Depth from the surface of the semiconductor region to the top surface of the buried layer, hI: Current amplification factor, lC: Collector current, lnX Rated value of collector current, lp: No leakage of emitter current or current flowing through a parasitic transistor, k: Parameter , ni-a/b. 1st (work 9 children's eyebrows) 2nd figure 202/ 302/20114 43 4241 3rd figure 4th figure

Claims (1)

[Claims] It is provided with a semiconductor substrate of one conductivity type on a semiconductor substrate of the other conductivity type, has a buried layer of the other conductivity type at the bottom, is surrounded by a separation layer of one conductivity type, and is junction-separated from the semiconductor substrate. A horizontal bipolar transistor built in a semiconductor region using the semiconductor region as a base region,
An emitter layer of one conductivity type diffused from the surface of the semiconductor region and an emitter layer diffused from the surface of the semiconductor region at least substantially surrounding the emitter layer, the effective diffusion depth of which is from the surface of the semiconductor region to the buried layer. A lateral bipolar transistor comprising a collector layer whose depth is at least half the depth to the top surface.