JPH01261750A - Reproducible storage circuit - Google Patents

Abstract

PURPOSE:To easily correct an incorrect writing cycle to reproduce original stored contents by providing the title circuit with an address storing means, an address selecting means, a data storing means, a data selecting means, and an AND circuit. CONSTITUTION:The AND circuit 600 inputs a write control signal and a clock to find out AND operation and the address storing means 200 stores an input address signal at timing determined by an output from the circuit 600. The data storing means 400 stores output data from a storage circuit 100 at the timing determined by the output of the circuit 600. When an incorrect writing cycle is generated, the address selecting means 300 and the data selecting means 500 select respective outputs from the means 200, 400 based upon a write reproducing signal and input the selected values to the storage circuit 100. Thus, one incorrect writing cycle can be easily corrected and the original stored contents can be reproduced.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a memory circuit that can easily correct a single erroneous write cycle and reproduce the original memory content with respect to a memory circuit used in a switchboard or the like. , In a memory circuit that writes input data to an address determined by an input address signal using a write control signal and reads data previously written to the address, an AND circuit (which calculates a logical product by inputting a write control signal and a clock) is used. (hereinafter referred to as an AND circuit), an address storage means for storing an input address signal at a timing determined by the output of the AND circuit, and an output of the input address signal and the address storage means connected to the address signal input terminal of the storage circuit in response to a write reproduction signal. address selection means for selecting and outputting one of the data; a data storage means for storing output data of the storage circuit at a timing determined by the output of the AND circuit; and data selection means for selecting and outputting one of the outputs of the data storage means.

[Industrial application field]

The present invention relates to improvements in memory circuits used in switching equipment and the like.

At this time, there is a need for a memory circuit that can easily correct one erroneous write cycle and reproduce the original memory contents.

[Conventional technology]

FIG. 4 is a block diagram of a circuit configuration of a conventional example.

FIG. 5 is a time chart explaining the operation of the conventional example.

In FIG. 4, a signal indicating digital data and an address for storing the data is input to the input terminal Di of the memory circuit 1.
When input to n and A, the above data is written into the memory circuit 1 when a signal indicating that writing is possible becomes "0" as shown in FIG. Then, the previous data stored at the same address is automatically read out from the output terminal Dout. In this manner, data is written to and read from the memory circuit 1.

[Problem to be solved by the invention]

However, the above-mentioned storage circuit has a problem in that if the write cycle is determined to be erroneous after the write is completed, the previously written data is erased and cannot be reproduced.

Therefore, an object of the present invention is to provide a memory circuit that can easily correct one erroneous write cycle and reproduce the original memory contents.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, in a memory circuit 100 that writes input data to an address determined by an input address signal using a write control signal and reads data previously written to the address, 600 inputs a write control signal and a clock. This is an AND circuit that calculates an AND.

Reference numeral 200 denotes an address storage means for storing an input address signal at a timing determined by the output of the AND circuit.

300 is connected to the address signal input terminal of the memory circuit;
This address selection means selects and outputs either the input address signal or the output of the address storage means based on the write/reproduction signal.

400 is a data storage means for storing output data of the storage circuit 100 at a timing determined by the output of the AND circuit.

Reference numeral 500 denotes data selection means that is connected to the data input terminal of the storage circuit and selects and outputs either the input data or the output of the data storage means based on the write/reproduction signal.

The above-mentioned 200, 300, 400, 500, and 600 are added to the memory circuit 100 to configure it.

[For production]

In FIG. 1, a write control signal and a clock are input to an AND circuit 600 to calculate an AND. The address storage means 200 stores the input address signal at a timing determined by the output of the AND circuit.

Further, in the address selection means 300, one of the input address signal and the output of the address storage means is selected and output based on the write/reproduction signal.

The data storage means 400 stores the output data of the storage circuit 100 at a timing determined by the output of the AND circuit. Then, the data selection means 500 selects and outputs either the input data or the output of the data storage means based on the write/reproduction signal.

As a result, if one erroneous write cycle occurs, the write reproduction signal causes the address selection means to
The data selection means selects the outputs of the address storage means and data storage means, respectively, and inputs them to the storage circuit 100.

In this way, the erroneous write cycle of l cycles can be easily corrected, and the original storage contents can be reproduced.

〔Example〕

FIG. 2 is a circuit configuration block diagram of an embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, normally the address selector 30 and the data selector 50 select ■ and ■, respectively, and the same signal (
“0”) is used to write to and read from the memory circuit 10.

In addition, the same signal as the clock is input to the AND circuit 60, and as shown in FIG. 40. Then, the input address signal and the output data of the memory circuit IO are respectively written.

Now, the processor (hereinafter referred to as CPU) connected to the memory circuit 10
(not shown), the CPU outputs a REWRITE signal and the memory circuit 10 enters the REWRITE mode.

As shown in FIG. 3, in response to the REWRITE signal (1''), the address selector 30 selects ■, and the address of the previous write cycle stored in the address register 20 is selected. choose,
The data previously written to the data register 40 is input to the memory circuit 100 input terminal Din.

Then, the data is written into the memory circuit 10 using the same signal (“0”). As a result, when the REWRITE cycle is completed, the memory contents immediately before the erroneous write cycle can be reproduced.

〔Effect of the invention〕

As described above, according to the present invention, one erroneous write cycle can be easily corrected. As a result, the original memory contents can be reproduced.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a circuit configuration block diagram of an embodiment of the present invention, Fig. 3 is a time chart explaining the operation of the embodiment, and Fig. 4 is a circuit configuration block diagram of a conventional example. , FIG. 5 is a time chart explaining the operation of the conventional example. In the figure, 200 is an address storage means, 300 is an address selection means, 400 is a data storage means, 500 is a data selection means, and 600 is an AND circuit.

Claims (1)

[Claims] A memory circuit (100) that writes input data to an address determined by an input address signal using a write control signal and reads data previously written to the address.
an AND circuit (600) that inputs the write control signal and a clock to obtain an AND; and an address storage means (200) that stores the input address signal at a timing determined by the output of the AND circuit; an address selection means (300) connected to the address signal input terminal of the storage circuit and configured to select and output either the input address signal or the output of the address storage means based on the write/reproduction signal; data storage means (for storing output data of the storage circuit (100) at timing;
400), and data selection means (500) which is connected to the data input terminal of the storage circuit and selects and outputs either the input data or the output of the data storage means in response to a write/reproduction signal. A reproducible memory circuit.