JPH01261030A - Space diversity control circuit - Google Patents

Abstract

PURPOSE:To stop the rotation of a phase shifter and to eliminate the phase fluctuation near zero phase difference by stopping the operation of an up/down counter in a prescribed range where the phase difference is close to zero. CONSTITUTION:A signal representing the polarity of the phase difference outputted from a signal processing circuit 50 counts the up/down counter 70 in response to the polarity. On the other hand, the signal representing the polarity of the phase difference from the signal processing circuit 50 is fed to a same phase detecting circuit 60, where the phase difference of the reception signal reaching a prescribed range (e.g., + or -2 deg.) near zero is detected and the count of the up/down counter 70 is stopped at that point of time, and the phase fluctuation of the phase shifter in the converging state of the phase difference is eliminated.

Description

[Detailed Description of the Invention] (Summary) Regarding the space diversity method, which is one of the fading compensation techniques for digital radio equipment, more specifically,
Compare the phases of the main side and sub side signals using a phase detector,
Regarding the space diversity control circuit that controls the phase shifter so that the phase difference disappears, the purpose is to eliminate the phase fluctuation of the phase shifter in the convergence state (near the phase difference pillow). A signal processing circuit that outputs a signal indicating polarity, an in-phase detection circuit that detects when the phase difference is within a predetermined range around zero based on the output signal of the signal processing circuit, and An up/down counter that performs an up/down counting operation and stops the counting operation when the same phase detection circuit detects the predetermined range, and controls the phase shift 3 according to the output of the up/down counter. A control signal generation circuit is provided to generate a control signal.

[Industrial application field]

The present invention relates to a space diversity method, which is one of the fading compensation techniques for digital radio equipment, and more specifically, the phase of No. 13 on the main side and sub side is compared using a phase detector, and the phase difference is eliminated. This invention relates to a space diversity control circuit that controls a phase shifter.

As is well known, in microwave band digital radio,
Fading occurs due to a variety of causes such as radio wave reflection. This facing causes a decrease in the reception level (an increase in the M sound), and in particular may cause a momentary line interruption.

Therefore, fading increases the bit error rate. Therefore, reducing the influence of fading is essential in wireless communication in the microwave band.

To date, various fading compensation techniques have been proposed and implemented. In general, the space diversity method (hereinafter referred to as the SD method) can be said to be an effective method. 5
The D7J type arranges two antennas apart to perform diversity reception. There are several SD methods as well.

For example, there are a phase comparison type in-phase synthesis method and a minimum width deviation synthesis method. Among these, the phase comparison type in-phase synthesis method is simple, fast, and has good accuracy.

[Conventional technology]

FIG. 6 is a block diagram of the phase comparison type in-phase synthesis method. This method compares the phases of the main side and sub side signals, and uses a rotary phase shifter (EP) to eliminate the phase difference.
S). In the figure, 1M is the main antenna, 18
is a sub-side antenna, 2M and 28 are high frequency/intermediate frequency conversion sections (hereinafter referred to as RF/IF sections), 3M and 3S are branch sections (hybrid circuits), 4 is a phase detector, and 5 is a space diversity control circuit. (Hereinafter, S
6 is a local oscillator, 7 is a rotary phase shifter (hereinafter simply referred to as phase shifter), and 8 is a combining section (hybrid circuit). The received signals on the main side and sub side are
They are branched at branch parts 3M and 3S, respectively, and are connected to a phase detector 4.
given to.

The phase difference detected here is converted into a control signal for the phase shifter 7 by the S D III 111 circuit 5. Then, the phase shifter 7 rotates the phase of the signal generated by the local oscillator 6 in a direction in which the phase difference disappears according to the control signal, and the RF/I
Inject into F part 2S.

FIG. 7 is a block diagram of the SD control circuit 5 shown in FIG. 6. The output of the phase detector 4 produces positive and negative voltages depending on the phase difference. The discriminator 9 receives this voltage and identifies whether the voltage is positive or negative. Then, it outputs a signal of "H" for positive voltage and "L" for negative voltage. Up/down counter 1
0 counts up when it receives a signal of °゛H'' and goes to “L”.
When it receives an IT signal, it counts down. up/
The output of the down counter 10 is stored in the ROMs 11a and 11b.
address. Data for changing the phase of the phase shifter 7 (amplitude constant) is written in these ROMs 11a and 11b. This change is a change in phase in opposite directions during up-counting and down-counting. ROMI 1a and ROMI 11b each transfer data corresponding to the address from the up/down counter 10 to D.
/A conversion 312a and 12b. And D/
The Δ-converted data is sent to the phase shifter 7. The phase shifter 7 rotates the phase in opposite directions during up-counting and down-counting. That is, the phase shifter 7 rotates the phase in the direction in which the output of the phase detector 4 becomes O.

[Problem that the invention seeks to solve]

However, the above conventional S D 1lij+ control circuit has the following problems.

The phase detector 4 always outputs a voltage having a positive or negative polarity 1, so the up/down counter 10 is always driven and performs either an up-count or a down-count operation.

FIG. 8 is a diagram showing the relationship between phase difference and voltage.

For example, when the phase is a value corresponding to the position of P in the figure.

The phase shifter 7 rotates the phase according to the data in the ROMs 11a and 11b corresponding to the count value of the up/down counter 10 so as to converge toward the origin (phase difference O) in the figure. However, as mentioned above, since the up/down counter 10 always performs a counting operation, the phase shifter 7 does not stop even when the output of the phase detector 4 becomes near 0, and the output near the origin in FIG. Repeat the phase fluctuation with . That is, the combined output undergoes repeated phase fluctuations, which deteriorates the characteristics. Particularly, when analog signal points are close to each other, such as in 64ifi or 256-value QAM, phase fluctuations cause jitter, generate noise, and increase the bit error rate.

Therefore, it is an object of the present invention to solve the above problems of the prior art and to eliminate phase fluctuations in the convergence state (near phase 10).

[Means for solving problems]

FIG. 1 is a block diagram showing the principle of the present invention.

The illustrated SD control circuit 100 is used, for example, in place of the SO control circuit 5 described above.

The signal processing circuit 50 outputs at least a signal indicating the polarity of the phase difference from the phase detector.

The in-phase detection circuit 60 detects, based on the output signal of the signal processing circuit 50, that the phase difference has fallen within a predetermined range near the pyro.

The up/down counter 70 performs an up-count or down-count operation according to the output of the signal processing circuit 50, and stops the counting operation when the same phase detection circuit 60 detects that the phase difference is within a predetermined range. .

A control signal generation circuit 80 controls the phase shifter according to the output of the up/down counter.

[Effect]

The signal processing circuit 50 outputs a signal indicating the polarity of the phase difference and causes the up/down counter 70 to perform a counting operation in accordance with the polarity.

On the other hand, a signal indicating the polarity of the phase difference from the signal processing circuit 50 is sent to the in-phase detection circuit 60, which detects that the phase difference of the received signal is within a predetermined range (for example, ±2°) near zero. At that point, the up/down counter 70 stops counting. As a result, the rotational operation of the phase shifter is stopped, and the phase fluctuation of the phase shifter in the state where the phase difference is converged is eliminated.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram of one embodiment of the sDIIIwJ circuit 100 shown in FIG. 1. This embodiment is used, for example, in place of the SD Ill t11 circuit 5 in FIG.

In FIG. 2, an operational amplifier (hereinafter referred to as an operational amplifier) 26 applies an offset voltage to the output of the phase detector 4. The phase detector 4 outputs Ov when the phase difference is zero. In this embodiment, an offset voltage of +2.5■ is given. Therefore, when the phase difference is equal, the voltage applied to the A/D converter 21 is +2.5V.

The A/D converter 21 corresponds to the signal processing circuit 50 in FIG. 1, and converts the received voltage into an 8-pit (Do"Dy) digital signal.

FIG. 3 is a diagram for explaining the operation of this embodiment.

As shown, A/D′! ! For the input of converter 21,
An 8-bit output is obtained. For example, MSB
LSB 5V → HHHHHHHI (2, 5 ■ → ILLLLLLLL OV-LLLLLLLL) The most significant bit of the digital output (
MSB) is “H” when the input voltage is 2.5V or higher,
When the voltage is lower than 2.5V, it becomes "L". That is, it shows the direction (polarity) of the phase difference.

This MSB bit is used to control flip-flops 23b and 23c. In other words, the MSB bit is directly connected to the clear terminal of the flip 70 knob 23b (
At the same time, the signal is input to the clear terminal (CLR) of the flip 70 knob 23c at J- after being inverted by the inverter 23a. Therefore, the Q outputs of the J- flip-flops 23b and 23c (7) are opposite to Aizu.

At J-, the Q output of the flip-flop 23b is given to the up drive input (U) of the up/down counters 23d and 23e, and at J-, the Q output of the flip-flop 23c is given to the down drive input (U) of the up/down counters 23d and 23e. D) is given. With the above configuration, MSB
When is H゛', the count is up and the MSB is "Shi".
It becomes a down count when . In addition, the inverter 23a,
The up/down counter 70 shown in FIG. 1 is constituted by flip-flops 23b and 23C1 and up/down counters 23d and 23e.

OR circuit 22a, AND circuit 22b1 inverter 22C
and exclusive one immediate sum circuit (hereinafter referred to as EX-OR circuit)
22d constitutes the in-phase detection circuit 60 shown in FIG. Outputs D2 to D6 and Dy (M
SB) is inverted by the OR circuit 22a and the AND circuit 22b.
and the respective gate outputs are input to the EX-OR circuit 22d. The output of the EX-OR circuit 22d is given to load terminals (LOAD) of up/down counters 23d and 23e. EX-OR circuit 22
When the output of d is 'TOBI', the counting operation is enabled, and when it becomes 'LII', the counting operation is stopped.

FIG. 3 shows the output of the A/D converter 21 as well as the outputs of the OR circuit 22a1ΔNO circuit 22b and the EX-OR circuit 22d. As shown in the figure, EX −
The reason why the output of the OR circuit 22d becomes L11 is because Dy
When (MSB) is “)-(” and D2 to D6 are “L”,
This is the case when Dy is "L II" and D2 to D6 are "H".

However, when the phase difference is 4 bits before and after 00 bits, E
The output of the X-ORfill path 22d becomes L II, stopping the counting operations of the up/down counters 23d and 23e. Here, the phase difference of 90° is A/l
) corresponds to a voltage range of 2.5 cm at the input voltage of the converter 21. Furthermore, in this embodiment, the configuration is 8 bits, and 9 bits are used.
A phase difference of 0° corresponds to 128 steps. Therefore, A
The output of the /D converter 21 is Q if the phase difference is φ (degrees).
= 128sin (φx (2π/360))
It becomes +128. Therefore, in the vicinity where the phase difference is Oo, per step (360/ (2πx 128)) = 0
．． This results in a phase difference of 45°. This is because the relationship between the phase difference and the output voltage is not a straight line but a sinusoidal wave, so it does not simply become (90''/128>).

As a result, in this embodiment, the phase difference is approximately 1L1.
Up/down counter 23d within a phase difference of 8°
The counting operation of 23e and 23e is stopped and converged.

The four output pits of each of up/down counters 23d and 23e become addresses of ROMs 24a and 24b, respectively. Phase shifter 7 (Fig. 6) is provided in ROM24a and 24b.
A signal that changes the phase of ! i width is constant) data is filled in. The phase shifter 7 can rotate the phase by 360 degrees, and the rotational position is determined by sin θ and COS θ.

Therefore, the ROM 24a stores data (voltage information vii) corresponding to this sin θ, and the ROM 24b stores the data (voltage information vii) corresponding to this sin θ.
Data (voltage information) corresponding to Sθ is stored. Since these data are digital values, the D/A converter 25
It is converted into an analog voltage by a and 25b and output to the phase shifter 7. In this way, ROM24a, 24b, D/A
Converter 25a.

25b is the control nll signal generation circuit 80 shown in FIG.
1 respond.

As explained above, in the case of the large tree, the counting operation is stopped within a phase difference range of approximately ±18° with the phase difference O as the center, and the rotation of the phase shifter 7 is stopped, so that the phase difference is The problem that fluctuation occurs and the phase difference does not converge to O can be solved. Therefore, it is possible to avoid inconveniences such as generation of miscellaneous errors and decrease in bit error rate due to this phase fluctuation, and it is possible to maintain good characteristics without deteriorating them. In the above embodiment, the rotation of the phase shifter 7 is stopped within the upper 18° range, but the present invention is not limited to this. This range is the multivalue number of QΔM (256QA
M has a more limited range than 64QAM), etc.
Determined by various conditions. Further, although the above embodiment has a configuration in which the phase shifter 7 is provided in the local system, it can be similarly implemented in a configuration in which the phase shifter is provided in the signal system. Further, although the above embodiment is constructed using the A/D converter 21 that indicates the polarity of the phase difference, it may also be a comparator with an alog input that compares the output of the phase detector 4 with two predetermined values.

Next, another embodiment of the present invention will be described. FIG. 4 is a block configuration diagram of an individual SD system in a multi-gear wireless line equipped with the present invention, and FIG. 5 is a block configuration diagram of each SD composite diagram in FIG. 4. The embodiments shown in FIGS. 4 and 5 are examples in which the invention is applied to individually controlled space diversity in a multicarrier radio link. This method is suitable for a wide band, and compensates for fading by dividing a carrier over a wide band into a plurality of chirelia.

In Fig. 4, 31M and 31S are antennas on the main side and rib side, respectively, and 32M and 328 are R antennas, respectively.
This is a receiving board for the main side and sub side, including the F/IF section, branch section, etc. 33 is the SO synthesis section, which is divided into four parts (
In this example, four multi-4-Yaria wireless lines are used as an example).

34 is a branching/AGC section, which is also divided into four parts. 3
5 is divided into four parts by a demodulating section.

The multi-4 antennas received by antennas 31M and 31S are sent to the RF/I receivers 32M and 323, respectively.
After processing F, etc., the signal is branched into four directions and provided to each SD synthesis section 33.

Each SD synthesis section is configured as shown in FIG.

The multi-gear from the receiving panel 32M is branched off at a branching section 36a and applied to a filter 37a. Filter 37a
has a 4F) area that allows only one predetermined carrier to pass among the four multi-gear carriers. Filter 37
The output of a is set to a constant level by the AGC section 38a and is given to the phase detector 39. Similarly, the multi-gear from the receiving 5J32S is branched off at the branching section 36b, and only one predetermined carrier is taken out at the filter 37b. The signal is then provided to the phase detector 39 via the AGC section 38b.

The phase detector 39 outputs a voltage corresponding to the phase difference between the two received signals, which is applied to the S D III m circuit 40 . The SD Ill i11 circuit 40 is constructed according to the present invention, and is constructed, for example, from the circuit shown in FIG.

The output of the SD control circuit 40 is given to a rotary phase shifter 41 provided in the sub side signal line to control the phase. The sub side received signal whose phase has been controlled in this way is given to the combining section 42 via the branching section 36b, while the main side received signal is given to the combining section 42 via the branching section 36a, where Both received signals are combined.

Similarly, the combined output of each SD combining section 33 is given to the corresponding demultiplexing/AGC section 34.

Here, only one carrier is demultiplexed, subjected to AGC amplification, and then sent to the corresponding demodulator 35 and demodulated.

〔Effect of the invention〕

As explained above, according to the present invention, the operation of the up/down counter is stopped in a predetermined range near where the phase difference is zero, thereby stopping the rotation of the phase shifter. Phase fluctuations near the phase difference P[;t1 are eliminated, thereby making it possible to prevent the occurrence of miscellaneous noise and an increase in the code error rate.

The present invention is suitable for application to 64QAM or 256QAM digital wireless lines.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a diagram for explaining the operation of the embodiment shown in Fig. 2, and Fig. 4 is a diagram for explaining the operation of the embodiment shown in Fig. 2. A block diagram of the individual SD method in a multicarrier wireless line equipped with the present invention, FIG. 5 is a block diagram of each SD combining unit in FIG. 4, and FIG. 6 is a block diagram of the phase comparison type in-phase combining method. 7 is a block diagram of the SD control circuit shown in FIG. 6, and FIG. 8 is a diagram showing the relationship between phase and voltage. In the figure, 50 is a signal processing circuit, 60 is a phase difference detection circuit, 70 is an up/down counter, 80 is a control signal generation circuit, and 100 is an SO control circuit. Patent applicant: Fujitsu Limited; Xiang i5 A diagram illustrating the operation of the embodiment shown in Fig. 2. Block configuration diagram of the phase comparison type in-phase synthesis method Fig. 6 The SD control circuit shown in Fig. 6. Block configuration diagram Figure 7 Relationship diagram between phase and voltage

Claims (1)

[Claims] Comparing the phases of the main side and sub side signals using a phase detector,
A space diversity control circuit that controls a phase shifter to eliminate the phase difference includes a signal processing circuit (50) that outputs at least a signal indicating the polarity of the phase difference, and a signal processing circuit (50) based on an output signal of the signal processing circuit (50). , an in-phase detection circuit (60) that detects that the phase difference is within a predetermined range near zero, and an in-phase detection circuit (60) that performs an up/down count operation according to the output of the signal processing circuit (50). (60
) detects the predetermined range, an up/down counter (70) that stops counting; and a control signal that creates a control signal that controls the phase shifter according to the output of the up/down counter (70). A space diversity control circuit comprising: a creation circuit.