JPH01260915A - Edge detection circuit - Google Patents

Abstract

PURPOSE:To attain generation of a pulse surely even to an input change generated at a shorter time interval than the pulse width generated by an edge detection circuit by detecting the leading change and the trailing change of a signal inputted to the edge detection circuit independently. CONSTITUTION:With an address signal 10 changed from a low to a high level, a flip-flop circuit 20 detects the change and generates an output pulse. With the address signal 10 changed from a low to a high level next, a flip-flop circuit 21 detects the change. Even if a signal change from a low level to a high level is generated in a time TN shorter than a prescribed delay time TW, since the flip-flop 20 detects the change, the output pulse separation having been caused in a conventional circuit and a sure edge detection signal is inputted to an enable signal of an address decoder. Thus, the cell interference by the address duplicate designation is prevented completely.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an edge detection circuit used as an address detection circuit for an asynchronous memory, etc., and in particular to an edge detection circuit that does not malfunction even if the detected signal contains noise. Regarding circuits.

[Conventional technology]

Conventionally, there is an example of this type of edge detection circuit applied to an address detection circuit of an asynchronous memory shown in FIG.

This address detection circuit generates a predetermined pulse when a rising or falling change occurs in at least one of the signals input to the detection circuit. It was used as a charge signal.

[Problem to be solved by the invention]

The conventional edge detection circuit described above has a circuit configuration that generates a pulse Tw close to the delay value of a predetermined delay circuit, regardless of the direction of change of the signal input to the detection circuit, as shown in FIG. When a noise pulse rise change and a fall change with a time interval TN shorter than the delay amount of the delay circuit occur in any one input signal itself, the output pulse of the edge detection circuit is divided into two and the pulse width becomes shorter. There are drawbacks.

This means that if the edge detection circuit described above is used as an address detection circuit in a memory circuit, the address decoder 80 cannot be sufficiently controlled when necessary, and multiple address lines are selected transiently, resulting in cell interference and malfunction. There is.

[Means to solve the problem]

The edge detection circuit of the present invention includes means for independently detecting a rising change and a falling change of at least one signal among the signals input to the edge detection circuit, and a means for independently detecting a rising change and a falling change of the signal, and a means for independently detecting a rising change and a falling change of the signal, It has means for generating a predetermined pulse.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. This figure shows the case where the edge detection circuit of the present invention is used in the address detection circuit of an asynchronous memory, and 10.11
is an address signal, 20 to 23 are flip-flop circuits,
30.31 is an inverter circuit, 40 to 43 are delay circuits,
50 to 53 are EOR gates, 60 is OR gate te, co(
7) The output of the OR gate is the output of the edge detection circuit,
The enable signal is input to the address decoder 80.

The operation when the signal shown in FIG. 2 is input to address signal 10.11 in FIG. 1 will now be described.

When address signal 10 changes from low level to high level, flip-flop circuit 20 detects this change and generates an output pulse.

Next, when the address signal 10 changes from high level to low level, this change is detected by the flip-flop circuit 21, and the signal changes from low level to high level in a time TN shorter than the predetermined delay time Tw. Even if an edge occurs, this change is detected by the flip-flop circuit 20, so there is no separation of the output pulses that was conventionally generated, and a reliable edge detection signal can be input to the enable signal of the address decoder. This has the advantage of completely preventing cell interference.

FIG. 3 is a block diagram of a second embodiment of the invention.

The same functional blocks as in Fig. 1 are given the same numbers. This example shows a circuit example that eliminates erroneous signals caused by the temporal difference in change timing of input signals 100 and 101 and noise. be.

In this figure, 200 is an AND gate, 300 is a delay circuit,
400 is a latch circuit.

Now, when there are changes in the input signals 100 and 101 shown in FIG. 4, these changes are detected independently by the flip-flop circuit 20 that detects rising changes and the flip-flop circuit 21 that detects falling changes. can be detected. Therefore, even if a rising or falling change occurs at a time interval TN shorter than the predetermined pulse width Tw of the signal 100, no separation of pulses occurs at the output cuff 0 of the edge detection circuit, so the gate of the latch circuit 400 There is an advantage that the output can be controlled reliably and that generated noise can be completely removed from the output signal 500.

It is assumed that the circuit configuration of the previous stage does not cause the signal 101 to change at time intervals shorter than the predetermined output pulse width Tw, and independent detection of rising and falling changes is not performed. An example is shown.

〔Effect of the invention〕

As explained above, the present invention independently detects the rising and falling changes of the signal input to the edge detection circuit, thereby generating pulses at shorter time intervals than the pulse width generated by the edge detection circuit. This has the effect of ensuring reliable pulse generation even when input changes occur.

This has the effect that when it is necessary to remove noise generated in a signal in an asynchronous circuit, the noise can be reliably removed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3 is a block diagram showing the second embodiment of the present invention, and FIG. 4 is a diagram showing changes in the main signals in the block diagram of FIG. 3. Diagram showing changes, 5th
The figure is a block diagram showing a conventional example, and FIG. 6 is a diagram showing changes in main part signals of the conventional example. 10.11...Address signal, 20-23...Flip-flop circuit, 30.31...Inverter circuit,
40-43...Delay circuit, 50-53...EOR gate, 60...○R gate, 70...Edge detection circuit output signal, 80...Address decoder, 100°1
01...Input signal, 200...AND gate, 40
0...Latch circuit, 500...Latch output.

Claims (2)

[Claims] (1) Equipped with means for independently detecting rising and falling changes of at least one of the input signals, and means for generating predetermined pulses from these detected signals. An edge detection circuit comprising: (2) The edge detection circuit according to claim 1, wherein a flip-flop circuit is used to detect rising and falling changes of the signal.