JPH01258162A - Information transmission equipment - Google Patents

Information transmission equipment

Info

Publication number
JPH01258162A
JPH01258162A JP8536888A JP8536888A JPH01258162A JP H01258162 A JPH01258162 A JP H01258162A JP 8536888 A JP8536888 A JP 8536888A JP 8536888 A JP8536888 A JP 8536888A JP H01258162 A JPH01258162 A JP H01258162A
Authority
JP
Japan
Prior art keywords
channel
interrupt
certain time
abnormal
interrupts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8536888A
Other languages
Japanese (ja)
Inventor
Hiroki Sakata
坂田 弘樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8536888A priority Critical patent/JPH01258162A/en
Publication of JPH01258162A publication Critical patent/JPH01258162A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the load on a control processing part to give a uniform service to each channel by detecting an abnormal channel in accordance with the number of interrupts in a certain time to stop the interrupt handling for a certain time. CONSTITUTION:The number of interrupts in the certain time is detected by a line abnormality monitor processing part 8 and abnormal states of channels are judged by this number, and a transmission/reception data processing circuit 1 is stopped for the certain time to stop the interrupt handling with respect to the channel decided to be in the abnormal state. That is, an information transmission equipment detects the abnormal state of the channel in accordance with the number of interrupts in the certain time to stop the interrupt handling of the abnormal channel for the certain time. Thus, trouble is prevented that the processing load of the trouble channel is increased in a control processing part 6 and has an influence upon processings of the other normal channels to disable the uniform service to each channel when the channel falls into the trouble state and the interrupt from the transmission/reception data processing circuit 1 frequently occurs.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、1つの制御処理部にて複数のチャネルの情
報伝送を制御する情報伝送装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information transmission device in which one control processing section controls information transmission of a plurality of channels.

〔従来の技術〕[Conventional technology]

第4図はこの種の従来の情報伝送装置を示す構成図であ
シ、図において、1はそれぞれ複数のチャネルの各々に
対応して設けられ、各チャネルの回線上に伝送されるデ
ータの取シ込み等を行う送/受信データ処理回路、2は
それぞれ前記送/受信データ処理回路1の各々に接続さ
れて、対応する送/受信データ処理回路1よ多発生した
割込要因を取シ込む割込処理部、3は所定の周期で割込
を発生するタイマ制御回路、4はこのタイマ制御回路3
よ多発生する割込を処理するタイマ割込処理部、5はこ
れら各割込処理部2およびタイマ割込処理部4が接続さ
れて、非同期に発生する割込要因を一時保留するインタ
ー7エイスキエー、6は回線状態を制御し、このインタ
ーフエイスキ為−5よシ順次入力される割込要因に基づ
いて、次の動作を判断してその起動を行う制御処理部、
7はこの制御処理部6の起動によりて実際に伝送される
データを作成する送信処理部である。
FIG. 4 is a configuration diagram showing this type of conventional information transmission device. In the figure, 1 is provided corresponding to each of a plurality of channels, and data handling equipment to be transmitted on the line of each channel is provided. Transmit/receive data processing circuits 2 that perform input, etc. are connected to each of the transmit/receive data processing circuits 1, and input interrupt factors that occur more frequently than the corresponding transmit/receive data processing circuits 1. An interrupt processing section, 3 is a timer control circuit that generates an interrupt at a predetermined period, and 4 is this timer control circuit 3.
A timer interrupt processing unit 5 handles frequently occurring interrupts, and an inter 7 ASK is connected to each of these interrupt processing units 2 and the timer interrupt processing unit 4 to temporarily suspend interrupt factors that occur asynchronously. , 6 is a control processing unit that controls the line state and determines the next operation and starts it based on the interrupt factors sequentially inputted from this interface.
Reference numeral 7 denotes a transmission processing section that creates data to be actually transmitted by activation of the control processing section 6.

次に動作について説明する。いづれかのチャネルの回線
上にデータ等が伝送されると、そのチャネルに対応付け
られ先送/受信データ処理回路1よシデータ受信の割込
が発生し、それに接続された割込処理部2が起動される
。起動された割込処理部2は、送/受信データ処理回路
1よシ受信データ等の割込要因を取シ出してインターフ
エイスキニー5へ送)、インターフエイスキ:L−5は
それを一時保留する。状態制御処理部6は、インター7
エイスキーー5よシ非同期にキューイングされた割込要
因をデキユーし、現在の回線状態にしたがって次の動作
を判断する。たとえば、次のデータの送信の場合は、送
信処理部Tを起動し、実際に回線上にデータを送シ込む
Next, the operation will be explained. When data etc. are transmitted on the line of any channel, a data reception interrupt occurs in the forward/receive data processing circuit 1 associated with that channel, and the interrupt processing unit 2 connected to it is activated. be done. The activated interrupt processing unit 2 extracts interrupt factors such as received data from the transmission/reception data processing circuit 1 and sends them to the interface skinny 5), and the interface skinny L-5 temporarily transmits them. Hold. The state control processing unit 6
A-key 5 dequeues the asynchronously queued interrupt factors and determines the next operation according to the current line state. For example, in the case of transmitting the next data, the transmission processing section T is activated and the data is actually transmitted onto the line.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の情報伝送装置は以上のように構成されているので
、いづれかのチャネルが障害状態となシ送/受信データ
処理回路1からの割込が多発した場合、制御処理部6で
は、当該障害チャネルの処理負荷が大きくなυ、他の正
常チャネルの処理に影響を与え各チャネルへの均等サー
ビスができなくなるという問題点がありた。
Since the conventional information transmission device is configured as described above, if one of the channels is in a faulty state and interrupts from the transmission/reception data processing circuit 1 occur frequently, the control processing unit 6 There was a problem that the processing load of υ was large, which affected the processing of other normal channels, making it impossible to provide equal service to each channel.

この発明は上記のような問題点を解消するためになされ
たもので、いずれかのチャネルが障害状態となった場合
に、その障害が他の正常なチャネルの処理に与える影響
を少なくして、各チャネルへの均等サービスが可能な情
報伝送装置を得ることを目的とする。
This invention was made in order to solve the above-mentioned problems, and when one of the channels becomes a failure state, the influence of the failure on the processing of other normal channels is reduced, and The object of the present invention is to obtain an information transmission device capable of providing equal service to each channel.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る情報伝送装置は、一定時間内に発生する
割込回数を検出し、その回数にょシチャネルの異常状態
を判断するとともに、異常状態と判定されたチャネルは
、一定時間割込の処理を停止させるものである。
The information transmission device according to the present invention detects the number of interrupts that occur within a certain period of time, determines the abnormal state of the channel depending on the number of times, and stops interrupt processing for a certain period of time for the channel determined to be in the abnormal state. It is something that makes you

〔作用〕[Effect]

この発明における情報伝送装置は、一定時間内に発生す
る割込回数によってチャネルの異常状態を検知し、異常
チャネルの割込処理を一定時間停止させる事によ)制御
処理部の負荷を軽減し、各チャネルの均等サービスを可
能にする。
The information transmission device according to the present invention detects an abnormal state of a channel based on the number of interrupts that occur within a certain period of time, and reduces the load on the control processing unit by stopping interrupt processing of the abnormal channel for a certain period of time. Allows equal service for each channel.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、1は送/受信データ処理回路、2は割込処
理部、3はタイマ制御回路、4はタイマ割込処理部、5
はインターフエイスキニー、6は制御処理部、1は送信
処理部であシ、第4図に同一符号を付した従来のそれら
と同一、あるいは相当部分であるため詳細な説明は省略
する。また、8は前記各送/受信データ処理回路1と各
割込処理部2との間に接続され、一定時間内の割込発生
回数に基づいて回線の異常状態を検知する回線異常監視
処理部、9は前記タイマ制御回路3とタイマ割込処理部
4との間に接続され、前記回線異常監視処理部8が回線
異常を検出するための時間の測定処理を行う回線異常時
間測定処理部である0 次に動作についてa明する。ζζで、第2図は前記回線
異常監視処理部8の動作手順を示すフローチャート、第
3図は前記回線異常時間測定処理部9の動作手順を示す
フローチャートである。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a transmission/reception data processing circuit, 2 is an interrupt processing section, 3 is a timer control circuit, 4 is a timer interrupt processing section, and 5
6 is an interface skinny, 6 is a control processing section, and 1 is a transmission processing section, which are the same or equivalent parts to those of the conventional system denoted by the same reference numerals in FIG. 4, and detailed explanations thereof will be omitted. Further, a line abnormality monitoring processing unit 8 is connected between each transmission/reception data processing circuit 1 and each interrupt processing unit 2, and detects an abnormal state of the line based on the number of interrupt occurrences within a certain period of time. , 9 is a line abnormality time measurement processing unit which is connected between the timer control circuit 3 and the timer interrupt processing unit 4 and performs a process of measuring time for the line abnormality monitoring processing unit 8 to detect a line abnormality. 0 Next, I will explain the operation. ζζ, FIG. 2 is a flowchart showing the operation procedure of the line abnormality monitoring processing section 8, and FIG. 3 is a flowchart showing the operation procedure of the line abnormality time measurement processing section 9.

いずれかのチャネルの回線上にデータ等が伝送されると
、そのチャネルに対応付けられた送/受信データ処理回
路1はデータ受信の割込を発生させる。この割込によっ
て対応する回線異常監視処理部8が起動され、起動され
た回線異常監視処理部8は対応する割込回数チエツクカ
ウンタの計数値をカウントアツプする(ステップ5TI
)。ここで、前記回数チエツクカウンタの計数値は、後
に説明するように回線異常時間測定処理部9の処理によ
って一定時間毎にクリアされている。
When data etc. are transmitted on the line of any channel, the transmission/reception data processing circuit 1 associated with that channel generates a data reception interrupt. This interrupt activates the corresponding line abnormality monitoring processing unit 8, and the activated line abnormality monitoring processing unit 8 counts up the count value of the corresponding interrupt number check counter (step 5TI).
). Here, the count value of the frequency check counter is cleared at regular time intervals by the process of the line abnormality time measurement processing section 9, as will be explained later.

次に、回線異常監視処理部8はその割込回数チエツクカ
ウンタの計数値を読み込んで、あらかじめ定められた異
常割込回数との比較を行う(ステップ5T2)。その結
果、計数値が異常割込回数以下であれば、当該回線異常
監視処理部8はそのチャネルが正常状態にあるものと判
断して処理を終了し、対応する割込処理部2は送/受信
データ処理回路1よ)受信データ等の割込要因を取シ出
してインター7エイスキ&−5にエンキューする。
Next, the line abnormality monitoring processing section 8 reads the count value of the interrupt number check counter and compares it with a predetermined number of abnormal interruptions (step 5T2). As a result, if the count value is less than or equal to the number of abnormal interrupts, the line abnormality monitoring processing unit 8 determines that the channel is in a normal state and ends the process, and the corresponding interrupt processing unit 2 Received data processing circuit 1) extracts interrupt factors such as received data and enqueues them to Inter 7 A/-5.

また、比較の結果、計数値が異常割込回数を越えていれ
ば、当該回線異常監視処理部8はそのチャネルの回線状
態に異常が発生したものと判定し、対応する送/受信デ
ータ処理回路1を停止させて(ステップST3 )処理
を終了する。これによって、当該異常状態のチャネルの
回線からの割込は、その後、あらかじめ設定された一定
の時間だけ処理されなくなる。
Furthermore, as a result of the comparison, if the counted value exceeds the number of abnormal interrupts, the line abnormality monitoring processing section 8 determines that an abnormality has occurred in the line state of that channel, and the corresponding transmission/reception data processing circuit 1 is stopped (step ST3), and the process ends. As a result, interrupts from the line of the channel in the abnormal state will not be processed for a predetermined period of time thereafter.

また、回線異常時間測定処理部9は、定められた所定の
周期で割込を発生しているタイマ制御回路3によって起
動され、まず、全ての割込回数チエツクカウンタの計数
値をクリアする(ステップST4 )。従りて、割込回
数チエツクカウンタはタイマ制御回路3の割込周期でク
リアされ、前記各回線異常監視処理部8は、この割込同
期内に割込回数チエツクカウンタの計数値が、あらかじ
め定められた異常割込回数を越えた場合に、そのチャネ
ルの異常状態と判定する。
The line abnormality time measurement processing unit 9 is activated by the timer control circuit 3 which generates interrupts at a predetermined period, and first clears the counts of all interrupt count check counters (step ST4). Therefore, the interrupt count check counter is cleared at the interrupt cycle of the timer control circuit 3, and each line abnormality monitoring processing section 8 clears the count value of the interrupt count check counter within this interrupt synchronization by a predetermined value. If the number of abnormal interrupts exceeds the specified number of abnormal interrupts, it is determined that the channel is in an abnormal state.

次に、回線異常時間測定処理部9は各チャネル毎に、送
/受信データ処理回路1が停止しているか否かを判定し
くステップST5 )、停止している場合にはその停止
時間があらかじめ定められた設定時間を経過したか否か
を判定する(ステップST6 )。判定の結果、停止時
間が設定時間を過ぎていればその送/受信データ処理回
路1の停止解除を行う(ステップ5T7)。これにより
て、−度対応するチャネルが異常と判定されて停止状態
となった送/受信データ処理回路1が、回線状態が正常
に復帰した後も永久に停止状態になっていることを防止
している。このステップST5〜ステップST7の処理
は、ステップST8で全チャネルの確認が済んだことを
検出するまで繰シ返される。ステップST8にて全チャ
ネルの確認が終了したことを検出すると、尚該処理を終
了し、次の割込がタイマ制御回路3よシ発生するまで待
機する。
Next, the line abnormality time measurement processing unit 9 determines for each channel whether or not the transmitting/receiving data processing circuit 1 is stopped (step ST5), and if it is stopped, the stopping time is determined in advance. It is determined whether the set time has elapsed (step ST6). As a result of the determination, if the stop time has exceeded the set time, the transmission/reception data processing circuit 1 is canceled (step 5T7). This prevents the sending/receiving data processing circuit 1, which has been stopped due to the determination that the corresponding channel is abnormal, from being permanently stopped even after the line status has returned to normal. ing. The processing of steps ST5 to ST7 is repeated until it is detected in step ST8 that all channels have been confirmed. When it is detected in step ST8 that the confirmation of all channels has been completed, the process is ended and the timer control circuit 3 waits until the next interrupt occurs.

なお、上記実施例では、タイマ制御回路からの割込によ
シ各監視時間を検知したが、タイマ制御回路を利用せず
にプログラム実効時間を利用してプログラムによる監視
時間の検知を行ってもよく、上記実施例と同様の効果を
奏する。
In the above embodiment, each monitoring time was detected by an interrupt from the timer control circuit, but it is also possible to detect the monitoring time by the program using the program effective time without using the timer control circuit. In many cases, the same effects as in the above embodiment can be achieved.

〔発明の妨果〕[Interference with invention]

以上のように、この発明によれば、一定時間内に発生す
る割込回数によル異常チャネルを検知し、当該異常チャ
ネルの割込処理を一定時間停止させるように構成したの
で、制御処理部の負荷を軽減し、異常状態のチャネルが
発生してもその異常状態が他のチャネルに与える影響を
少くして、各チャネルへの均等サービスが可能な情報伝
送装置が得られる効果がある。
As described above, according to the present invention, an abnormal channel is detected based on the number of interrupts occurring within a certain period of time, and the interrupt processing of the abnormal channel is stopped for a certain period of time. This has the effect of reducing the load on other channels, reducing the influence of the abnormal state on other channels even if a channel is in an abnormal state, and providing an information transmission apparatus that can provide equal service to each channel.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例による情報伝送装置を示
す構成図、第2図はよび第3図はその動作手順を示すフ
ローチャート、第4図は従来の情報伝送装置を示す構成
図である。 1は送/受信データ処理回路、2は割込処理部、3はタ
イマ制御回路、4はタイマ割込処理部、6は制御処理部
、8は回線異常監視処理部、9は回線異常時間測定処理
部。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a configuration diagram showing an information transmission device according to an embodiment of the present invention, FIGS. 2 and 3 are flowcharts showing its operating procedure, and FIG. 4 is a configuration diagram showing a conventional information transmission device. be. 1 is a transmission/reception data processing circuit, 2 is an interrupt processing section, 3 is a timer control circuit, 4 is a timer interrupt processing section, 6 is a control processing section, 8 is a line abnormality monitoring processing section, 9 is a line abnormality time measurement processing section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 1つの制御処理部にて複数のチャネルの情報伝送の制御
を行う情報伝送装置において、前記各チャネル毎に一定
時間内に発生する割込回数を検出し、検出された前記割
込回数が所定値を越えた場合、当該チャネルを異常状態
と判定するとともに、異常状態と判定された前記チャネ
ルからの割込の処理を一定時間停止することを特徴とす
る情報伝送装置。
In an information transmission device in which one control processing unit controls information transmission of a plurality of channels, the number of interruptions that occur within a certain period of time for each channel is detected, and the detected number of interruptions is a predetermined value. An information transmission device characterized in that when the channel is determined to be in an abnormal state, the channel is determined to be in an abnormal state, and interrupt processing from the channel determined to be in the abnormal state is stopped for a certain period of time.
JP8536888A 1988-04-08 1988-04-08 Information transmission equipment Pending JPH01258162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8536888A JPH01258162A (en) 1988-04-08 1988-04-08 Information transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8536888A JPH01258162A (en) 1988-04-08 1988-04-08 Information transmission equipment

Publications (1)

Publication Number Publication Date
JPH01258162A true JPH01258162A (en) 1989-10-16

Family

ID=13856774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8536888A Pending JPH01258162A (en) 1988-04-08 1988-04-08 Information transmission equipment

Country Status (1)

Country Link
JP (1) JPH01258162A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2256628A1 (en) 2009-05-22 2010-12-01 Renesas Electronics Corporation Interrupt processing apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2256628A1 (en) 2009-05-22 2010-12-01 Renesas Electronics Corporation Interrupt processing apparatus and method

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