JPH01256165A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance the breakdown strength of a bipolar transistor against an junction and to quicken the operating speed of the bipolar transistor by a method wherein the emitter and collector diffused regions of a lateral PNP transistor and the emitter diffused region of a vertical PNP transistor are formed into a structure, wherein a region of a high P-type impurity concentration is formed in a region of a low P-type impurity concentration. CONSTITUTION:A lateral PNP transistor is formed in an N-type well 16 and its emitter 18 consisting of a P-type diffused region is formed into a structure, wherein a high impurity concentration diffused region 18b is formed on the inner side of a low-impurity concentration diffused region 18a. Moreover, a vertical PNP transistor is formed in an N-type well 21 and its emitter 22 consisting of a P-type diffused region is formed into a structure, wherein a high impurity concentration diffused region 22b is formed on the inner side of a low impurity concentration diffused region 22a. Thereby, the breakdown strength of a bipolar transistor against a junction can be enhanced and the operating speed of the bipolar transistor can be quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor integrated circuit device having a bipolar transistor and a MOS transistor mixed therein, and particularly to a BiCMO5 type semiconductor integrated circuit device having a bipolar transistor and a CMO3 mixedly mounted thereon.

(Prior Art) In a BiCMO5 type semiconductor integrated circuit, a source region and a drain region of a MOS transistor constituted by a P-type impurity diffusion region and a P-type diffusion region of a bipolar transistor are formed in the same process.

However, when forming an NPN transistor, the P-type diffusion region must be formed deep, so that the P-type diffusion region of the MOS transistor also becomes deep, resulting in a disadvantage that the degree of integration cannot be increased.

Furthermore, in order to improve the characteristics of an NPN transistor, the impurity concentration of the P-type diffusion region, which is the base, must be lowered, so the resistance value of the P-type diffusion region becomes high in the MoS transistor.

In another method of manufacturing a B i CMO8 type O8 integrated circuit device, the base of the NPN) transistor is Mo8)-
Although it is formed in a separate process from the P-type diffusion region of the transistor,
NP) - The emitter diffusion region and collector diffusion region of the transistor are made in the same process as the P-type diffusion region of the MOS transistor.

However, in this method, the impurity concentration of the emitter diffusion region and the collector diffusion region of the PNP transistor is matched to the impurity concentration of the MOS transistor, so the concentration is high for a bipolar transistor, and the emitter-base breakdown voltage BVebo and base-collector breakdown voltage BVcbo becomes lower.

(Objective) The present invention provides a BiCMO5 type semiconductor integrated circuit device that includes:
The purpose is to increase the junction breakdown voltage and operation speed of bipolar transistors.

(Structure) In the present invention, the emitter diffusion region and the collector diffusion region of the L-PNP transistor and the emitter diffusion region of the V-PNP transistor are formed such that a high concentration region of P-type impurity is formed within a region of low concentration of P-type impurity. Make it a structure.

Examples will be specifically described below.

FIG. 1 represents one embodiment.

P-type epitaxial layer 2 on P-type silicon single crystal substrate l
is formed, and in each field region separated by the field oxide film 3, an NMOS transistor, a P
MOS transistor, NPN transistor, L-PNP
A transistor and a -PNP transistor are formed.

The NMOS transistor has a source 4 by an N-type diffusion region.
, a drain 5, and a gate electrode 6 made of a polysilicon layer provided through a gate oxide film.

The PMOS transistor is composed of a source 8 formed by a P-type diffusion region in an N-type well 7, a drain 9, and a gate electrode 10 formed by a polysilicon layer provided via a gate oxide film.

The NPN transistor is formed in an N-type well 11, 13 is a base, 14 is an emitter, and well 1
1 is a collector, and 15 is a contact. An N-type buried layer 12 is formed at the bottom of the well 11 .

An L-PNP transistor is formed in N-type well 16. 18 is an emitter made of a P-type diffusion region;
The collector 19 is formed by a P-type diffusion region in a ring shape around it.
is surrounding. The well 16 serves as a base, and 20 is a contact to the base. An N-type buried layer 17 is formed at the bottom of the well 16.

In the emitter 18, a diffusion region 18b with a high impurity concentration is formed inside a diffusion region 18a with a low impurity concentration. Similarly, in the collector 19, a diffusion region 19b with a high impurity concentration is placed inside a diffusion region 19a with a low impurity concentration.
is formed.

The V-PNP transistor is formed in an N-type well 21, 22 is an emitter formed by a P-type diffusion region, and the well 2
1 serves as a base, P-type epitaxial layer 2 and substrate 1
becomes the collector. 23 is a base contact.

In the emitter 22, a diffusion region 22b with a high impurity concentration is formed inside a diffusion region 22a with a low impurity concentration.

Next, regarding the manufacturing method of this example, FIGS. 2(A) to (C)
) and FIG.

Figure 2 (A) shows a typical polysilicon gate BiCM.
In accordance with the manufacturing process of an O8 type semiconductor integrated circuit device, a gate electrode of up to 6.10 mm is formed by a polysilicon layer. 30 is a gate oxide film.

Using a resist as a mask, boron is implanted at about 60 KeV into the base of the NPN transistor, the emitter and collector of the L-PNP transistor, and the emitter of the V-PNP transistor at about I×10”/cm 3 using a resist as a mask.

Thereafter, heat treatment is performed in nitrogen at about 950° C. for about 60 minutes to activate the implanted ions. As a result, (B
), a base 13, an emitter 18a, a collector 19a, and an emitter 22a are formed by low concentration P-type impurity diffusion regions.

Next, the source and drain of the NMOS transistor, N
Emitter and collector of P N transistor, L-
Arsenic was applied to the base of the PNP transistor and the base of the V-PNP transistor using a resist as a mask.
Implant approximately 6X10''/cm' at 0 KeV. Then perform a heat treatment in nitrogen at approximately 900 °C for approximately 40 minutes to activate the implanted ions, as shown in (C).

Source 4, drain 5, emitter 14. collector 15,
Base 20 and base 23 are formed.

Next, the source, drain, and L-
PNP) - emitter, collector of transistor, V-PN
P) - Apply boron at about 30KeV to about 3XI O1S/c using resist as a mask where it will become the emitter of the transistor.
m' implantation 6 Thereafter, heat treatment is performed in nitrogen at about 900° C. for about 20 minutes to activate the implanted ions. As a result, the B1CMOS transistor shown in FIG. 1 is formed.

Thereafter, as is generally done, an interlayer insulating film is formed, contact holes are formed, metal wiring is formed, and a passivation film is formed.

The example is a B1CMOS semiconductor integrated circuit device with an N-type well configuration in which a P-type epitaxial layer is formed on a P-type substrate. It is also possible to apply the present invention to a BiCMO8 type semiconductor integrated circuit device.

In addition, in the example, as shown in FIG. 2(C), NP
Although the emitter I4 of the N transistor and the source 4 and drain 5 of the NMOS transistor are formed in the same process, the present invention can also be applied to the case where they are formed in separate processes. In that case, the source 4 and drain 5 may be formed after forming the emitter 14. By performing separate steps in this way, the impurity concentration and the annealing temperature for activating the implanted ions can be determined independently. This is advantageous in terms of transistor characteristics.

When forming a region with a high impurity concentration within a region with a low impurity concentration in the emitter or collector of a bipolar transistor, the mask on the high concentration side and the mask on the low concentration side may be the same, and the size of the mask on the high concentration side may be smaller than the size of the mask on the low concentration side.

(Effects) In the present invention, the emitter diffusion region and collector diffusion region of the L-PNP transistor and the emitter diffusion region of the V-PNP transistor are formed such that a high concentration region of P-type impurity is formed within a region of low concentration of P-type impurity. This structure increases the junction breakdown voltage. Furthermore, since a highly concentrated impurity diffusion region is formed inside these diffusion regions, the resistance is lowered and the operating speed is increased.

The table below shows the ft (cutoff frequency) and emitter-base breakdown voltage BVebo of the L-PNP transistor, (A) in the example, (B) in the case where the emitter and collector are formed only with low impurity concentration regions, and (C). Comparison results are shown for cases in which the emitter and collector are formed only from high impurity concentration regions.

This shows that according to the present invention, both the operating speed and the junction breakdown voltage are satisfied.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment, and FIGS. 2(A) to 2(C) are sectional views showing the manufacturing process of one embodiment. 18.22...Emitter diffusion region, 19...
...Collector diffusion region. 18a, 19a, 22a...Low concentration area. 18b, 19b, 22h... High concentration area.

Claims (1)

[Claims] (1) A bipolar transistor and a MOS transistor are mounted together, and the emitter diffusion region and collector diffusion region of the L-PNP transistor and the emitter diffusion region of the V-PNP transistor are a region with a high concentration of P-type impurity within a region with a low concentration of P-type impurity. A semiconductor integrated circuit device in which