JPH01253320A - Cyclic encoding circuit - Google Patents

Cyclic encoding circuit

Info

Publication number
JPH01253320A
JPH01253320A JP63080680A JP8068088A JPH01253320A JP H01253320 A JPH01253320 A JP H01253320A JP 63080680 A JP63080680 A JP 63080680A JP 8068088 A JP8068088 A JP 8068088A JP H01253320 A JPH01253320 A JP H01253320A
Authority
JP
Japan
Prior art keywords
pattern
circuit
pseudo random
random numbers
shift registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63080680A
Other languages
Japanese (ja)
Other versions
JP2531737B2 (en
Inventor
Tatsuhiko Nakagawa
中川　達彦
Hiroya Watanabe
渡邊　浩哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Miyagi Ltd
Original Assignee
NEC Corp
NEC Miyagi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Miyagi Ltd filed Critical NEC Corp
Priority to JP63080680A priority Critical patent/JP2531737B2/en
Publication of JPH01253320A publication Critical patent/JPH01253320A/en
Application granted granted Critical
Publication of JP2531737B2 publication Critical patent/JP2531737B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To produce (2<n>-n) types of different pseudo random numbers by providing a circuit which decides the pattern of the produced pseudo random number for selection of the specific value contained in the random number and inverting an output pattern just by a single bit. CONSTITUTION:A cyclic encoding circuit 100 consisting of the shift registers of (n) stages produces the pseudo random numbers in the cycle of (2<n>-1) patterns and the data of the pseudo random numbers are held by the shift registers 1-n. A pattern deciding circuit 200 compares the data of the pseudo random numbers with the values of the shift registers. When the coincidence of pattern is detected, an inverting circuit 300 inverts the output pattern of the pseudo random number just by a single bit and sends the pattern. The optional patterns which are compared by the circuit 200 can be prepared in (2<n>-1) different types and therefore (2<n>-1) types of different pseudo random numbers are obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多数の擬似乱数を発生する巡回符号化回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cyclic encoding circuit that generates a large number of pseudorandom numbers.

〔従来の技術〕[Conventional technology]

従来、１つの擬似乱数を発生するためには、ｎ段のシフ
トレジスタを組合せた２”−１パターンの巡回符号化回
路を用いていた。Conventionally, in order to generate one pseudorandom number, a 2''-1 pattern cyclic encoding circuit combining n-stage shift registers has been used.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来回路においては、擬似乱数を発生する巡回
符号は、その回路を構成するシフトレジスタの段数によ
って、その乱数のパターンおよびその周期が決定されて
いるので、異なる乱数のパターンを持ち、かつ同じ周期
性を持つ擬似乱数を発生出来ないという欠点があった。In the conventional circuit described above, the cyclic code that generates pseudo-random numbers has a random number pattern and its period determined by the number of stages of the shift register that constitutes the circuit, so it has different random number patterns and the same The drawback was that it was not possible to generate pseudo-random numbers with periodicity.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の目的は上述の欠点を除去した巡回符号化回路を
提供することにある。本発明の回路は、上記目的を達成
するために、巡回符号化回路で発生する擬似乱数のパタ
ーンを判定する回路を備えて、乱数内の特定の値を選択
し、その状態での出力パターンを１ｂｉｔのみ反転する
ことによって、２”−１種の異なる擬似乱数を発生して
いるン〔実施例〕　　　。SUMMARY OF THE INVENTION An object of the present invention is to provide a cyclic encoding circuit which eliminates the above-mentioned drawbacks. In order to achieve the above object, the circuit of the present invention includes a circuit that determines a pattern of pseudorandom numbers generated in a cyclic encoding circuit, selects a specific value among the random numbers, and outputs an output pattern in that state. By inverting only 1 bit, 2''-1 different pseudo-random numbers are generated [Example].

次に本発明を図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.

第１図は、本発明の一実施例を示す回路図である。図に
おいて、ｎ段のシフトレジスタで構成される巡回符号化
回路１００は、２″−１パターンの周期で擬似乱数を発
生している。そのおのおののシフトレジスタ１〜ｎには
擬似乱数のデータが保持されている。パターン判定回路
２００は、比較器から構成され、擬似乱数のデータを保
持しているシフトレジスタの値と比較を行ない、任意の
パターンの値と一致するまで待つ。パターンの一致が検
出されると、反転回路３００にて擬似乱数の出力パター
ンを１ｂｉｔのみ反転させ出力させる。比較器２００で
比較する任意のパターンは、２”−１種の区別を付ける
事が可能なため、２”−１の異なる擬似乱数を作る事が
可能となる。FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, a cyclic encoding circuit 100 composed of n-stage shift registers generates pseudo-random numbers at a period of 2''-1 pattern. Each of the shift registers 1 to n stores pseudo-random number data. The pattern determination circuit 200 is composed of a comparator, and compares the value with the value of the shift register that holds the pseudo-random number data, and waits until the value matches the value of an arbitrary pattern. When detected, the inversion circuit 300 inverts only 1 bit of the pseudorandom number output pattern and outputs it. Any pattern to be compared by the comparator 200 can be distinguished from 2"-1. ``It is possible to create different pseudo-random numbers of -1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明では、簡単な回路の追加に
より２１１−１の一定周期の巡回符号発生回路内の任意
のパターンに対応する出力信号の擬似乱数内の１ビツト
を反転させて２ａ−１種類の異なる乱数を同一の周期で
発生させることができる。As explained above, in the present invention, by adding a simple circuit, one bit in the pseudo-random number of the output signal corresponding to an arbitrary pattern in the constant-period cyclic code generation circuit 211-1 is inverted. One type of different random number can be generated at the same cycle.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す回路図である。 １００・・・・・・シフトレジスタで構成される巡回符
号化回路、２００・・・・・・パターン判定回路、３０
０・・・・・・位相反転回路。 代理人　弁理士　　内　原　　　晋FIG. 1 is a circuit diagram showing an embodiment of the present invention. 100...Cyclic encoding circuit composed of shift registers, 200...Pattern determination circuit, 30
0... Phase inversion circuit. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] ２＾ｎ−１パターンの擬似乱数を発生する巡回符号化回
路において、擬似乱数内の任意のパターンを判定し、そ
の時の出力パターンを反転することによって、２＾ｎ−
１種の区別が可能な擬似乱数を発生することを特徴とす
る巡回符号化回路。In a cyclic encoding circuit that generates 2^n-1 patterns of pseudo-random numbers, by determining an arbitrary pattern in the pseudo-random numbers and inverting the output pattern at that time, 2^n-
A cyclic encoding circuit characterized in that it generates pseudorandom numbers that can be distinguished from one another.
JP63080680A 1988-03-31 1988-03-31 Cyclic coding circuit Expired - Lifetime JP2531737B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63080680A JP2531737B2 (en) 1988-03-31 1988-03-31 Cyclic coding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63080680A JP2531737B2 (en) 1988-03-31 1988-03-31 Cyclic coding circuit

Publications (2)

Publication Number Publication Date
JPH01253320A true JPH01253320A (en) 1989-10-09
JP2531737B2 JP2531737B2 (en) 1996-09-04

Family

ID=13725063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63080680A Expired - Lifetime JP2531737B2 (en) 1988-03-31 1988-03-31 Cyclic coding circuit

Country Status (1)

Country Link
JP (1) JP2531737B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54132145A (en) * 1978-04-06 1979-10-13 Nec Corp False random code generator
JPS566522A (en) * 1979-06-28 1981-01-23 Mitsubishi Electric Corp False irregular signal generator
JPS6181223U (en) * 1984-11-02 1986-05-29
JPS6218819A (en) * 1985-07-17 1987-01-27 Fujitsu Ltd Generating circuit for pseudo random pattern
JPS63248242A (en) * 1987-04-03 1988-10-14 Fujitsu Ltd Error generating circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54132145A (en) * 1978-04-06 1979-10-13 Nec Corp False random code generator
JPS566522A (en) * 1979-06-28 1981-01-23 Mitsubishi Electric Corp False irregular signal generator
JPS6181223U (en) * 1984-11-02 1986-05-29
JPS6218819A (en) * 1985-07-17 1987-01-27 Fujitsu Ltd Generating circuit for pseudo random pattern
JPS63248242A (en) * 1987-04-03 1988-10-14 Fujitsu Ltd Error generating circuit

Also Published As

Publication number Publication date
JP2531737B2 (en) 1996-09-04

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