JPH0125266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for encoding digital image signals such as binary image signals for facsimile devices.

[Prior art]

Conventionally, facsimile apparatuses have a function of performing facsimile transmission by, for example, modifying read encoding (the modified read code is hereinafter referred to as MR code) of a binary image signal.

By the way, MR encoding is an example of boundary differential encoding that belongs to two-dimensional sequential encoding. information bit,
The run length of each black information bit is calculated to detect signal change points from white to black and from black to white in the reference line image signal, and at the same time, one line of binary image signal (hereinafter referred to The run lengths of the white information bits and black information bits of the encoded line image signal (referred to as the encoded line image signal) are calculated to detect the signal change point of the encoded line image signal, and then the both image signal is detected based on the signal change point information of the encoded line image signal. The encoded line image signal is encoded by calculating the boundary difference between the lines.Next, the principle of MR encoding will be explained with reference to FIGS. 1 to 4.

In Figures 1 to 3, a ₀ is the starting pixel of the encoded line image signal, a ₁ is the first change point pixel to the right of the starting pixel a ₀ of the encoded line image signal, and the starting pixel a ₀ It is the opposite color. _A2 is the next change point pixel of the encoded line image signal to the right of the change point pixel _a1 .

_b1 is the first change point pixel of the reference line image signal, is located to the right of the starting point pixel _a0 , and has the same color as the change point pixel _a1 . _b2 is the next change point pixel of the reference line image signal to the right of the change point pixel _b1 .

In FIGS. 1 to 3, pixel colors are distinguished by diagonal lines and non-diagonal lines.

Figure 1 shows the pixel colors of each change point pixel a ₁ , b ₁ , b ₂ with respect to the starting pixel a ₀ , and the pixels marked with ○ in the reference line image signal in the figure have a different pixel color from the change point pixel a ₁ . Therefore, it is not a change point pixel.

In addition, Fig. 2 shows the case where the change point pixel b ₂ is located to the left of the change point pixel a ₂ , that is, the pass mode (hereinafter referred to as P
).

Further, FIG. 3 shows the case of vertical mode (hereinafter referred to as V) and horizontal mode (hereinafter referred to as H), in which the change point pixel a ₁ or b ₁ is changed from the change point pixel b 1 to the change point pixel a 1 or b ₁ .
or the length up to a ₁ , i.e. the boundary difference described below
When a ₁ b ₁ is 3 or less, it is V, and the boundary difference described above
When a ₁ b ₁ is 4 or more, it is H.

In the case of V, the change point pixel a ₁ is the change point pixel
If it is on the right of b ₁ , it is defined as VR (a ₁ b ₁ ), and conversely, if the change point pixel a ₁ is on the left of change point pixel b ₁ , it is defined as VL (a ₁ b ₁ ).

In addition, in the case of H, the unique code of H (001),
Run length from origin pixel a ₀ to change point pixel a ₁
A code is formed by a ₀ a ₁ and a modified Huffman code (hereinafter referred to as MH code) of the run length a ₁ a ₂ from the change point pixel a ₁ to the change point pixel a ₂ .

Furthermore, the encoded symmetric pixels and codes in each mode are shown in FIG. 4, respectively. In addition, V(0) in the same figure is the change point pixel a ₁ and the change point pixel
b shows the case where ₁ appears at the same time, and M
(a ₀ a ₁ ) and M (a ₁ a ₂ ) each indicate the MH code.

Note that when performing MR encoding of a coded line image signal, for example, if the mode of the previous encoding to the currently performed encoding is P, the current change point pixel _b2 corresponds to The pixel of the encoded line image signal to be encoded is taken as the starting pixel a ₀ , and if the mode at the time of the previous encoding is V, the change point pixel a ₁ at this time is taken as the starting pixel a ₀ , and further , if the mode at the time of the previous encoding is H, the change point pixel _a2 at this time is set as the starting point pixel _a0 .

Therefore, when performing MR encoding, the run length of the reference line image signal is
a ₀ b ₁ , b ₁ b ₂ and the run lengths a ₀ a ₁ , a ₁ a ₂ of the encoded line image signal are respectively calculated, and based on the results of the calculations, the position of the changing point pixel a ₁ and the changing point are calculated. Boundary difference consisting of the difference length from the position of pixel b ₁
It is necessary to calculate a ₁ b ₁ .

Note that since a ₀ b ₁ is determined as the length from the pixel corresponding to the starting pixel a ₀ of the reference line image signal to the change point pixel b ₁ , it is regarded as a run length.

The encoding circuit of the conventional facsimile device is constructed as shown in FIG.
is a reference line memory, which rewrites and holds at least one line's worth of reference line image signals that have been MR encoded. 2 is a reference line shift register that latches the reference line image signal read from memory 1, and has the same number of parallel output terminals as the number of bits of the reference line image signal, and outputs one line's worth of digital signals in parallel. do.

3 is a reference line discriminator to which the register output signal of register 2 is input; it discriminates whether all bits of the input register output signal are white information or black information; for example, if the black information bit is a logic 1
(hereinafter referred to as “1”), the white information bit is logic 0.
(hereinafter referred to as "0"), when all bits of the input register signal are "1", a discrimination signal B of "1" is output, and when all bits of the input register output signal are "0" ”, a discrimination signal W of “1” is output.

4 is an encoding line memory, which contains at least
The encoded line image signal for one line to be MR encoded is rewritten and held. Reference numeral 5 denotes a coding line shift register for latching the coded line picture signal read out from the memory 4, and it has the same structure as register 2 and has the same number of parallel output terminals as the number of bits of the coded line picture signal. and outputs one line of digital signals in parallel.

Reference numeral 6 denotes a coded line discriminator to which the register output signal of register 6 is input, which has the same configuration as discriminator 3 and determines whether all bits of the input register output signal are white information or black information. determine,
For example, if the black information bit is "1" and the white information bit is "0", when all bits of the input digital signal are "1", a discrimination signal B' of "1" is output, and the input digital signal is When all bits of the digital signal are "0", a discrimination signal W' of "1" is output.

7 is a control circuit that performs various arithmetic processing and control processing, and outputs a reference line address signal A to the memory 1 via the reference line address bus 8, and also outputs a code to the memory 4 via the encoded line address bus 9. outputs line address signal A' and clock input terminal of registers 2 and 5.
Shift clock signals Ka and Ka' are output to ck, respectively, and serial bit signals S and S' are output to serial input terminals di of registers 2 and 5, respectively.

10 is a reference line counter that counts the clock signal Kb for run length calculation output from the control circuit 7. By counting the clock signal Kb, it calculates the aforementioned a ₀ b ₁ and b ₁ b ₂ , and also calculates the data. a ₀ b ₁ , to the control circuit 7 via the bus 11
Outputs the calculated value data signal D of b ₁ b ₂ . 12 is an encoded line counter that counts the clock signal Kb' for run length calculation output from the control circuit 7, and calculates the aforementioned a ₀ a ₁ and a ₁ a ₂ by counting the clock signal Kb'. At the same time, the calculated value data signal D' of a ₀ a ₁ and a ₁ a ₂ is output to the control circuit 7 via the data bus 13.

Note that the control circuit 7 includes shift registers 2 and 5.
Signals Q and Q' of the first bit of each register output signal and the clock signal for MR code transmission
Kc is also input.

The registers 2 and 5, the discriminators 3 and 6, the control circuit 7, and the counters 10 and 12 are formed by a microcomputer 14.

Next, the encoding operation shown in FIG. 5 will be explained with reference to FIGS. 6 and 7.

Note that the reference line image signal and the encoded line image signal are composed of 8-bit digital signals,
Assume that the black information bit is set to "1" and the white information bit is set to "0".

First, a reference line address signal A is outputted from the control circuit 7 to the memory 1, a reference line picture signal is read out from the memory 1 to the register 2, and the read reference line picture signal is latched in the register 2.

Next, the encoded line address signal A' is output from the control circuit 7 to the memory 4, the encoded line image signal is read from the memory 4 to the register 5, and the read encoded line image signal is input to the register 5. Latched.

Then, one line of pixels based on the reference line image signal latched in register 2 and one line of pixels based on the encoded line image signal latched in register 5 are arranged, for example, as shown in FIG. 6a. Suppose that

Note that the hatched areas and non-hatched areas in the figure indicate black pixels and white pixels, respectively, and bits, . . . indicate the first to eighth bits of registers 2 and 5, respectively.

Next, the reference line picture signal latched in the register 2 is input to the discriminator 3 from each parallel output terminal of the register 2. At this time, since all bits of the reference line picture signal are not "1" or "0", Both discrimination signals B and W become "0".

Also, the encoded line image signal latched in the register 5 is input to the discriminator 6 from each parallel output terminal of the register 5, and at this time, since all bits of the encoded line image signal are not "1" or "0", ,
Both discrimination signals B' and W' become "0".

Therefore, the discrimination signals B, B', W, and W' of "0" are input to the control circuit 7, and at this time, the signals Q,
Q' is also input to the control circuit 7.

Then, the control circuit 7 changes the starting point pixel a ₀ of the first encoding of the encoded line image signal of _FIG . Furthermore, if the first encoding starting pixel _a0 of the encoded line image signal in FIG. Therefore, it is recognized that the encoded line image signal includes the bit of the black change point pixel _a1 .

Next, when it is recognized that the encoded line image signal includes the " ₁ " bit of the change point pixel a1,
In order to calculate a ₀ b ₁ , the control circuit 7 holds the serial bit signal S at "1" and also outputs the signal Q.
Outputs the clock signal Ka until becomes “1”,
Moreover, the clock signal Kb is output at the output timing of the clock signal Ka.

By the way, every time the clock signal Ka is input, the register 2 transfers the 8th bit signal to the 7th bit, the 7th bit signal to the 6th bit, etc.
The second bit signal is sequentially transferred to the first bit, and the serial bit signal S is latched to the eighth bit.

In the case of Figure 6a, the second clock signal
When Ka is input, signal Q changes from “0” to “1”
At this time, the control circuit 7 detects the change point pixel _b1 and stops outputting the clock signal Ka.

Next, in order to calculate a ₀ a ₁ , the control circuit 7 holds the serial bit signal S' at "1" and turns on the clock signal until the signal Q' becomes "1".
Ka' is output, and a clock signal Kb' is output at the output timing of the clock signal Ka'.

By the way, every time the clock signal Ka' is input, the register 5 transfers the 8th bit signal to the 7th bit, the 7th bit signal to the 6th bit, etc.
The second bit signal is sequentially transferred to the first bit, and the serial bit signal S' is latched to the eighth bit.

In the case of Figure 6a, the fourth clock signal
When Ka' is input, the signal Q' changes from "0" to "1", and at this time the control circuit 7 detects the change point pixel _a1 and stops outputting the clock signal Ka'.

Note that when the signal Q' becomes "1", the signal Q
is held at "1", and at this time, the pixel arrangement based on the counter output signals of registers 2 and 5 becomes as shown in FIG. The point pixel b ₁ and the change point pixel a ₁ of the fifth bit of the encoded line image signal each shift to the first bit.

Furthermore, when the signals Q and Q' both become "1" and the change point pixels a ₁ and b ₁ are detected, the counter 1
0 to the control circuit 7 via the data bus D, a ₀ b ₁
At the same time, the counter 12 outputs the calculated value data signal D' of a ₀ a ₁ to the control circuit 7 via the data bus 13.

Then, the control circuit 7 calculates a boundary difference a ₁ b ₁ from the difference between both data signals D and D'. In this case, two clock signals Ka are output before detecting the change point pixel b ₁ , and the change point Since four clock signals Ka' are output until pixel _a1 is detected, _the calculated boundary difference _a1b1 becomes [2].

Furthermore, based on both data signals D and D', the control circuit 7 recognizes that the change point pixel a ₁ is located to the right of the change point pixel b ₁ .

When the change point pixel _a1 is located to the right of the change point pixel _b1 , the control circuit 7 holds the serial bit signal S at "1" and outputs the clock signal Ka twice,
It is determined whether the encoding mode is P or not depending on whether the signal Q changes from "1" to "0".

That is, since the signal Q when the change point pixel b ₁ is detected is "1" and the change point pixel b ₂ has the opposite color to the change point pixel b ₁ , the clock signal Ka causes the register 2 to be The output signal is sequentially transferred to the first bit side, and the signal Q changes from “1” to “0”.
When the pixel changes to , the change point pixel _b2 is detected.

Furthermore, as described above, the encoding mode becomes P when the change point pixel _b2 is located to the left of the change point pixel _a1 .

Therefore, when the change point pixel a ₁ is located to the right of the change point pixel b ₁ and a ₁ b ₁ is [2], the digital signal of register 2 changes to 1 by the first clock signal Ka.
When the bit shifts to the first bit and the signal Q changes from "1" to "0", the calculated value data D of b ₁ b ₂ is output from the counter 10 to the control circuit 7.
becomes [1], and in this case, the control circuit 7 recognizes that the change point pixel b ₂ is located to the left of the change point pixel a ₁ and identifies that the encoding mode is P.

However, even if the encoded line image signal in FIG. 6a is shifted 2 bits to the left from the pixel arrangement in FIG. Since it does not change to 0'', the control circuit 7
identifies that the encoding mode is not P.

And the encoding mode is not P, and a ₁ b ₁ =
[2] Therefore, the control circuit 7 recognizes that the first encoding mode of the encoded line image signal is VR(2), and starts VR at the timing of the clock signal Kc.
Output the MR code (00001) in (2) serially.

Note that F in the figure indicates an MR code that is serially output.

By the way, in the case of FIG. 6a, since the pixels located at the 6th to 8th bits of the reference line image signal and the pixels located at the 7th and 8th bits of the encoded line image signal are white, As shown in Figure b, the pixel arrangement based on the register output signal of register 2 when change point pixels a ₁ and b ₁ are detected is such that the 4th to 6th bits are white, and the pixel arrangement is based on the digital signal of register 5. In the array, the 3rd and 4th bits are white, and in this case, as described above, when the change point pixels a ₁ and b ₁ are detected, both discrimination signals B,
Both B' become "0".

However, if the pixels located at the third to eighth bits of the reference line image signal and the pixels located at the fifth to eighth bits of the encoded line image signal are all black, then the change point pixel a ₁ , When _b1 is detected, both discrimination signals B and B' become "1".

On the other hand, when the black change point pixels a ₁ and b ₁ are detected and the first encoding of the encoded line image signal is completed,
The pixel color of the starting point pixel a ₀ of the next encoding becomes black, and the pixel color of the change point pixels a ₁ and b ₁ becomes white.

Therefore, if both discrimination signals B and B' are "1" when the black change point pixels a ₁ and b ₁ are detected and the first encoding of the encoded line image signal is completed, the corresponding encoded line The image signal contains the following encoding change point pixels.
It can be recognized that a ₁ and b ₁ do not exist, and in this case, it is possible to move on to encoding the next encoded line image signal after the encoded line image signal concerned.

Therefore, as mentioned above, the first encoding of the encoded line picture signal in FIG. 6a is completed and the VR(2)
When the MR code is output, the control circuit 7 determines whether both determination signals B and B' are both "1".

In the case of the encoded line image signal shown in FIG. It is recognized that there are change point pixels a ₁ and b ₁ for the next encoding, and memory 1,
4, the same reference line address signal A and encoded line address signal A' as in the first encoding are output, respectively.

Then, the two image signals shown in FIG. is changed to a dual image signal.

By the way, the starting pixel a ₀ for the next encoding is
This is a black pixel at the 5th bit position of the encoded line image signal in FIG. 6a, and the change point pixels a ₁ , b ₁
The color of is white.

Therefore, when the contents of the latches in registers 2 and 5 are changed, the control circuit 7 first holds the serial bit signals S and S' at "0" and detects the change point pixel _a1 during the first encoding. The required number of clock signals Ka, Ka' are outputted, respectively, and the pixel arrangement of the digital signals output from the registers 2 and 5 is made into the pixel arrangement shown in FIG. 6c.

In other words, the change point pixel a ₁ at the time of first encoding
Then, the pixel arrangement is such that the pixel of the reference line image signal corresponding to the pixel _a1 is transferred to the first bit of the registers 5 and 2.

Next, in order to calculate a ₀ b ₁ as in the first encoding, the control circuit 7 holds the serial bit signal S at "0" and changes the signal Q from "1" to "0".
The clock signal Ka is outputted until the change point pixel _b1 is detected, and the clock signal Kb is outputted at the output timing of the clock signal Ka.

In the case of FIG. 6c, the signal Q changes from "1" to "0" when the first clock signal Ka is output, and at this time the control circuit 7 stops outputting the clock signal Ka.

Next, in order to calculate a ₀ a ₁ , the control circuit 7 holds the serial bit signal S' at "0" and outputs the signal.
Until Q' changes from "1" to "0", that is, until the change point pixel _a
Ka', and also outputs a clock signal Kb' at the timing of the clock signal Ka'.

In the case of FIG. 6c, when the second clock signal Ka' is output, the signal Q' changes from "1" to "0", and at this time, the control circuit 7 outputs the clock signal Ka'. Stop.

After stopping the output of the clock signal Ka',
The control circuit 7 takes in the calculated value data signals D and D' of a ₀ b ₁ and a ₀ a ₁ of the counters 10 and 12 and calculates the boundary difference.
In this case, since _{a 0 b 1} is [1] and a ₀ a ₁ is _[ 2], the control circuit 7 calculates [1] as the boundary difference a ₁ b ₁ , and Since the change point pixel a ₁ is located to the right of the change point pixel b ₁ , it is recognized that the encoding mode is VR (1), and the MR code (011) of VR (1) is recognized at the timing of the clock signal Kc. )
output serially.

Furthermore, when the output of the MR code of VR(1) is finished,
The control circuit 7 further starts the next encoding.

By the way, the starting pixel a ₀ for the next encoding is
This becomes the change point pixel a ₁ in the second encoding of the encoded line image signal in FIG. 6a, that is, the white pixel of the third bit in FIG. 6c, which is the change point pixel a ₁ in the aforementioned encoding.

Then, when the output of the MR code of VR(1) is finished,
The control circuit 7 determines whether both discrimination signals W and W' are "1", that is, whether black change point pixels a ₁ and b ₁ exist.

When the output of the MR code of VR(1) is completed, the pixel array based on the counter output signals of registers 2 and 5 is an all-white pixel array as shown in Figure 6d, so both discriminations are possible. Both the signals W and W' become "1", and in this case, the control circuit 7 recognizes that the change point pixels a ₁ and b ₁ do not exist in the counter output signals of the registers 2 and 5.

Furthermore, when it is recognized that the change point pixels a ₁ and b ₁ do not exist, the control circuit 7 controls the change point pixel a ₁ at the time of the second encoding, that is, the encoded line image signal of FIG. 6a. The remaining number 2 (=8-6), which is the number of pixels remaining from the 7th bit pixel, is counted as counter 1.
It is held at 0,11.

That is, the starting pixel _a0 at the time of the first encoding of the encoded line image signal following the encoded line image signal of FIG. 6a becomes the pixel of the 7th bit of FIG. The first encoding of the line image signal
For calculations such as a ₀ b ₁ , a ₁ a ₂ , M (a ₀ a ₁ ), etc., the aforementioned remaining number 2 is held in the counters 10 and 11.

When the remaining number 2 is held in the counters 10 and 11, the control circuit 7 finishes encoding the encoded line image signal shown in FIG.
4, a reference line address signal A and an encoded line address signal A' for reading out the next reference line image signal and encoded line image signal are output, respectively, and are transferred from the memories 1 and 4 to the registers 2 and 5.
The next encoded line image signal and the encoded line image signal in FIG. 6a are respectively held in FIG.
The newly encoded line image signal held in the register 5 is encoded by the same operation as in the case of the encoded line image signal.

Note that when encoding the next encoded line image signal after the encoded line image signal in FIG. 6a, the encoded line image signal in FIG. The encoded line image signal in the memory 5 is transferred to the memory 1 every time encoding is completed.

Thereafter, by repeating the same operation, the encoded line image signal of each line is sequentially encoded into an MR code.

By the way, if the reference line image signals and encoded line image signals read out from memories 1 and 4 have exactly the same pixel arrangement, that is, the contents are the same, as shown in FIG. 7, then a ₁ b ₁ will always be 0. The MR code of the encoded line image signal is a series of V(0), and the MR code of V(0) is generated at the timing of the clock signal Kc.
(1) is output continuously.

When V(0), a ₁ b ₁ becomes the shortest and the MR code becomes 1 bit. Therefore, unless encoding is performed at high speed, the MR code of V(0) is sequentially encoded at the timing of the clock signal Kc. This results in a so-called transmission delay.

In other words, unless the time required for encoding when V(0) is reduced to 1/3 of the time required for encoding when using a 3-bit MR code such as VR(1) or VL(1), the aforementioned transmission delay will occur. occurs.

However, in the case of FIG. 5, when encoding, first calculate a ₀ b ₁ , b 1 b ₂ from the reference line image signal, and then calculate a ₀ a 1 , b ₁ b ₂ from the encoded line image signal.
It is necessary to calculate a ₁ a _{2 ,} and then calculate a ₁ b 1 from the calculation results of a ₀ b ₁ , b ₁ b ₂ and the calculation results of a ₀ a ₁ , a ₁ a ₂ , and V(0 ), it is necessary to perform similar calculations, so the time required for encoding becomes longer.

As shown in Figure 7, when the contents of both image signals are the same and the encoding outputs V(0) MR codes continuously, a transmission delay occurs because encoding cannot be performed at high speed. .

[Purpose of the invention]

The present invention has been made with the above-mentioned points in mind, and it speeds up the encoding when the contents of the encoded digital image signal and the digital image signal to be encoded are the same, thereby achieving high-speed encoding. The purpose is to make it possible to do so.

[Structure of the invention]

The present invention calculates the run length of a digital image signal that has been encoded for one unit, and the run length of the digital image signal that is to be encoded for the next one unit of the encoded digital image signal. In addition, in the encoding method in which the digital image signal to be encoded is encoded by calculating a boundary difference between the two digital image signals based on the calculation result, when the contents of the two digital image signals are equal, the boundary difference between the two digital image signals is calculated. An encoding method characterized in that the digital image signal to be encoded is encoded by generating a predetermined code when detecting a change point in either of the digital image signals without calculating a difference. be.

〔Effect of the invention〕

Therefore, according to the encoding method of this invention,
When the contents of the digital image signal that has been encoded and the digital image signal to be encoded are the same, a predetermined code is generated by only detecting the change point of either one of the two digital image signals, without calculating the boundary difference. can be generated and encoded at high speed.

〔Example〕

Next, this invention will be explained in detail with reference to FIG. 8 showing one embodiment thereof.

In FIG. 8, the same symbols as in FIG. 5 indicate the same or equivalent things. “0”
In addition to providing a comparator 15 that outputs a detection signal N of "1", the calculation of a ₀ b ₁ and b ₁ b ₂ from the reference line image signal is omitted when the detection signal N of "1" is input to the control circuit 7. This is because we have added a function to do this.

If the reference line image signal read out from the memory 1 to the register 2 and the encoded line image signal read out from the memory 4 to the register 5 have the pixel arrangement shown in FIG. If the contents are not equal, a coincidence detection signal N of "0" is output from the comparator 15 to the control circuit 7. At this time, the control circuit 7 operates in the same manner as in the case of FIG. 5, and first a ₀ b ₁ , Calculate b ₁ b ₂ , then a ₀ a ₁ , a ₁ a ₂
is calculated, and a ₁ b ₁ is calculated from the results of both calculations to encode the encoded line image signal.

On the other hand, if the reference line image signal read out from memory 1 to register 2 and the encoded line image signal read out from memory 4 to register 5 have the pixel arrangement shown in FIG. If the contents are equal, the comparator 15 to the control circuit 7
A coincidence detection signal N of "1" is output at this time, and at this time, the control circuit 7 recognizes that the contents of both picture signals are equal and controls the operation of only the register 5 and the counter 12, and detects the change point of the encoded line picture signal. Encoding is performed based on the detection of .

That is, when a detection signal N of "1" is input,
In the case of FIG. 8, since the starting pixel _a0 of the first encoding of the encoded line image signal is white, first, the serial bit signal S' is set to "0" and the signal Q' changes from "0" to "1". The clock signal Ka′ is output until it changes to ”, and
Also, it outputs a clock signal Kb' at the timing of the clock signal Ka'.

Then, the signal Q' changes from "0" to "1" and the counter 12 outputs the calculated value data signal D' of a ₀ a _1. When the first changing point is detected, the control circuit 7 changes the clock signal V(0) at the timing of Kc
Output the MR code serially and finish the first encoding.

Next, when the first encoding is completed, the control circuit 7 determines whether the discrimination signals B', W' are "1" or not, that is, the pixel array based on the output signal of the register 5 is all white or black. If the discrimination signals B' and W' are both "0",
It is recognized that there remains content to be encoded in the register output signal of register 5, and the next encoding is started.

By the way, in the next encoding, the second
Since the black pixel at the bit position becomes the starting pixel _a0 , the serial bit signal S' is set to "1" and the signal is
Clock signal Ka' is output until Q' changes from "1" to "0", and clock signal Kb' is output at the timing of clock signal Ka'.

Then, the signal Q' changes from "1" to "0" and the counter 12 outputs the calculated value data signal D' of a ₀ a _1. When the next changing point is detected, the control circuit 7 Clock signal as in encoding
The MR code of V(0) is output serially at the timing of Kc.

Thereafter, the same operation as described above is repeated until the discrimination signal B' or W' becomes "1", and the encoding of the encoded line image signal is completed.

Therefore, according to the embodiment, when the contents of both picture signals are equal, only the register 5 and the counter 12 are controlled, and the boundary difference is calculated based on the detection of the change point of the encoded line picture signal. The encoded line image signal can be encoded without any transmission delay, and the encoding speed is significantly increased, so that even when V(0) MR codes are consecutive as shown in Fig. 7, encoding can be performed without transmission delay. be able to.

Further, since it is only necessary to add the comparator 14 to the conventional circuit and to slightly change the contents of the control circuit 7, the present invention can be realized by adding a simple circuit.

In the above embodiment, only the register 5 and the counter 12 are operated and the encoding is performed based only on the detection of the change point of the encoded line image signal.
The same effect can be obtained by controlling the operation of only the reference line image signal and performing encoding based only on detecting the change point of the reference line image signal.

In addition, in the above embodiment, the MR of the facsimile machine
Although the present invention is applied to encoding, it is of course applicable to boundary differential encoding other than MR encoding of various digital image signals.

[Brief explanation of drawings]

1 to 4 are diagrams explaining the principle of MR encoding, FIG. 5 is a block diagram of a conventional encoding circuit, and FIG. 6 and subsequent drawings show an embodiment of the encoding method of the present invention. 6A to 6D and FIG. 7 are explanatory diagrams of the pixel arrangement, respectively, and FIG. 8 is a block diagram of the encoding circuit. 1, 4... Reference line memory, encoded line memory, 2, 5... Reference line shift register, encoded line shift register, 3, 6... Reference line discriminator, encoded line discriminator, 7... Control Circuits 10, 12... Reference line counter, encoded line counter, 15... Comparator.

Claims (1)

[Claims] 1 Calculate the run length of the digital image signal for which one unit of encoding has been completed and the run length of the digital image signal for one unit after the encoded digital image signal, and calculate the run length of the digital image signal for one unit of the encoded digital image signal, and Originally, in an encoding method in which the digital image signal is encoded by calculating the boundary difference between the two digital image signals, when the contents of the two digital image signals are equal, the boundary difference between the two digital image signals is calculated, and the boundary difference between the two digital image signals is calculated. An encoding method comprising: generating a predetermined code when detecting a change point in either one of the digital image signals, and encoding the digital image signals.