JPH01251977A - Digital acc circuit - Google Patents

Abstract

PURPOSE:To reduce the number of bits by executing an ACC operation by previously switching the gain of an input chrominance signal while giving hysteresis characteristics. CONSTITUTION:Plural chrominance signals having different amplification degrees with each other are previously generated before the gain of an input chrominance signal 201 is controlled by using a gain control signal 209 having information, the amount of which is the same as that of the burst amplitude of the input chrominance signal 201. Further, when one chrominance signal out of these chrominance signals is selected, and the gain is controlled, the chrominance signal is selected by a selecting signal 206 from a selecting control circuit 218, which has the hysteresis characteristics and operates based on the gain control signal 209, in order to enlarge an operating range for an ACC. Consequently, the gain of the chrominance signal of a preceding step in a multiplier 208 can be previously switched even when the burst amplitude of the input chrominance signal 201 at an initial stage is large or small, and a gain adjusting range necessary for the multiplier 208 can be reduced. Thus, the number of the bits for the multiplier can be decreased.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a digital ACC related to a digital television receiver that digitally processes a baseband video signal.
Regarding circuits.

(Prior art) In order to prevent variations in color signal gain (color density on the screen) caused by variations in received radio waves, mismatch in the antenna system, etc.
Conventional television receivers incorporate an ACC circuit that automatically keeps the gain of color signals constant.

The ACC circuit extracts the color burst part of the color signal,
The amplitude of the color burst is detected, and based on this, the color signal is multiplied by a certain gain coefficient to keep the gain of the color signal output to the subsequent stage constant. That is, the ACC circuit performs a negative feedback operation such that if the color burst amplitude is larger than a certain level, the gain coefficient applied to the color signal is reduced, and if the color burst amplitude is smaller than a certain level, the gain applied to the color signal is increased. Consists of loops.

FIG. 5 shows an example of a conventional digital ACC circuit. The digital color signal 101 input to the digital ACC circuit 100 is multiplied by a gain control signal 109 in a multiplier 102 to keep the gain of the output color signal 103 constant. Burst integration circuit 104. Comparator 10
7. The closed loop formed by the up/down counter 108 is a negative feedback loop that performs ACC operation. This closed loop will be explained below.

A color signal 101 is supplied to a multiplier 102, which is multiplied by a gain control signal 109 output from an up/down counter 108, and a burst portion of the 0 color signal 103 from which a color signal 103 is obtained as an output is subjected to burst integration. circuit 1
04 in the burst sampling circuit 105 and further integrated in the integrating circuit 106. This burst integral value is compared with a reference value ref1 in a comparator circuit 107. The comparison result is input to the up/down counter 108, but
The operation of the up/down counter 108 is as follows.

In the comparator 107, the burst integral value is base 1! value ref
When the value is less than 1, the up/down counter 108 operates up. When the burst integral value is equal to the reference value ref1, the up/down counter 108 holds its output. When the burst integral value is greater than the reference value ref1, the up-down counter 108 operates down. The gain of the output color signal 103 is kept constant.

FIG. 6(a) shows the input/output characteristics representing the relationship between the burst amplitude of the input color signal 101 and the burst amplitude of the output color signal 103. This figure shows that the burst width of the input color signal 101 is smaller than the specified amplitude <IV, , the automatic color control (ACC) operation is performed until the magnitude is -12 dB for a burst amplitude of 0.3 V in the video signal of , and at that time, the burst amplitude of the output color signal 103 is B1
Normally, the ACC operating range is the range in which the output burst amplitude is always constant regardless of the size of the input cover burst@width. FIG. 6(b) shows the relationship between the input color signal and the ACC gain (gain control signal).

By the way, this A required for a television set
The CC operating range is quite wide, and its value is often -10 dB to -15 dB with respect to the specified burst amplitude. Therefore, the gain of the chrominance signal must be controlled over a wide range, and the multiplier 102 The 0 multiplier, which requires a large number of bits, requires approximately 100 gates in hardware for each additional bit of input bits. However, cost was also an issue.

(Problems to be Solved by the Invention) As described above, in the conventional digital ACC circuit, in order to keep the gain of the output color signal constant over a wide range, it is necessary to increase the number of bits in the multiplier.

Therefore, an object of the present invention is to provide a digital ACC circuit that can perform a wide range of gain control unlike the conventional one while suppressing the number of bits of the multiplier to the necessary minimum (the number of bits that does not affect image quality). do.

[Structure of the Invention] (Method PM for Solving the Problems) This invention provides a method for controlling the gain of an input chrominance signal in advance using a gain control signal having information on the magnitude of the burst amplitude of the input chrominance signal. When a plurality of color signals with different amplification degrees are created and a color signal among these is selected for gain control, in order to expand the ACC operating range, a color signal having a hysteresis characteristic and based on the gain control signal is used. The color signal is selected by a selection signal from an operating selection control means.

(Function) With the above means, even if the burst amplitude of the initial input color signal is large or small, the color signal gain before the multiplier can be switched in advance, and the gain adjustment range originally required by the multiplier can be changed. It can be reduced. Therefore, the number of bits of the multiplier can be reduced, leading to cost reduction.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a digital color signal 201 is supplied as an input signal. This color signal 201 is input to a gain adjustment circuit 202, doubled by an amplifier 203 using bit shifting means, and then sent to a limiter circuit 204.
The signal is amplitude-limited and supplied to multiplexer 205, and is also directly input to multiplexer 204. The multiplexer 205 selects one of the color signals according to the selection signal 206 from the flip 70 tube 220 and supplies it to the multiplier 208. The 1 multiplier 208 receives the gain control signal 209 and outputs the color signal 210.

The color signal 210 is guided to a burst integration circuit 211. First, in the burst extraction circuit 212, the color signal 2
Ten burst portions are extracted, and an integration circuit 213 integrates the burst portions. The burst integral output is compared with a reference value ref1 in a comparator 214, and the comparison result is supplied to an up/down counter 216 provided in a time constant circuit 215. This up/down counter 216 uses a gain control signal 2 with a certain time constant.
09 to the multiplier 208, and the selection signal 20
6 to a selection control circuit 218 which generates 6.

The multiplier 208. Burst integration circuit 211° comparator 2
14 and the up/down counter 216 is an ACC loop and has the characteristics shown in FIG. 2(a). FIG. 2(a) shows the input color signal 201 and the output color signal 2.
Burst fiI with 10! It shows the relationship between When the burst vibration of the input color signal 201 is 112 dB or more, the amplitude of the output color signal 210 is 81 (standard burst level)
Indicates that it is maintained.

The gain control signal 209 is supplied to the selection control circuit 218 together with the ripple carry 221 of the up/down counter 216. The ripple carry 221 is a signal that indicates information when the output 209 of the up/down counter 216 is all 1.
19 and a flip 70 tube 220. The gain control signal 209 is compared with a reference value rllllf2 by a comparator 219, and when the magnitude of the gain control signal 209 is less than or equal to the reference value refz, the comparator 219 outputs a signal indicating this. Ripple carry 221 above
The comparator 219 output is supplied to the set and reset inputs of the flip-flop 220, and operates as follows.

In this embodiment, when the ripple carry 221 is output as a pulse, the multiplexer 205 outputs the limiter 2
04, the multiplexer 217 selects the reference value ACC2 shown in FIG. 2(b), and sets the output 209 of the up/down counter 216 to the value of ACC2. Conversely, when a pulse is output from the comparator output, the multiplexer 205 selects the input color signal 201, the multiplexer 217 selects the value of the reference value ACC1 shown in FIG. 2(b), and the value of the output 209 of the up/down counter. A
Set to CCl. The purpose of setting the output of the up/down counter 216 is to make the difference between the selection switching time in the multiplexer 205 and the time when the value of the gain control signal 209 switches as short as possible, and to reduce the period during which the system is unstable.

As a result of the above operations, the gain control signal is as shown in Figure 2 (b
For example, when the burst amplitude of the input color signal 201 changes from a value of 112 dB to the specified burst amplitude, the gain control signal gradually decreases (see Fig. 2(b)). When the curve A) reaches the reference value ref2 at the comparator 219, it shifts to the curve B in FIG. 2(b), further decreases on the curve B, and stabilizes at a certain value.

Conversely, when the burst amplitude of the input color signal 201 changes from the specified burst amplitude to a burst amplitude around -12 dB, the gain control signal 209 rises on curve B in FIG. 2(b), and the gain control signal Maximum of 209 (MAX)
A pulse is generated in the triple carry 221 that reaches the value, shifts to curve A, further rises on curve A, and stabilizes at a certain value. By having the hysteresis characteristic in this way, even if a color signal with a burst amplitude that fluctuates slightly near the transition between curve A and curve B is input, this ACC loop system will not operate unstablely. As a result, the ACC characteristics of the entire circuit are obtained as shown in FIG. 4(a).

Furthermore, the series of operations shown in FIG. 2(b) expands the dynamic range of the gain control signal 209, that is, the gain variable width, without increasing the number of bits of the multiplier. In digital signal processing, it is very important to make effective use of the word length of the signal, that is, the number of bits, from the standpoint of both preventing an increase in quantization noise and reducing the amount of hardware, and the present invention has great effects in this regard. ing.

FIG. 3 shows another embodiment of the invention. In the case of this embodiment, the basic operation is the same as in the previous embodiment, and the same parts as in the previous embodiment are denoted by the same reference numerals, and the explanation thereof will be omitted.

The input color signal 201 is not only doubled by the amplifier 203 in the gain adjustment circuit 202 but also quadrupled by the amplifier 301 and supplied to the multiplexer 205 . Further, the burst integral value is subtracted from the reference value ref by the error detection circuit 302 by the subtracter 303. The error signal that is the output of the error detection circuit 302 is supplied to the loop gain coefficient unit 305 of the time constant circuit 215, and is sent to the adder 306 and the latch circuit 307.
9 time constant circuits integrated by an integrator circuit composed of 21.
5 outputs this integration result as a gain control signal 209 and is supplied to a multiplier 208 and a selection control circuit 218.

The gain control signal 209 is transmitted to the comparator 30 of the selection control circuit 218.
9,308, and in each comparator
Reference value r13f2 and gain control maximum value A shown in (b)
Compare with CCMAX. The comparator 309 outputs a pulse when the gain control signal 209 is equal to or less than the reference value ef2.The comparator 308 outputs a pulse when the gain control signal 209 is equal to or greater than the maximum gain control value ACCHAX. The signal is supplied to a 2-bit up/down counter 310. The up/down counter 310 counts up the gain control signal 209 above the maximum gain control value ACCNAXCCN, and counts down when the gain control signal 209 is equal to or less than the reference value "ef2."

In this embodiment, the selection signal 206 output from the up/down counter 310 takes only three values and controls the selection operation of the multiplexer 205. For example, the selection signal 206 is (H3B, LSB) = (0, 0). (0,1)
If we assume three values (1, 0), multiplexer 20
The output of 5 is (H3B, LSB) = (0,0)
When the input color signal 201 is selected, (H3B, LS
When B) = (0,1), the output of amplifier 203 is selected, and when (83B, LSB) = (1,0), the output of amplifier 30 is selected.
1 output is selected. Also, up/down counter 31
When the up/down counter 310 counts up, the set signal 311 output from 0 is sent to the "4th" multiplexer 217 in the time constant circuit 215.
Select the reference value ACC2 shown in Figure (b) and latch 307
The gain control signal 209 which is the output of is set to the reference value Acc2. When the up/down counter 310 counts down, the set signal 311 selects the reference value ACC shown in FIG. 4(b) in the multiplexer 217, and sets the output 209 of the latch 307 to ACCl.

As a result of the above operation, the gain control signal 209 has a hysteresis characteristic as shown in FIG. 4(b), so that the ACC characteristic shown in FIG. 4(a) is obtained for the entire circuit. That is, in this embodiment, a plurality of level portions with hysteresis characteristics are formed compared to the previous embodiment, and the ACC operating range can be expanded accordingly without increasing the number of bits of the multiplier. According to the conventional method, the wider the ACC operating range, the more bits are required.
The advantages of the present invention increase as the operating range of the ACC is expanded.

Note that the embodiments listed here are only a part of the embodiments of the present invention, and many others can be considered. The burst integrator circuit 211 and the error detection circuit 302 can be combined, and even if the integrator circuit 213 and the error detection circuit are replaced, the performance will not change.Also, since the time constant circuit 215 performs an integral operation, the integrator circuit 213
may be incorporated into the time constant circuit 215.

[Effects of the Invention] As explained above, the present invention performs the ACC operation by switching the gain of the input color signal in advance while providing hysteresis characteristics, so the number of bits can be reduced compared to the conventional digital ACC circuit, and the number of bits can be reduced compared to the conventional digital ACC circuit. Contributes to hardware reduction and cost reduction. Further, by having a hysteresis characteristic, even if an input signal having an amplitude that causes gain switching is input, unstable operation due to a switching signal does not occur.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of this invention, Fig. 2 is a characteristic diagram shown to explain the circuit operation of Fig. 1, and Fig. 3 is a circuit diagram showing another embodiment of this invention. , FIG. 4 is a diagram showing the circuit characteristics of FIG. 3, FIG. 5 is a diagram showing a conventional ACC circuit, and FIG. 6 is a diagram of the circuit characteristics of FIG. 202...Gain adjustment circuit, 203.301...Amplifier, 205...Multiplexer, 204,207...
- Limiter, 208... Multiplier, 211... Burst integration circuit, 214... Comparator, 302... Error integrator, 215... Time constant circuit, 218... Selection control circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] The first chromaticity signal constituting the digital video signal has 2^m
(m is an integer) a gain adjustment circuit that outputs a plurality of chromaticity signals multiplied by different gains, and a selection that selects only one from the plurality of chromaticity signals and outputs it as a second chromaticity signal. a multiplier that multiplies the second chromaticity signal and the automatic gain control signal to output a gain-adjusted third chromaticity signal; and extracts a color burst signal portion from the third chromaticity signal. a burst integrating circuit that integrates the amplitude of the sampled color burst signal and outputs it as a burst integral value signal; and a burst integral circuit that receives the burst integral value signal and an integral target value as input and reduces the difference between the burst integral value signal and the integral target value. a time constant circuit that outputs the automatic gain control signal with an arbitrary time constant to increase the ACC operation; and a selection control circuit that supplies the time constant circuit.