JPH01251784A - Manufacture of wiring board - Google Patents

Manufacture of wiring board

Info

Publication number
JPH01251784A
JPH01251784A JP63078383A JP7838388A JPH01251784A JP H01251784 A JPH01251784 A JP H01251784A JP 63078383 A JP63078383 A JP 63078383A JP 7838388 A JP7838388 A JP 7838388A JP H01251784 A JPH01251784 A JP H01251784A
Authority
JP
Japan
Prior art keywords
electroless
plating
resist
electroless plating
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63078383A
Other languages
Japanese (ja)
Inventor
Hiroshi Takahashi
宏 高橋
Toshiro Okamura
岡村 寿郎
Shin Takanezawa
伸 高根沢
Yorio Iwasaki
順雄 岩崎
Masao Sugano
雅雄 菅野
Akishi Nakaso
昭士 中祖
Kiyoshi Hasegawa
清 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP63078383A priority Critical patent/JPH01251784A/en
Priority to EP89302794A priority patent/EP0335565B1/en
Priority to DE68916085T priority patent/DE68916085T2/en
Priority to KR1019890003938A priority patent/KR920002276B1/en
Publication of JPH01251784A publication Critical patent/JPH01251784A/en
Priority to US07/970,925 priority patent/US5309632A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0236Plating catalyst as filler in insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0344Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0709Catalytic ink or adhesive for electroless plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1407Applying catalyst before applying plating resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1415Applying catalyst after applying plating resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H05K3/387Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive for electroless plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To suppress insulation degradation due to electric erosion by including a material having small ingredient migration due to electric fields between copper which is a wiring conductor and an insulation board. CONSTITUTION:An adhesive layer contained a catalyzer for electroless plating is formed on the surface of an insulating board containing a catalyzer for electroless plating. A hole to be used as a through hole is bored. A resist for electroless plating is formed on a portion except the through hole and a portion to become a circuit section. It is immersed in a chemically roughening liquid and the surface of the portion where resist for electroless plating is not formed is selectively roughened. As a first metal layer, a layer of a combination of one or more kinds selected from among electroless nickel alloys, electroless cobalt alloys, electroless palladium and electroless gold is formed on a portion where resist for electroless plating is not formed. It is immersed in an electroless copper plating and a copper plating layer is formed on the first metal layer.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、耐電食性に優れた無電解めっき方法に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an electroless plating method with excellent electrolytic corrosion resistance.

(従来の技術) 配線板として、経済的に優れた製造方法として無電解め
っきを析出させるためにパラジウム等の無電解めっき用
触媒を含有する接着剤層を表面に形成しその中にも同様
の無電解めっき用触媒を含有する絶縁板に回路部となる
べき箇所以外の部分に無電解めっき用レジストを設はク
ロム酸等の化学粗化液に浸漬してレジストが形成されて
いない箇所の表面を選択的に粗化し無電解めっき液に浸
漬して回路パターンを形成するいわゆるアディティブ法
がある。
(Prior art) As an economically superior manufacturing method for wiring boards, an adhesive layer containing an electroless plating catalyst such as palladium is formed on the surface to deposit electroless plating. If a resist for electroless plating is applied to parts of an insulating plate containing a catalyst for electroless plating other than the parts that should become circuit parts, the surface of the parts where no resist is formed is immersed in a chemical roughening solution such as chromic acid. There is a so-called additive method in which a circuit pattern is formed by selectively roughening the material and immersing it in an electroless plating solution.

(発明が解決しようとする課題) 近年、電子機器の小型化、軽量化に伴い、配線板には配
線の高密度化が要求され、そのために配線板の両面の回
路導体を接続するためのスルーホールを設ける間隔を狭
めたり配線のための導体の幅を狭めたりしている。この
ような高密度の配線板においては、異なった電位の導体
が近接し、長時間の間にその導体を支持している絶縁板
の表面で異なった電位の導体の間にある領域で、イオン
性不純物による銅の移行(マイグレーション)のためか
あるいはアディティブ法による配線板の製造工程の各種
処理液による影響を受けるためか、多湿の条件下におい
てデンドライトと呼ばれる樹枝状の銅化合物が形成され
ることがある。このデンドライトは、同様の条件下にお
いて次第に成長し、最終的には導体間を短絡させるに至
る。
(Problem to be Solved by the Invention) In recent years, as electronic devices have become smaller and lighter, wiring boards are required to have higher wiring density. The spacing between holes is being narrowed, and the width of conductors for wiring is being narrowed. In such a high-density wiring board, conductors with different potentials are in close proximity, and over a long period of time, ions are generated in the area between the conductors with different potentials on the surface of the insulating board that supports the conductors. Under humid conditions, dendritic copper compounds called dendrites are formed, either due to the migration of copper due to sexual impurities or due to the effects of various processing solutions in the additive manufacturing process of wiring boards. There is. This dendrite gradually grows under similar conditions and eventually leads to a short circuit between the conductors.

したがって、従来のアディティブ法においては、導体の
間隔を0.15mm以下にすることができず、配線の高
密度化を行うには導体の幅のみを狭めなければならず、
配線密度を高める上で障害となっていた。
Therefore, in the conventional additive method, it is not possible to reduce the distance between conductors to 0.15 mm or less, and in order to increase the density of wiring, only the width of the conductor must be reduced.
This has been an obstacle to increasing wiring density.

本発明は、この電食による絶縁劣化の抑制に優れた無電
解めっき方法を提供するものである。
The present invention provides an electroless plating method that is excellent in suppressing insulation deterioration due to electrolytic corrosion.

(課題を解決するための手段) 本発明は、以下に示す工程よりなる配線板の製造方法で
ある。
(Means for Solving the Problems) The present invention is a method for manufacturing a wiring board, which includes the steps shown below.

a、無電解めっき用触媒を含む絶縁基板表面に無電解め
っき用触媒を含む接着剤層を形成する。
a. An adhesive layer containing a catalyst for electroless plating is formed on the surface of an insulating substrate containing a catalyst for electroless plating.

b、スルーホールとなる穴をあける。b. Drill a hole that will become a through hole.

c.スルーホールと回路部となるべき部分以外の箇所に
無電解めっき用レジストを形成する。
c. A resist for electroless plating is formed in areas other than the through holes and the portions that will become circuit parts.

d、化学粗化液に浸漬し、無電解めっき用レジストが形
成されていない箇所の表面を選択的に粗化する。
d. Immerse in a chemical roughening solution to selectively roughen the surface where the electroless plating resist is not formed.

e、無電解めっき用レジストが形成されていない箇所に
第1の金属層として、無電解ニッケル合金、無電解コバ
ルト合金、無電解パラジウム又は無電解金のうちの1種
又は2種以上の組み合わせによる層を形成する。
e. As the first metal layer in areas where the resist for electroless plating is not formed, one or a combination of two or more of electroless nickel alloy, electroless cobalt alloy, electroless palladium, or electroless gold is used. form a layer.

f、無電解銅めっき液に浸漬し、第1の金属層の上に銅
めっき層を形成する。
f. Immerse in electroless copper plating solution to form a copper plating layer on the first metal layer.

すなわち、本発明においては、配線導体である銅と絶縁
基板との間に、電界による成分の移行の少ない物質を介
在させることによってこのデンドライトに関する問題を
解決使用とするものである。
That is, in the present invention, the problem related to dendrites is solved by interposing a substance whose components are less likely to migrate due to an electric field between copper, which is a wiring conductor, and an insulating substrate.

工程aにおいて、本発明に用いることのできる絶縁基板
としては、紙基材フェノール樹脂積層板、紙基材エポキ
シ樹脂積層板、ガラス布エポキシ樹脂積層板、又は、ガ
ラス布ポリイミド樹脂積層板等があり、この樹脂中に無
電解めっき用触媒であるパラジウム、白金、ロジウム等
を含有させた絶縁基板を用いる。市販品としては、LE
−168、LE−144(日立化成工業株式会社、商品
名)等がある。
In step a, insulating substrates that can be used in the present invention include paper-based phenolic resin laminates, paper-based epoxy resin laminates, glass cloth epoxy resin laminates, or glass cloth polyimide resin laminates. , an insulating substrate containing palladium, platinum, rhodium, etc., which are catalysts for electroless plating, is used in this resin. As a commercially available product, LE
-168, LE-144 (Hitachi Chemical Co., Ltd., trade name), etc.

接着剤としては、NBRを主成分とするもの、NBRと
クロロスルフォン化ポリエチレンを主成分とするもの、
又は、エポキシ樹脂を主成分とするものが使用でき、こ
れに無電解めっき用触媒であるパラジウム、白金、ロジ
ウム等を含有させ、充填剤として珪酸ジルコニウム、シ
リカ、炭酸カルシウム又は水酸化アルミニウム等を混合
したものも使用できる。
Adhesives include those whose main components are NBR, those whose main components are NBR and chlorosulfonated polyethylene,
Alternatively, epoxy resin as a main component can be used, which contains palladium, platinum, rhodium, etc. as a catalyst for electroless plating, and is mixed with zirconium silicate, silica, calcium carbonate, aluminum hydroxide, etc. as a filler. You can also use the

工程すにおいて、スルーホールとなる穴は、パンチ、ド
リル等、通常、配線板の穴あけに用いられる装置であれ
ばどのようなものでももちいることができる。
In the process, any device, such as a punch or drill, which is normally used for making holes in wiring boards, can be used to form the holes that will become through holes.

工程Cにおいて形成する無電解めっき用レジストとして
は、光硬化による樹脂をフィルム状にした紫外線硬化型
レジストフィルムや、紫外線硬化型レジストインク、熱
硬化型レジストインク等をスクリーン印刷法によって塗
布できるもの等が使用でき、後述の無電解ニッケルめっ
き液、銅めっき液及びその前処理液等工程中に用いる化
学液とその使用条件において、剥離等の発生しないもの
であればどのようなものでも用いることができる。
The resist for electroless plating formed in Step C includes an ultraviolet curable resist film made of a photocurable resin, an ultraviolet curable resist ink, a thermosetting resist ink, etc. that can be applied by screen printing. Any chemical solution and usage conditions used during the process, such as the electroless nickel plating solution, copper plating solution, and its pretreatment solution described below, can be used as long as it does not cause peeling or the like. can.

工程dにおいて、レジストが形成されていない部分の表
面を選択的に粗化する粗化液としては、通常アディティ
ブ法配線板の製造に用いることができる化学粗化液、例
えば、クロム酸−硫酸混合液、クロム酸−棚部酸混合液
等が使用できる。
In step d, the roughening liquid that selectively roughens the surface of the portion where the resist is not formed is a chemical roughening liquid that can be normally used in manufacturing additive method wiring boards, such as a chromic acid-sulfuric acid mixture. liquid, chromic acid-tracebe acid mixed liquid, etc. can be used.

工程eにおいて、第1の金属層を形成するための無電解
めっき液としては、ニッケル、ニッケル/タングステン
合金、ニッケル/コバルト合金、コバルト、コバルト/
タングステン合金、パラジウム、又は金をめっきできる
ものであれば特に限定するものではなく、通常の次亜リ
ン酸塩を還元剤とするリン含有又は硼素を含有するめっ
き液、例えば、ニッケルの場合では市販品として、ブル
ーシューマ(日本カニゼン株式会社、商品名)、トップ
ニコロン(奥野製薬株式会社、商品名)、ニムデン(上
村工業株式会社、商品名)等が使用できる。また、パラ
ジウム又は金のめっき層の厚さは0.5〜5μmとする
ことがめっきの厚さの均一性と仕上がり状態での配線板
の厚さとから好ましく、その他の金属の場合は同様の理
由から0゜5〜10μmとすることが好ましい。
In step e, the electroless plating solution for forming the first metal layer includes nickel, nickel/tungsten alloy, nickel/cobalt alloy, cobalt, cobalt/
There is no particular limitation as long as it can plate tungsten alloy, palladium, or gold. For example, in the case of nickel, a plating solution containing phosphorus or boron using ordinary hypophosphite as a reducing agent is commercially available. As products, Blue Shuma (Nippon Kanizen Co., Ltd., trade name), Top Nicolon (Okuno Pharmaceutical Co., Ltd., trade name), Nimden (Kamimura Industries Co., Ltd., trade name), etc. can be used. In addition, it is preferable that the thickness of the palladium or gold plating layer is 0.5 to 5 μm from the viewpoint of uniformity of the plating thickness and thickness of the finished wiring board, and for other metals, the same reason applies. It is preferable to set it as 0 degrees 5-10 micrometers.

工程fにおいて、第1の金属層の上に行う銅めっきに用
いる無電解銅めっき液についても、特に限定するもので
はなく、CC−41めっき液(日立化成工業株式会社、
商品名)等、通常の無電解めっき液が使用できる。
In step f, the electroless copper plating solution used for copper plating on the first metal layer is not particularly limited, and CC-41 plating solution (Hitachi Chemical Co., Ltd.,
Ordinary electroless plating solutions such as (trade name) can be used.

(作用) 銅のデンドライトは、電位差のある導体間において電位
の高い方の銅導体の溶解及び電位に低い方へのイオン移
動と電位の低い方の導体における析出現象であり、銅と
絶縁基板の界面に、電界による成分の移行の少ない物質
である第1の金属層を介在させることによって絶縁基板
の表面における配線導体間の電圧印加時での電食による
絶縁劣化を防ぐことができる。
(Function) Copper dendrites are a phenomenon in which between conductors with a potential difference, the copper conductor with a higher potential dissolves, ions move to the lower potential, and precipitation occurs in the conductor with a lower potential. By interposing the first metal layer, which is a substance whose components are less likely to migrate due to an electric field, at the interface, it is possible to prevent insulation deterioration due to electrolytic corrosion when a voltage is applied between wiring conductors on the surface of the insulating substrate.

実施例1 無電解めっき用触媒として塩化パラジウムを含有するガ
ラスクロス基材エポキシ樹脂積層板LE−144(日立
化成工業株式会社、商品名)に、同じ塩化パラジウムを
含有する接着剤でアクリロニトリルブタジェンゴムを主
成分としアルキルフェノール樹脂、エポキシ樹脂、無機
充填剤としてのシリカ、珪酸ジルコニウムを溶媒中で配
合した接着剤を塗布、乾燥し、加熱硬化して接着剤層を
形成した。
Example 1 A glass cloth base epoxy resin laminate LE-144 (trade name, Hitachi Chemical Co., Ltd.) containing palladium chloride as a catalyst for electroless plating was coated with acrylonitrile butadiene rubber using an adhesive containing the same palladium chloride. An adhesive containing alkylphenol resin, epoxy resin, silica as an inorganic filler, and zirconium silicate as main components in a solvent was applied, dried, and cured by heating to form an adhesive layer.

次いで、パンチプレスにより所定の位置に穴をあけた後
、無電解めっき用フォトレジストフィルムであるフォテ
ックSR−’3000(日立化成工業株式会社、商品名
)を真空ラミネータによってラミネートし、回路となら
ない箇所に露光し露光されなかった部分を現像して除去
しレジストを形成した。このとき、回路幅と導体間の間
隔は、いずれも0.15mmとした。
Next, after punching holes at predetermined positions using a punch press, Photec SR-'3000 (trade name, Hitachi Chemical Co., Ltd.), a photoresist film for electroless plating, is laminated using a vacuum laminator to form holes in areas that will not form a circuit. The unexposed portions were developed and removed to form a resist. At this time, the circuit width and the spacing between the conductors were both 0.15 mm.

レジストを形成した絶縁板を、Cr0g55gと濃硫酸
210mj!とを水で希釈し11としたクロム酸混液の
温度55℃の溶液の中に10分間浸漬し、回路部となる
部分を選択的に化学粗化して、水洗、中和した。
The insulating plate on which the resist was formed was heated with 55 g of Cr and 210 mj of concentrated sulfuric acid! The sample was immersed for 10 minutes in a solution of chromic acid mixture diluted with water to make 11 at a temperature of 55° C., and the portion that would become the circuit portion was selectively roughened chemically, washed with water, and neutralized.

この絶縁板を、下記の無電解ニッケル/タングステン合
金めっき液に60分間浸漬し、約2μmの合金めっき層
を形成した。
This insulating plate was immersed in the following electroless nickel/tungsten alloy plating solution for 60 minutes to form an alloy plating layer of about 2 μm.

〔組成〕〔composition〕

硫酸ニッケル       :1g/lタングステン酸
ナトリウム :35g/lクエン酸ナトリウム    
 :20g/1次亜リン酸ナトリウム   :LOg/
l〔条件〕 pH:9.8 液温度          :93℃ 次いで、水洗した後に、無電解めっき液としてCC−4
1めっき液(日立化成工業株式会社、商品名)に70℃
で浸漬し、約20μmの銅めっきを析出させた後、スル
ーホール以外の基板表面にソルダレジストをスクリーン
印刷法によって印刷塗布し加熱硬化して試験用配線板と
した。
Nickel sulfate: 1g/l Sodium tungstate: 35g/l Sodium citrate
:20g/1 Sodium hypophosphite :LOg/
l [Conditions] pH: 9.8 Solution temperature: 93°C Next, after washing with water, CC-4 was used as an electroless plating solution.
1 Plating solution (Hitachi Chemical Co., Ltd., trade name) at 70℃
After depositing a copper plating of about 20 μm, a solder resist was applied by screen printing to the surface of the substrate other than the through holes and cured by heating to obtain a test wiring board.

実施例2 塩化パラジウムを含有するガラス布エポキシ樹脂積層板
LE−168(日立化成工業株式会社、商品名)に実施
例1で使用した接着剤を塗布し、加熱硬化して絶縁基板
とした。
Example 2 The adhesive used in Example 1 was applied to a glass cloth epoxy resin laminate LE-168 (trade name, Hitachi Chemical Co., Ltd.) containing palladium chloride, and cured by heating to obtain an insulating substrate.

この後、高速ドリルマシンにより所定の位置に穴あけし
たものに、無電解めっき用フォトレジストフィルレムで
あるフォテック5R−3000(日立化成工業株式会社
、商品名)を真空ラミネータでラミネートし、露光・現
像して回路とならない部分にレジストを形成した。
After that, a hole was drilled at a predetermined position using a high-speed drill machine, and Photec 5R-3000 (trade name, Hitachi Chemical Co., Ltd.), which is a photoresist film for electroless plating, was laminated with a vacuum laminator, and exposed and developed. Then, a resist was formed on the parts that would not form a circuit.

レジストを形成した絶縁板を、Cr0g55gと濃硫酸
210mlとを水で希釈し11としたクロム酸混液の温
度55℃の溶液の中に10分間浸漬し、回路、部となる
部分を選択的に化学粗化して、水洗、中和した。
The insulating plate on which the resist was formed was immersed for 10 minutes in a solution of chromic acid mixture (11) made by diluting 55 g of Cr and 210 ml of concentrated sulfuric acid with water at a temperature of 55°C to selectively chemically remove the parts that would become the circuits. It was roughened, washed with water, and neutralized.

この絶縁基板を下記の無電解コバルト/ニッケル合金め
っき液に50分間浸漬して、約10μmの合金めっき層
を形成した。
This insulating substrate was immersed in the following electroless cobalt/nickel alloy plating solution for 50 minutes to form an alloy plating layer of about 10 μm.

(組成〕 塩化コバルト      :30g/It塩化ニッケル
      :30g/lグリコール酸ソーダ   :
l00g/A1次亜リン酸ソーダ     :22g/
i!〔条件〕 p)l           :4.5〜5.0液温度
         :92℃ 次いで、水洗した後に、無電解めっき液としてCC−4
1めっき液(日立化成工業株式会社、商品名)に70℃
で浸漬し、約20μmの銅めっきを析出させた後、スル
ーホール以外の基板表面にソルダレジストをスクリーン
印刷法によって印刷塗布し加熱硬化して試験用配線板と
した。
(Composition) Cobalt chloride: 30g/It Nickel chloride: 30g/L Sodium glycolate:
100g/A1 Sodium hypophosphite: 22g/
i! [Conditions] p)l: 4.5-5.0 Solution temperature: 92°C Next, after washing with water, CC-4 was used as an electroless plating solution.
1 Plating solution (Hitachi Chemical Co., Ltd., trade name) at 70℃
After depositing a copper plating of about 20 μm, a solder resist was applied by screen printing to the surface of the substrate other than the through holes and cured by heating to obtain a test wiring board.

実施例3 塩化パラジウムを含有するガラス布エポキシ樹脂積層板
LE−168(日立化成工業株式会社、商品名)に実施
例1で使用した接着剤を塗布し、加熱硬化して絶縁基板
とした。
Example 3 The adhesive used in Example 1 was applied to a glass cloth epoxy resin laminate LE-168 (trade name, Hitachi Chemical Co., Ltd.) containing palladium chloride, and cured by heating to obtain an insulating substrate.

この後、高速ドリルマシンにより所定の位置に穴あけし
たものに、無電解めっき用フォトレジストフィルレムで
あるフォテック5R−3000(日立化成工業株式会社
、商品名)を真空ラミネータでラミネートし、露光・現
像して回路とならない部分にレジストを形成した。
After that, a hole was drilled at a predetermined position using a high-speed drill machine, and Photec 5R-3000 (trade name, Hitachi Chemical Co., Ltd.), which is a photoresist film for electroless plating, was laminated with a vacuum laminator, and exposed and developed. Then, a resist was formed on the parts that would not form a circuit.

レジストを形成した絶縁板を、CrOz55gと濃硫酸
210mJとを水で希釈し11としたクロム酸混液の温
度55℃の溶液の中に10分間浸漬し、回路部となる部
分を選択的に化学粗化して、水洗、中和した。
The insulating plate on which the resist was formed was immersed for 10 minutes in a solution of chromic acid mixture (11) made by diluting 55 g of CrOz and 210 mJ of concentrated sulfuric acid with water at a temperature of 55°C to selectively chemically roughen the parts that would become the circuit parts. It was washed with water and neutralized.

この絶縁基板を下記の無電解コバルトめっき液に60分
間浸漬して、約5μmのめっき層を形成した。
This insulating substrate was immersed in the following electroless cobalt plating solution for 60 minutes to form a plating layer of about 5 μm.

〔組成〕〔composition〕

塩化コバルト      :35g/j!クエン酸ソー
ダ     :116g/j!次亜リン酸ソーダ   
 :11.5g/A〔条件〕 pH:s、oん10.0 液温度         :90を 次いで、水洗した後に、無電解めっき液としてCC−4
1めっき液(日立化成工業株式会社、商品名)に70℃
で浸漬し、約20Iimの銅めっきを析出させた後、ス
ルーホール以外の基板表面にソルダレジストをスクリー
ン印刷法によって印刷塗布し加熱硬化して試験用配線板
とした。
Cobalt chloride: 35g/j! Sodium citric acid: 116g/j! Sodium hypophosphite
: 11.5 g/A [Conditions] pH: s, on 10.0 Solution temperature: After washing with water, CC-4 was used as an electroless plating solution.
1 Plating solution (Hitachi Chemical Co., Ltd., trade name) at 70℃
After depositing about 20 Iim of copper plating, a solder resist was applied by screen printing to the surface of the substrate other than the through holes and cured by heating to prepare a test wiring board.

実施例4 塩化パラジウムを含有するガラス布エポキシ樹脂積層板
LE−168(日立化成工業株式会社、商品名)に実施
例1で使用した接着剤を塗布し、加熱硬化して絶縁基板
とした。
Example 4 The adhesive used in Example 1 was applied to a glass cloth epoxy resin laminate LE-168 (trade name, Hitachi Chemical Co., Ltd.) containing palladium chloride and cured by heating to obtain an insulating substrate.

この後、高速ドリルマシンにより所定の位置に穴あけし
たものに、無電解めっき用フォトレジストフィルレムで
あるフォテック5R−3000(日立化成工業株式会社
、商品名)を真空ラミネータでラミネートし、露光・現
像して回路とならない部分にレジストを形成した。
After that, a hole was drilled at a predetermined position using a high-speed drill machine, and Photec 5R-3000 (trade name, Hitachi Chemical Co., Ltd.), which is a photoresist film for electroless plating, was laminated with a vacuum laminator, and exposed and developed. Then, a resist was formed on the parts that would not form a circuit.

レジストを形成した絶縁板を、CrOz55gと濃硫酸
210m1tとを水で希釈し11としたクロム酸混液の
温度55℃の溶液の中に10分間浸漬し、回路部となる
部分を選択的に化学粗化して、水洗、中和した。
The insulating plate on which the resist was formed was immersed for 10 minutes in a solution of chromic acid mixture (11) made by diluting 55 g of CrOz and 210 ml of concentrated sulfuric acid with water at a temperature of 55°C to selectively chemically roughen the parts that would become the circuit parts. It was washed with water and neutralized.

この絶縁基板を下記の無電解パラジウムめっき液に60
分間浸漬して、約1μmのめっき層を形成したゆ (組成〕 テトラミンパラジウムクロライド :7.5g/A EDTA−2Na     : 8.Og/Rアンモニ
ア水      :280g/6ヒドラジン(1モル/
1):8mj!//!〔条件〕 液温度         :38℃ 次いで、水洗した後に、無電解めっき液としてCC−4
1めっき液(日立化成工業株式会社、商品名)に70℃
で浸漬し、約20μmの銅めっきを析出させた後、スル
ーホール以外の基板表面にソルダレジストをスクリーン
印刷法によって印刷塗布し加熱硬化して試験用配線板と
した。
This insulating substrate was immersed in the following electroless palladium plating solution for 60 minutes.
A plating layer of about 1 μm was formed by immersion for a minute (composition) Tetramine palladium chloride: 7.5 g/A EDTA-2Na: 8. Og/R Ammonia water: 280 g/6 hydrazine (1 mol/
1):8mj! //! [Conditions] Solution temperature: 38°C Next, after washing with water, CC-4 was used as an electroless plating solution.
1 Plating solution (Hitachi Chemical Co., Ltd., trade name) at 70℃
After depositing a copper plating of approximately 20 μm, a solder resist was applied by screen printing to the surface of the substrate other than the through holes and cured by heating to obtain a test wiring board.

実施例5 塩化パラジウムを含有するガラス布エポキシ樹脂積層板
LE−168(日立化成工業株式会社、商品名)に実施
例1で使用した接着剤を塗布し、加熱硬化して絶縁基板
とした。
Example 5 The adhesive used in Example 1 was applied to a glass cloth epoxy resin laminate LE-168 (trade name, Hitachi Chemical Co., Ltd.) containing palladium chloride, and the adhesive was cured by heating to obtain an insulating substrate.

この後、高速ドリルマシンにより所定の位置に穴あけし
たものに、無電解めっき用フォトレジストフィルレムで
あるフォテフク5R−3000(日立化成工業株式会社
、商品名)を真空ラミネータでラミネートし、露光・現
像して回路とならない部分にレジストを形成した。
After this, a hole was drilled at a predetermined position using a high-speed drill machine, and Fotefuku 5R-3000 (trade name, Hitachi Chemical Co., Ltd.), which is a photoresist film for electroless plating, was laminated with a vacuum laminator, and exposed and developed. Then, a resist was formed on the parts that would not form a circuit.

レジストを形成した絶縁板を、croz55gと濃硫酸
210mj+とを水で希釈し11としたクロム酸混液の
温度55℃の溶液の中に10分間浸漬し、回路部となる
部分を選択的に化学粗化して、水洗、中和した。
The insulating plate on which the resist has been formed is immersed for 10 minutes in a solution of chromic acid mixture (11) made by diluting 55 g of croz and 210 mj+ of concentrated sulfuric acid with water at a temperature of 55°C to selectively chemically roughen the parts that will become the circuit parts. It was washed with water and neutralized.

この絶縁基板を下記の無電解金めっき液に30分間浸漬
して、約0.5μmのめっき層を形成した。
This insulating substrate was immersed in the following electroless gold plating solution for 30 minutes to form a plating layer of about 0.5 μm.

〔組成〕〔composition〕

シアン化金カリウム   :2g/j!塩化アンモニウ
ム    :15g/lクエン酸ナトリウム   :5
0g/β次亜リン酸ソーダ    :10g/j!〔条
件〕 p)(ニア、O〜7.5 液温度         :92℃ 次いで、水洗した後に、無電解めっき液としてCC−4
1めっき液(日立化成工業株式会社、商品名)に70℃
で浸漬し、約20μmの銅めっきを析出させた後、スル
ーホール以外の基板表面にソルダレジストをスクリーン
印刷法によって印刷塗布し加熱硬化して試験用配線板と
した。
Potassium gold cyanide: 2g/j! Ammonium chloride: 15g/l Sodium citrate: 5
0g/β sodium hypophosphite: 10g/j! [Conditions] p) (Near, O~7.5 Solution temperature: 92°C Next, after washing with water, CC-4 was used as an electroless plating solution.
1 Plating solution (Hitachi Chemical Co., Ltd., trade name) at 70℃
After depositing a copper plating of about 20 μm, a solder resist was applied by screen printing to the surface of the substrate other than the through holes and cured by heating to obtain a test wiring board.

比較例1 以下のように、実施例1において、無電解銅めっきのみ
を行った。
Comparative Example 1 As described below, in Example 1, only electroless copper plating was performed.

無電解めっき用触媒として塩化パラジウムを含有するガ
ラスクロス基材エポキシ樹脂積層板LE−144(日立
化成工業株式会社、商品名)に、同じ塩化パラジウムを
含有する接着剤でアクリロニトリルブタジェンゴムを主
成分としアルキルフェノール樹脂、エポキシ樹脂、無機
充填剤としてのシリカ、珪酸ジルコニウムを溶媒中で配
合した接着剤を塗布、乾燥し、加熱硬化して接着剤層を
形成した。
Glass cloth base epoxy resin laminate LE-144 (Hitachi Chemical Co., Ltd., trade name) containing palladium chloride as a catalyst for electroless plating is coated with acrylonitrile butadiene rubber as a main component using an adhesive containing the same palladium chloride. An adhesive prepared by blending alkylphenol resin, epoxy resin, silica as an inorganic filler, and zirconium silicate in a solvent was applied, dried, and cured by heating to form an adhesive layer.

次いで、パンチプレスにより所定の位置に穴をあけた後
、無電解めっき用フォトレジストフィルムであるフォテ
ック5R−3000(日立化成工業株式会社、商品名)
を真空ラミネータによってラミネートし、回路とならな
い箇所に露光し露光されなかった部分を現像して除去し
レジストを形° 成した。このとき、回路幅と導体間の
間隔は、いずれも0.15mmとした。
Next, after punching holes at predetermined positions using a punch press, Photec 5R-3000 (trade name, Hitachi Chemical Co., Ltd.), a photoresist film for electroless plating, was used.
were laminated using a vacuum laminator, exposed to light in areas that would not form a circuit, and the unexposed areas were developed and removed to form a resist. At this time, the circuit width and the spacing between the conductors were both 0.15 mm.

レジストを形成した絶縁板を、CrOz55gと4硫酸
210nl!とを水で希釈しlβとしたクロム酸混液の
温度55℃の溶液の中に10分間浸漬し、回路部となる
部分を選択的に化学粗化して、水洗、中和した。
The insulating plate with the resist formed was treated with 55g of CrOz and 210nl of 4-sulfuric acid! It was immersed for 10 minutes in a solution of a chromic acid mixture diluted with water to give lβ at a temperature of 55° C., to selectively chemically roughen the portion that would become the circuit portion, and then washed with water and neutralized.

次いで、水洗した後に、無電解めっき液としてCC−4
1めっき液(日立化成工業株式会社、商品名)に70℃
で浸漬し、約20μmの銅めっきを析出させた後、スル
ーホール以外の基板表面にソルダレジストをスクリーン
印刷法によって印刷塗布し加熱硬化して試験用配線板と
した。
Next, after washing with water, CC-4 was applied as an electroless plating solution.
1 Plating solution (Hitachi Chemical Co., Ltd., trade name) at 70℃
After depositing a copper plating of about 20 μm, a solder resist was applied by screen printing to the surface of the substrate other than the through holes and cured by heating to obtain a test wiring board.

比較例2 以下のように、実施例2において、無電解銅めっきのみ
を行った。
Comparative Example 2 As described below, in Example 2, only electroless copper plating was performed.

塩化パラジウムを含有するガラス布エポキシ樹脂積層板
LE−168(日立化成工業株式会社、商品名)に実施
例1で使用した接着剤を塗布し、加熱硬化して絶縁基板
とした。
The adhesive used in Example 1 was applied to a glass cloth epoxy resin laminate LE-168 (trade name, Hitachi Chemical Co., Ltd.) containing palladium chloride and cured by heating to obtain an insulating substrate.

この後、高速ドリルマシンにより所定の位置に穴あけし
たものに、無電解めっき用フォトレジストフィルレムで
あるフォテック5R−3000(日立化成工業株式会社
、商品名)を真空ラミネータでラミネートし、露光・現
像して回路とならない部分にレジストを形成した。
After that, a hole was drilled at a predetermined position using a high-speed drill machine, and Photec 5R-3000 (trade name, Hitachi Chemical Co., Ltd.), which is a photoresist film for electroless plating, was laminated with a vacuum laminator, and exposed and developed. Then, a resist was formed on the parts that would not form a circuit.

レジストを形成した絶縁板を、CrOz55gと濃硫酸
210m1とを水で希釈し11としたクロム酸混液の温
度55℃の溶液の中に10分間浸漬し、回路部となる部
分を選択的に化学粗化して、水洗、中和した。
The insulating plate on which the resist was formed was immersed for 10 minutes in a solution of chromic acid mixture (11) made by diluting 55 g of CrOz and 210 ml of concentrated sulfuric acid with water at a temperature of 55°C to selectively chemically roughen the parts that would become the circuit parts. It was washed with water and neutralized.

次いで、水洗した後に、無電解めっき液としてCC−4
1めっき液(日立化成工業株式会社、商品名)に70℃
で浸漬し、約20μmの銅めっきを析出させた後、スル
ーホール以外の基板表面にソルダレジストをスクリーン
印刷法によって印刷塗布し加熱硬化して試験用配線板と
した。
Next, after washing with water, CC-4 was applied as an electroless plating solution.
1 Plating solution (Hitachi Chemical Co., Ltd., trade name) at 70℃
After depositing a copper plating of about 20 μm, a solder resist was applied by screen printing to the surface of the substrate other than the through holes and cured by heating to obtain a test wiring board.

また、実施例、比較例ともに、導体幅と間隔が共に0.
11■で、スルーホール径0.6tm、スルーホール数
約200穴とし、スルーホールを介して交互に絶縁基板
の両面にスルーホールを接続する導体パターンを有する
電食評価用パターンを用いた。
Further, in both the example and the comparative example, the conductor width and interval are both 0.
In No. 11, an electrolytic corrosion evaluation pattern was used, which had a through-hole diameter of 0.6 tm, approximately 200 through-holes, and a conductor pattern that alternately connected the through-holes to both sides of the insulating substrate via the through-holes.

電食評価の試験は、多数の試験片において、これを促進
して行うため、65℃/90%の加温加湿下で、導体間
に直流50Vを印加して連続的に通電し一定時間毎に取
り出して、導体間の絶縁抵抗値を測定し、また、スルー
ホールの断面を観察してデンドライト発生の有無調べた
。その結果を、以下の第1表に示す。
In order to accelerate the electrolytic corrosion evaluation test on a large number of test pieces, under heating and humidification at 65°C/90%, 50 V DC was applied between the conductors and the current was applied continuously at regular intervals for a certain period of time. The insulation resistance value between the conductors was measured, and the cross section of the through hole was observed to check for the occurrence of dendrites. The results are shown in Table 1 below.

また、同時に配線板に必要とされるはんだ耐熱性、引き
剥がし強度を、JIS−C−6481に準拠して測定し
た。その結果も、第1表に示す。
At the same time, the solder heat resistance and peel strength required for the wiring board were measured in accordance with JIS-C-6481. The results are also shown in Table 1.

これらの結果から分かるように、本実施例の効果として
、配線板に要求される他の特性を損なう  ゛ことなく
、絶縁基板表面における電食による絶縁劣化の抑制に優
れ、また、スルーホール間の電食にも改善が見られた。
As can be seen from these results, the effects of this example are that it is excellent in suppressing insulation deterioration due to electrolytic corrosion on the surface of an insulating substrate, without impairing other properties required for wiring boards, and that Improvement was also seen in electrolytic corrosion.

第1表 (発明の効果)Table 1 (Effect of the invention)

Claims (1)

【特許請求の範囲】[Claims] 1.以下に示す工程よりなる配線板の製造方法。 a.無電解めっき用触媒を含む絶縁基板表面に無電解め
っき用触媒を含む接着剤層を形成する。 b.スルーホールとなる穴をあける。 c.スルーホールと回路部となるべき部分以外の箇所に
無電解めっき用レジストを形成する。 d.化学粗化液に浸漬し、無電解めっき用レジストが形
成されていない箇所の表面を選択的に粗化する。 e.無電解めっき用レジストが形成されていない箇所に
第1の金属層として、無電解ニッケル合金、無電解コバ
ルト合金、無電解パラジウム又は無電解金のうちの1種
又は2種以上の組み合わせによる層を形成する。 f.無電解銅めっき液に浸漬し、第1の金属層の上に銅
めっき層を形成する。
1. A method for manufacturing a wiring board comprising the steps shown below. a. An adhesive layer containing a catalyst for electroless plating is formed on the surface of an insulating substrate containing a catalyst for electroless plating. b. Drill a hole that will become a through hole. c. A resist for electroless plating is formed in areas other than the through holes and the portions that will become circuit parts. d. It is immersed in a chemical roughening solution to selectively roughen the surface where the electroless plating resist is not formed. e. As the first metal layer, a layer made of one or a combination of two or more of electroless nickel alloy, electroless cobalt alloy, electroless palladium, or electroless gold is applied to the area where the electroless plating resist is not formed. Form. f. A copper plating layer is formed on the first metal layer by immersing it in an electroless copper plating solution.
JP63078383A 1988-03-28 1988-03-31 Manufacture of wiring board Pending JPH01251784A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP63078383A JPH01251784A (en) 1988-03-31 1988-03-31 Manufacture of wiring board
EP89302794A EP0335565B1 (en) 1988-03-28 1989-03-21 Process for producing printed wiring board
DE68916085T DE68916085T2 (en) 1988-03-28 1989-03-21 Process for the production of printed circuit boards.
KR1019890003938A KR920002276B1 (en) 1988-03-28 1989-03-28 Manufacture of printed wiring board
US07/970,925 US5309632A (en) 1988-03-28 1992-11-02 Process for producing printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63078383A JPH01251784A (en) 1988-03-31 1988-03-31 Manufacture of wiring board

Publications (1)

Publication Number Publication Date
JPH01251784A true JPH01251784A (en) 1989-10-06

Family

ID=13660491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63078383A Pending JPH01251784A (en) 1988-03-28 1988-03-31 Manufacture of wiring board

Country Status (1)

Country Link
JP (1) JPH01251784A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158587A (en) * 1983-02-26 1984-09-08 日立コンデンサ株式会社 Method of producing printed circuit board
JPS60124891A (en) * 1983-12-09 1985-07-03 セイコーエプソン株式会社 Method of producing printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158587A (en) * 1983-02-26 1984-09-08 日立コンデンサ株式会社 Method of producing printed circuit board
JPS60124891A (en) * 1983-12-09 1985-07-03 セイコーエプソン株式会社 Method of producing printed circuit board

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