JPH01251391A - Memory cell - Google Patents

Abstract

PURPOSE:To suppress the gate leak current of a data holding transistor of a memory cell even at the time of a high temperature by providing a resistance and a transistor for writing between the gate of the data holding transistor and the source of a load transistor. CONSTITUTION:The drain of a sixth enhancement type MESFET (E-FET) Q16 is connected to a second node, its gate is connected to a fourth node, and its source is connected to a second power source respectively, the drain of a seventh depression type MES (Metal Semiconductor) FET (D-FET) Q17 is connected to the second node, its gate is connected to a signal line for writing YW, and its source is connected to a third node respectively, and the drain of an eighth D-FETQ18 is connected to a first node, its gate is connected to the signal line for writing YW, and its source is connected to the fourth node respectively. At the time of the high temperature, while the forward breakdown voltage Vf of the parasitic diode of the E-FETQ16 is lowered, a gate leak current I11 is suppressed by a resistance R12. Thus, the gate leak current applied to the transistor for holding data can be suppressed even at the time of the high temperature.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory cell, particularly a static RAM (hereinafter referred to as SRAM) which is composed of a compound semiconductor FET.
Regarding memory cells.

[Conventional technology]

Conventionally, this type of memory cell is a depletion type M
E S (Met, al Sem1 conductor
)FET (hereinafter referred to as D-FET) and an enhancement type MESFET (hereinafter referred to as E-FET) constitute a flip-flop, and the D-FET is connected to the digit line of the flip-flop and the gate is connected to the word line. has been done. The following will be explained with reference to the drawings. FIG. 3 shows a circuit of a conventional SRAM memory cell. Qll~Q
14 is a D-FET and Q11. Q+4 is used as a selection transistor, Q121Q13 is used as a load transistor, and Q15+Qlb is an E-FET used as a data holding transistor. vo
D is +2.0 V, DL and DL are complementary digit lines, WL is a word line, and Rpυ is a pull-up resistor.

FIG. 4(a) shows that the memory cell in FIG. 3 is ■DD;+2,O
V, data retention characteristics of the memory cell when operating at room temperature (lower curve in the drawing), and D of the digit line DL.
FIG. 4(b) shows the memory cell of FIG. 3 at Vo.

=+2. OV, shows the data retention characteristics of the memory cell when operated at high temperatures, and the DC characteristics of the digit line DL.

Next, the difference in characteristics between FIGS. 4(a) and 4(b) will be explained. First, in FIG. 4(a) at room temperature, the data retention characteristics of the memory cell and the amplitude of the digit line DL are sufficient. On the other hand, when the temperature rises, the forward breakdown voltage f of the parasitic diode of the E-FET Q and 6 decreases, the gate leakage current I'll shown in FIG. 3 increases, and the node I'
When the "hyper level" of ltt is lowered, the data retention characteristics of the memory cell become worse as shown in FIG. 4(b), and the amplitude of the digit line DL becomes smaller.

[Problem to be solved by the invention]

A memory cell constructed of the above-described conventional compound semiconductor MES FET has the drawback that when the temperature rises, it becomes difficult to maintain the "high" level of the memory cell as described above, and the amplitude of the digit line becomes small.

An object of the present invention is to connect a resistor and a D-FET in parallel between the gate of the data retention transistor of a memory cell and the source of the load transistor, thereby reducing the gate leakage current that flows to the data retention transistor even at high temperatures. It is an object of the present invention to provide a memory cell which can suppress the occurrence of problems and has good characteristics.

[Means to solve the problem]

In the memory cell of the present invention, the gate of the first D-FET is connected to the word line, the drain is connected to the first digit line, and the source is connected to the first digit line.
, the gate and source of a second D-FET are connected to the first node, the drain is connected to the first power supply, and the gate and source of a third D-FET are connected to the second A fourth D-FET has its gate connected to the word line, its drain connected to the word line, and its source connected to the second digit line complementary to the first digit line. the drain of the fifth E-FET is connected to the first node, the gate is connected to the third node, the source is connected to the second power supply, and the drain of the sixth E-FET is connected to the second power source. The gate of the seventh D-FET is connected to the second node, the source is connected to the fourth node, and the source is connected to the second power supply, and the drain of the seventh D-FET is connected to the second node, the gate is connected to the write signal line, and the source is connected to the write signal line. the drain of an eighth D-FET is connected to the first node, the gate is connected to the write signal line, and the source is connected to the fourth node, respectively;
A resistor is connected between the second node and the third node, and a second resistor is connected between the first node and the fourth node.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a memory cell according to an embodiment of the present invention. Qst~Q141Qlf1Q18 is D-FET +
Q 15+ Q lb is E-FET, R, □, R1 □ are resistors, VDD is +2.0■ power supply, N 11+ N
1□+NlB+N14 is a node, WL is a word line, DL
, D are complementary digit lines, and YW is a write signal line. Compared to the conventional memory cell shown in FIG. 3, the present invention has Q1? It is constructed by adding a D-FET of +Q 1s and a resistor of R+□+R1□, and the same symbols as those in FIG. 3 indicate the same ones.

FIG. 2 (a> shows the data retention characteristics of the memory cell and the DC characteristics of the digit line DL at room temperature in FIG. 1,
FIG. 2(b) shows the data retention characteristics of the memory cell and the DC characteristics of the digit line DL at high temperatures in FIG.

Next, the difference in characteristics between FIGS. 2(a) and 2(b) will be explained. First, in the read state, the write signal line Y
When W is at “low” level, D-FETQI7. Since Q10 is off and the forward breakdown voltage V, of the parasitic diode of E F E T Q t 6 is high, gate leakage current III does not flow and the level of node Nil is maintained, as shown in FIG. As shown in a), the data retention characteristics of the memory cell and the amplitude of the digit line DL are sufficient.On the other hand, at high temperatures, the forward breakdown voltage V of the parasitic diode of E-FET QI6 decreases, but the gate Since the leakage current ■1□ is suppressed and the drop in the "high" level of the node Nll can be suppressed, the data retention characteristics of the memory cell and the amplitude of the digit line DL are different from those of the memory cell of the conventional circuit, as shown in FIG. 2(b). are multiplied by lj and 1.5 times, respectively.

Furthermore, in the write state, the write signal line YW goes to the "high" level, and D-F, ETQ1F.

Q18 turns on, and D-FETQ17. Assuming that the on-resistance (resistance between drain and source) of Qts is sufficiently smaller than R11+R12, data in the memory cell can be rewritten at high speed as in conventional memory cells.

FIG. 5 is a circuit diagram of a memory cell according to another embodiment of the present invention. In FIG. 5, a pebble-up circuit compared to the embodiment of FIG.
It is a Q20A E-FET, and the other circuits are the same as in FIG. In this embodiment, the pull-up circuit includes the data holding transistor Q15 of the memory cell.
．． E-FET same as Q16 Q 19A I Q 20
Since A is used, the flip flow 11 inversion voltage V↑
This has the advantage that variations due to fluctuations in are also compensated for, thereby improving the data retention characteristics of the memory cell. Note that the operation is the same as the embodiment shown in FIG.

〔Effect of the invention〕

As explained above, the present invention provides data retention in a memory cell at high temperatures in a read state by providing a resistor and a D-FET as a write transistor between the gate of a data retention transistor of a memory cell and the source of a load transistor. Even if the forward breakdown voltage V of the parasitic diode of the transistor resists, the gate leakage current of the data storage transistor can be suppressed and the memory cell can be kept at a "high" level. Similar to memory cells, data can be rewritten at high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIGS. 2(a) and 2(b) are characteristic diagrams of the memory cell in FIG. 1 at room temperature and high temperature, respectively, and FIG. 3 is a conventional circuit diagram. 4(a) and 4(b) are characteristic diagrams of the memory cell of FIG. 3 at room temperature and high temperature, respectively, and FIG. 5 is a circuit diagram of the memory cell of another embodiment of the present invention. Circuit diagram, Figure 6 (
6a) and 6(b) are characteristic diagrams of the memory cell of FIG. 5 at room temperature and at high temperature, respectively. Qll~Q14. QlF~Q20...Depression type MES FET (D-FET), Q10. Q
16°Q! 9A IQ 204-Enhancement type MES FET (,E-FET),
Voo...+2.0V power supply, DL. 7th line, digit line, RPL+... pull-up resistor, YW... write signal line, WL... word line.

Claims (1)

[Claims] The first depression type MES (MetalSemi
conductor) FET (hereinafter referred to as D-FET)
The gate of D-F is connected to the word line, the drain is connected to the first digit line, the source is connected to the first node, and the second D-F
The gate and source of the ET are connected to the first node, and the drain is connected to the first power source, and the gate and source of the third D-FET are connected to the second node, and the drain is connected to the first power source, respectively. a gate of a fourth D-FET is connected to the word line, a drain is connected to the first digit line, a complementary second digit line is connected, and a source is connected to the second node, and a fifth enhancement type MESF
The drain of an ET (hereinafter referred to as E-FET) is connected to the first node, the gate is connected to the third node, and the source is connected to the second power supply, and the drain of the sixth E-FET is connected to the second node. The gate is connected to the fourth node and the source is connected to the second node.
The drain of the seventh D-FET is connected to the second node, the gate is connected to the write signal line, the source is connected to the third node, and the drain of the seventh D-FET is connected to the third node.
The drain of T is connected to the first node, the gate is connected to the write signal line, and the source is connected to the fourth node, and a first resistor is connected between the second node and the third node. and a second resistor is connected between the first node and the fourth node.