JP2000057778A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which a current sense circuit can start a readout operation without being affected by the completion timing of the recovery operation, of a bit line, which follows a write operation. SOLUTION: A flip-flop circuit which is composed of transistors Q1, Q2, Q3, Q4 and a pair of transistors Q5, Q6 for cell selection constitute a memory cell 1. The transistors Q5, Q6 are connected to a bit line BL and a bit line *BL which are connected to a write circuit. The source of the transistor Q1 and the source of the transistor Q2 are connected to a pseudo grounding conductor Vgnd and a pseudo grounding conductor *Vgnd which are connected to a current sense circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory using a current sensing circuit, and more particularly to a semiconductor memory capable of high-speed reading.

[0002]

2. Description of the Related Art A current sensing circuit used in a semiconductor MOS memory is a signal detection circuit using a current as an input signal, and an output is a voltage signal. Since this current sensing circuit can suppress the voltage amplitude of the input signal to the limit (ideally, zero), the signal on the transmission line, which has a large parasitic capacitance and causes a delay time, can be used at high speed. It is effective when detecting. Such a current sense circuit is provided by the SRA
M is used to detect a read signal on a bit line when reading data from a memory cell (reference: N. Shibata, "Current sense amplifiers fo
r low-voltage memories, "IEICE Trans.Electron., vo
l.E79-C, no.8, pp.1120-1130, Aug. 1996.).

Hereinafter, the problem will be described with reference to FIG. 5 as a conventional technique. The memory cell 1 'is configured by combining a pair of load PchMOS transistors Q3, Q4 and a pair of drive NchMOS transistors Q1', Q2 'forming a flip-flop circuit with cell selection NchMOS transistors Q5, Q6. One of the pair of circuit nodes T1 and T2 of the flip-flop circuit is
The memory cell 1 'stores 1-bit data depending on the difference between the high level and the low level. WL is a word line for transmitting a selection signal of the memory cell 1 ', and is controlled to a high level when selected and to a low level when not selected. BL and * BL are paired bit lines (*
Represents inversion. The same applies to the following description. )
The input / output data is transmitted to the memory cell 1 'in the form of a differential signal. Although a large number of memory cells are connected to the bit line, only one is shown in FIG.

[0004] Q11 'and Q12' are Pch MOS transistors, R1 'and R2' are load resistors, and these four elements constitute a current sense circuit 2 '. T3, T
Reference numeral 4 denotes an input node of the current sense circuit 2 ', which is connected to a pair of bit lines BL and * BL in the conventional configuration.

Q9 and Q10 are Nch MOS transistors which constitute an output stage of a write circuit. When writing data to the memory cell 1 ', one of the bit lines BL or * BL is grounded (GND) according to the input data. ) Used to lower to near level. Q7 and Q8 are P-channel MOS transistors for pulling up a bit line, function as a constant current source when reading data from the memory cell 1 ', and write data to the memory cell 1' in a write cycle, Function as a recovery transistor for returning the power supply voltage to an initial level near the power supply voltage VDD. CB1 and CB2 are parasitic capacitances of the bit lines BL and * BL.

The contact T1 is at a high level and the contact T2 is
Assuming that data is stored in the memory cell 1 'so as to be at the LOW level, a read operation from the memory cell 1' will be described below. Since both control signals φ1 and φ2 are controlled to LOW level, transistors Q9 and Q10 are off, transistors Q7 and Q8 are on,
The transistors Q7 and Q8 function as constant current sources having the same current value.

Here, when the word line WL is controlled to a high level in order to read data from the memory cell 1 ', the transistor Q6 is turned on, and a current I _cell flows from the bit line * BL into the memory cell 1'. At this time, the node T
'Current into I _2, the current sense circuit 2 from the node T3' current sense circuit 2-4 and the current flowing into the I _1, the current flowing through the transistors Q7 and Q8 in this case is equal, during the current _Has a relationship of I ₁ = I ₂ + I _cell (1).

For simplicity, it is assumed that the transistors Q11 'and Q12' and the resistors R1 'and R2' have the same electrical characteristics without loss of generality. Resistance R1 ', R
Due to the difference in the amount of current flowing through 2 ', the output node Tout is at a higher level than the other output node * Tout. At these output nodes Tout and * Tout, the signal current I _cell flowing into the current sense circuit 2 'and the load resistance R1',
As R2 'is larger, a larger differential signal voltage can be obtained, but the output node may fall into a latch state (the output does not follow even if the differential input is reversed). There is a limit to the size of.

If the signal voltages available at these output nodes Tout, * Tout are not sufficient to directly drive the next logic gate, these signals are applied to a second, such as a current mirror type sense circuit. The amplitude is input to a sense circuit to further amplify the amplitude.

As shown by the equation (1), since the currents flowing through the transistors Q7 and Q8 are equal, the differential signal voltage of the paired bit lines BL and * BL is zero. This means that even if another memory cell is selected and the read data changes,
This means that charge and discharge do not occur in the large bit line parasitic capacitances CB1 and CB2, and data can be read very quickly by using the current sense circuit 2 '.

On the other hand, data writing to the memory cell 1 'is as follows. As an initial state, it is assumed that data is stored in the memory cell 1 'so that the contact T1 is at a high level and the contact T2 is at a low level, and a case where data opposite to this is written will be described. In the initial state, the control signals φ1 and φ2 are both at the LOW level,
The pair bit lines BL and * BL are set to a high level near the power supply voltage VDD.

Here, when the control signal φ1 is controlled to a high level after controlling the word line WL to a high level, the transistor Q7 is turned off, the transistor Q9 is turned on, and the level of the bit line BL is lowered. . Therefore, the gate and source of the transistor Q5 (bit line BL
A sufficiently large voltage is applied between the nodes (side nodes), and the transistor Q5 is turned on. As a result, the level of the contact T1 decreases and the transistor Q
When the voltage falls below the logical threshold voltage of the inverter composed of 2 'and Q4, the state of the flip-flop circuit is inverted and the contact T
1 becomes LOW level and the contact T2 becomes HIGH level, and the memory cell 1 'can hold updated data. After the data is written in the memory cell 1 'in this manner, the control signal φ1 is returned to the LOW level again to control the transistor Q7 to be conductive and the transistor Q9 to be non-conductive.

As a result, the level of the bit line BL is restored to the initial level by the electric charge supplied from the power supply VDD via the transistor Q7. There is no particular limitation on the timing of setting the word line WL to the inactive state (LOW level) after the data writing is completed.

[0014]

The conventional read circuit using the current sense circuit 2 'uses a bit line pull-up transistor Q7 or Q8 which functions as a constant current source at the time of reading, and uses the bit line pull-up transistors Q7 and Q8 to perform the write operation. The recovery operation of the bit line was performed. These transistors Q7, Q8
It is necessary to set the conduction resistance of the transistors Q7 and Q8 low in order to make the characteristics close to the ideal constant current source. On the other hand, to speed up the recovery operation, the conduction resistance of the transistors Q7 and Q8 must be set low. Normally, the transistors Q7 and Q7 are set so that the change in the current input to the current sense circuit 2 'increases in accordance with the contents stored in the memory cell 1'.
Since the conduction resistance of No. 8 is set higher, the recovery time becomes longer as a result.

One of the items representing the performance of a semiconductor memory is a minimum cycle time. In the conventional configuration using the current sense circuit 2 ', the write cycle time is longer than the read cycle time because the recovery operation following the write operation is slow as described above (the minimum write cycle time is equal to the data write time. Therefore, in order to shorten this even slightly, the potential difference between the paired bits must be reduced to some extent without waiting for the completion of the recovery operation of the bit line following the write operation, that is, to the extent that erroneous write does not occur. It is also possible to switch the selected memory cell and start a new read operation in the state where the size is reduced.

However, in this method, the start of the operation of the current sense circuit is delayed by the shortage of the recovery operation, and the access time increases, so that the minimum cycle time is not shortened. This is because no matter how fast the current sensing circuit is used, it cannot be detected unless a signal appears on the bit line.

As described above, the conventional read circuit using the current sense circuit can perform a read operation at a high speed, but requires a long recovery time after data is written. There was a problem that can not be shortened.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory capable of high-speed reading without being affected by the completion timing of a recovery operation.

[0019]

According to a first aspect of the present invention, there is provided a flip-flop circuit comprising a pair of load MOS transistors and a pair of drive MOS transistors, and a pair of flip-flop circuits connected to the flip-flop circuit. In a semiconductor memory having memory cells provided with the cell selecting MOS transistors of
A pair of bit lines are connected to a drain or a source of the S transistor opposite to a side connected to the flip-flop circuit, a pair of pseudo ground lines are connected to sources of the pair of driving MOS transistors, and A write circuit is connected to the bit line, and a current sense circuit is connected to the pair of pseudo ground lines.

In a second aspect based on the first aspect, the current sensing circuit comprises: a pair of input MOS transistors having a gate and a drain cross-connected; a load resistance of each of the input MOS transistors; And a pair of load transistors which are connected in series to the input MOS transistor and have a gate and a drain cross-connected and have the same conductivity type as the input MOS transistor.

According to a third aspect, in the first or second aspect, one end of the first resistor is connected to one of the pair of pseudo ground lines, and one end of the second resistor is connected to the other. The other end of the first resistor and the other end of the second resistor are grounded via a third resistor.

According to a fourth aspect, in the first to third aspects, the current sense circuit has a switch for cutting off a current.

[0023]

[First Embodiment] FIG. 1 is a circuit diagram showing a semiconductor memory according to a first embodiment of the present invention. The memory cell 1 is configured by combining a pair of load PchMOS transistors Q3 and Q4 and a pair of drive NchMOS transistors Q1 and Q2 forming a flip-flop circuit with cell selection NchMOS transistors Q5 and Q6. A pair of circuit nodes T1,
In T2, one of them becomes HIGH level and the other becomes LOW level, and the memory cell 1 stores 1-bit data depending on the state. WL is a word line for transmitting a selection signal of the memory cell 1, and is controlled to a high level when selected and to a low level when not selected. BL and * BL are paired bit lines that transmit input data to the memory cell 1 in the form of a differential signal.

5 differs from the conventional circuit shown in FIG. 5 in that the sources of a pair of driving NchMOS transistors Q1 and Q2 have a pair of pseudo ground lines Vgnd and * Vg running in parallel to bit lines BL and * BL.
Differently connected to nd. Note that bit line B
Many memory cells are connected to L and * BL and the pseudo ground lines Vgnd and * Vgnd, but only one is shown in FIG.

Q11 and Q12 are input NchMOS transistors, R1 and R2 are load resistors, and the current sensing circuit 2 is constituted by these four elements. T3, T4
Is an input node of the current sense circuit 2, and is different from the current sense circuit 2 'shown in FIG. 5 in that the input nodes T3 and T4 are separated from a pair of bit lines BL and * BL to form a pair of pseudo ground lines Vgnd and Vgnd. * Being connected to Vgnd, this pseudo ground line Vg
The difference is that nd and * Vgnd are connected to ground via a pair of constant current source resistors R3 and R4.

Q9 and Q10 are Nch MOS transistors, which constitute an output stage of the write circuit.
It is used to lower one bit line (BL or * BL) to near the ground level in accordance with input data when writing data to the memory cell 1. Q7 and Q8 are PchMOS transistors for pulling up bit lines, and are recovery transistors for returning bit lines BL and * BL to an initial level near power supply voltage VDD after writing data to memory cell 1 in a write cycle. Function. CB1 and CB2 are the parasitic capacitance of the bit line, CG1,
CG2 is a parasitic capacitance of the pseudo ground lines Vgnd and * Vgnd.

The contact T1 is at a high level and the contact T2 is at a high level.
Assuming that data is stored in the memory cell 1 so as to be at the LOW level, a read operation from the memory cell 1 will be described below. Since both control signals φ1 and φ2 are controlled to the LOW level, transistors Q9 and Q10 are off, and transistors Q7 and Q8 are on.

Here, when the word line WL is controlled to a high level in order to read data from the memory cell 1, the transistor Q6 becomes conductive, and a current I _cell flows into the memory cell 1 from the bit line * BL. Flows out to the pseudo ground line Vgnd. At this time, if the current flowing from the current sensing circuit 2 to the node T4 is I ₂ , and the current flowing from the current sensing circuit 2 to the node T3 is I _l , the resistors R3, R
Since the currents flowing through the currents 4 are equal, the relationship of I ₁ = I ₂ + I _cell (2) holds between the above-mentioned currents.

For the sake of simplicity, it is assumed that the resistors R3 and R4 have ideal characteristics as constant current sources having sufficiently large resistance values and equal sink currents without loss of generality.
1 and R2 and the transistors Q11 and Q12 have the same electrical characteristics. Due to the difference in the amount of current flowing through the resistors R1 and R2, the output node * Tout is relatively at a LOW level from the other output node Tout. Output node Tout, *
Tout has a signal current I flowing into the current sense circuit 2.
_A larger differential signal voltage can be obtained as the _cell and the load resistances R1 and R2 are larger, but the output node may fall into a latch state (the output does not follow even if the differential input is reversed). There is a limit to the magnitude of the output signal amount.

If the signal voltage obtained at the output contacts Tout, * Tout is insufficient to directly drive the next logic gate, these signals are supplied to a second sense circuit such as a current mirror type sense circuit. The signal is input to a circuit to further amplify the amplitude.

As shown by the equation (2), since the currents flowing through the resistors R3 and R4 are equal, the pair of pseudo ground lines BL and *
The differential signal voltage of BL is zero, and these pseudo ground lines are virtually short-circuited. Therefore, the introduction of the pseudo ground line does not lower the static noise margin of the memory cell 1.

On the other hand, data writing to the memory cell 1 is as follows. As an initial state, the memory cell 1
It is assumed that data is stored such that the contact T1 is at a high level and the contact T2 is at a low level, and a case where data opposite to this is written will be described.

In the initial state, the control signals φ1 and φ2 are both
It is at the LOW level, and the pair bit lines BL and * BL are set to a high level near the power supply voltage VDD. Here, after controlling the word line WL to a high level, the control signal φ1 is
When controlled to HIGH level, transistor Q7 is turned off, transistor Q9 is turned on, and bit line BL
Levels decrease. Therefore, a sufficiently large voltage is applied between the gate and the source (node on the bit line BL side) of the transistor Q5, and the transistor Q5
Becomes conductive. As a result, when the level of the contact T1 decreases and falls below the logical threshold voltage of the inverter constituted by the transistors Q2 and Q4, the state of the flip-flop circuit is inverted, and the contact T1 changes to the low level and the contact T2 changes to the high level. As a result, the memory cell 1 can hold the updated data.

After the data is thus written into the memory cell 1, the control signal φ1 is returned to the low level again to control the transistor Q7 to the conductive state and the transistor Q9 to the non-conductive state. Is restored to the initial level by the electric charge supplied from the power supply VDD via the transistor Q7. Regarding the timing of making the word line WL inactive (low level),
There is no particular limitation as long as the data writing is completed as in the prior art.

When the bit line BL is not completely restored to the initial level when the word line WL is controlled to the inactive state, the power supply V is supplied via the transistor Q7.
Charge is supplied from DD, and the recovery operation of the bit line BL continues. However, by controlling the word line WL to the inactive state, both the current path from the bit line BL to the pseudo ground line * Vgnd and the current path from the bit line * BL to the pseudo ground line Vgnd are completely cut off. Even if another memory cell is selected following the write operation and the operation of reading the opposite data starts, the charging current of the bit lines BL and * BL does not affect the subsequent read operation. That is, the current sense circuit can start the next read operation without being affected by the completion timing of the bit line recovery operation following the write operation.

[Second Embodiment] FIG. 2 shows a semiconductor memory according to a second embodiment of the present invention. The first embodiment is different from the first embodiment in that a pair of NchMOS transistors Q1 having a gate and a drain cross-connected to the current sense circuit 2 in FIG.
3 is different from the current sense circuit 2A in which Q14 is added as a part of the load.

These MOS transistors Q13, Q1
Reference numeral 4 indicates that the conduction resistance changes depending on the current flowing through the resistors R1 and R2. For example, when the current I _l increases and the current I ₂ decreases, the transistor Q13 increases the applied gate-source voltage, so that the conduction resistance decreases, and the transistor Q14 decreases the gate-source voltage. The conduction resistance increases. That is, the transistors Q13 and Q1
Reference numeral 4 functions as a variable impedance load using the resistors R1 and R2 in series. As a result, the transistor Q1
3, Q14 is the output node Tout, since suppressing the amplitude of * Tout, the current value of the current flowing through the sense circuit 2A (I ₁ and I ₂₎ is greater changes output node Tout, * Tout that fall into the latch state It operates with little speed.

[Third Embodiment] FIG. 3 shows a semiconductor memory according to a third embodiment of the present invention. The difference from the first embodiment is that a common resistor R5 is added to the ground side of the resistors R3 and R4.

Since the resistor R5 acts as a common impedance to the current flowing through the resistors R3 and R4, when the virtual short-circuit relationship between the pseudo ground lines Vgnd and * Vgnd is impaired due to the influence of noise, the resistance R5 is set to Suppressing the potential difference has the effect of preventing the storage contents of the memory cell 1 from being destroyed.

[Fourth Embodiment] FIG. 4 shows a semiconductor memory according to a fourth embodiment of the present invention. The first embodiment is different from the first embodiment in that a PchMOS transistor Q15 for cutting off a current path of the current sense circuit 2 in FIG.
The current sensing circuit 2B configured by adding Q16 is different.

When there is no need to operate the current sense circuit, such as during standby or data writing, the control signal φ
By controlling 3 to a high level, transistor Q15,
By turning off Q16, the power consumption of the current sensing circuit 2B can be reduced to zero.

The positional relationship between R1 and Q15 and between R2 and Q16 can be interchanged. Also, PchM
Instead of the OS transistor, an Nch MOS transistor can be used for current path cutoff. In this case, the NchMOS transistor is connected to T3 and Q11
, Each is connected between T4 and Q12, but has the same power consumption reduction effect.

[Other Embodiments] Other configurations in which the second to fourth embodiments are combined, and configurations in which the conductivity types (Pch and Nch) of the MOS transistors are replaced with the positive and negative polarities of the power supply voltage VDD are all adopted. It is feasible and has the same effect as the above embodiment.

[0044]

As described above, according to the first aspect, there is an advantage that the current sense circuit can start the read operation without being affected by the completion timing of the bit line recovery operation following the write operation. Therefore, when the demand for the minimum cycle time is strict, application of the semiconductor memory using the current sense circuit of the present invention is very effective.

According to the second aspect of the present invention, even if the difference between the differential currents flowing through the current sensing circuit changes greatly, the output contact operates at high speed without falling into the latch state.

According to the third aspect of the invention, even when the virtual short-circuit relationship between the pseudo ground lines is broken, the potential difference is suppressed, and the storage contents of the memory cells can be prevented from being destroyed.

Further, according to the fourth aspect of the invention, the current can be cut off when the current sensing circuit is not required to operate such as at the time of standby or at the time of data writing, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor memory according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor memory according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a semiconductor memory according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional semiconductor memory.

[Explanation of symbols]

Q1, Q2, Q5, Q6, Q9, Q10, Q11, Q1
2, Q13, Q14, Q15, Q16, Q1 ', Q
2 ': Nch MOS transistor Q3, Q4, Q7, Q
8, Q11 ′, Q12 ′: PcMOS transistors CB1, CB2, CG1, CG2: parasitic capacitance VDD: power supply voltage φ1, φ2, φ3: control signals T1, T2, T3, T4, Tout, * Tout: circuit nodes R1, R2 , R3, R4, R5, R1 ′, R2 ′: resistance I _cell , I ₁ , I ₂ : current WL: word line BL, * BL: bit line Vgnd, * Vgnd: pseudo ground line

Claims (4)

[Claims] 1. A semiconductor memory having a flip-flop circuit including a pair of load MOS transistors and a pair of driving MOS transistors, and a memory cell including a pair of cell selection MOS transistors connected to the flip-flop circuit. A pair of bit lines are connected to a drain or a source of the pair of cell selection MOS transistors on a side opposite to a side connected to the flip-flop circuit, and the pair of drive M
A semiconductor memory, wherein a pair of pseudo ground lines is connected to the source of the OS transistor, a write circuit is connected to the pair of bit lines, and a current sense circuit is connected to the pair of pseudo ground lines. 2. A current sensing circuit comprising: a pair of input MOS transistors having a gate and a drain cross-connected; a load resistance of each of the input MOS transistors; and a series connection of the load resistance and the input MOS transistor. The gate and the drain are cross-connected and the input MOS
2. The semiconductor memory according to claim 1, comprising a pair of load transistors having the same conductivity type as the transistor. 3. A pair of pseudo ground lines, one end of a first resistor is connected to one end, the other end of a second resistor is connected to the other, and the other end of the first resistor is connected to the second resistor. 3. The semiconductor memory according to claim 1, wherein the other end is grounded via a third resistor. 4. The current sensing circuit according to claim 1, further comprising switch means for cutting off a current.
4. The semiconductor memory according to any one of 1 to 3.