JPH01248651A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH01248651A JPH01248651A JP63077700A JP7770088A JPH01248651A JP H01248651 A JPH01248651 A JP H01248651A JP 63077700 A JP63077700 A JP 63077700A JP 7770088 A JP7770088 A JP 7770088A JP H01248651 A JPH01248651 A JP H01248651A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- plating
- lead frame
- area
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000007747 plating Methods 0.000 claims abstract description 45
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052802 copper Inorganic materials 0.000 claims abstract description 23
- 239000010949 copper Substances 0.000 claims abstract description 23
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000956 alloy Substances 0.000 abstract description 7
- 229910000978 Pb alloy Inorganic materials 0.000 abstract description 5
- 229910000510 noble metal Inorganic materials 0.000 abstract description 5
- 229910001128 Sn alloy Inorganic materials 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- XFXPMWWXUTWYJX-UHFFFAOYSA-N Cyanide Chemical compound N#[C-] XFXPMWWXUTWYJX-UHFFFAOYSA-N 0.000 abstract description 2
- 238000003672 processing method Methods 0.000 abstract description 2
- KIKDPIYHXZFGGH-UHFFFAOYSA-N B(F)(F)F.[Sn] Chemical compound B(F)(F)F.[Sn] KIKDPIYHXZFGGH-UHFFFAOYSA-N 0.000 abstract 1
- 229910052729 chemical element Inorganic materials 0.000 abstract 1
- 239000002075 main ingredient Substances 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000010970 precious metal Substances 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- DOBRDRYODQBAMW-UHFFFAOYSA-N copper(i) cyanide Chemical compound [Cu+].N#[C-] DOBRDRYODQBAMW-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- FAKFSJNVVCGEEI-UHFFFAOYSA-J tin(4+);disulfate Chemical compound [Sn+4].[O-]S([O-])(=O)=O.[O-]S([O-])(=O)=O FAKFSJNVVCGEEI-UHFFFAOYSA-J 0.000 description 1
- 239000011573 trace mineral Substances 0.000 description 1
- 235000013619 trace mineral Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating And Plating Baths Therefor (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はめっき膜構造を改良した半導体装置用リードフ
レームに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device with an improved plating film structure.
［従来の技術］
従来、半導体装置用リードフレームは第５図及び第６図
に示すように、ニッケルを４２重量％含有し、残部が鉄
である鉄・ニッケル合金（通常４２合金）又は銅を主成
分とし、鉄、ニッケル、リン、シリコン及び錫等の元素
を微量添加した銅合金からなるテープ状のリードフレー
ム本体１１の半導体素子搭載領域１２と外部リード部１
３側のワイヤボンディング領域１４に夫々銀又は金等の
めっき膜１５が形成されていた。[Prior Art] Conventionally, lead frames for semiconductor devices are made of an iron-nickel alloy (usually 42 alloy) containing 42% by weight of nickel and the balance being iron, or copper, as shown in FIGS. 5 and 6. Semiconductor element mounting area 12 and external lead portion 1 of a tape-shaped lead frame body 11 made of a copper alloy whose main component is a copper alloy to which small amounts of elements such as iron, nickel, phosphorus, silicon, and tin are added.
A plating film 15 of silver, gold, or the like was formed on each of the wire bonding regions 14 on the third side.
［発明が解決しようとする課題］
上述したように従来の半導体装置用リードフレームは、
めっき膜１５として金又は銀の貴金属を使用しているた
め、必然的に高価なものとなっていた。また、金又は銀
等の貴金属は国際相場の変動が激しく、場合によっては
リードフレームを安定して調達することができないこと
がある。更に、銅合金材で製作したリードフレームのワ
イヤボンディング領域１４に銅線を金又は銀等のめっき
を施さずに熱圧着ボンディングする方法も近時性われて
いるが、この方法では銅合金材に含まれている微量元素
による銅線との接合面への影響がらボンデ、イング異常
が生じやすく、半導体装置の信頼性を損う等の欠点があ
った。[Problems to be solved by the invention] As mentioned above, conventional lead frames for semiconductor devices have
Since the plating film 15 uses noble metals such as gold or silver, it is inevitably expensive. Furthermore, the international market prices of precious metals such as gold and silver are subject to rapid fluctuations, and in some cases it may not be possible to stably procure lead frames. Furthermore, a method has recently been developed in which a copper wire is thermocompression bonded to the wire bonding area 14 of a lead frame made of a copper alloy material without being plated with gold or silver. Bonding and bonding abnormalities tend to occur due to the influence of the trace elements contained on the bonding surface with the copper wire, resulting in drawbacks such as impairing the reliability of semiconductor devices.
本発明はかかる問題点に鑑みてなされたものであって、
めっき膜として高価な貴金属を使用することがなく安価
であると共に、ボンディングワイヤとして銅線を使用し
てもボンディング異常が生じることがな′＜、信頼性が
向上した半導体装置用リードフレームを提供、すること
を目的とする。The present invention has been made in view of such problems, and includes:
Provides a lead frame for semiconductor devices that is inexpensive as it does not use expensive precious metals as a plating film, does not cause bonding abnormalities even when copper wire is used as a bonding wire, and has improved reliability. The purpose is to
し課題を解決するための手段］
本発明に係る半導体装置用リードフレームは、銅合金を
素材とし、半導体素子搭載領域、ワイヤボンディング領
域及び外部リード部を備えた半導体装置用リードフレー
ムにおいて、前記半導体素子搭載領域及び前記ワイヤボ
ンディング領域に銅めっき膜を被着形成したことを特徴
とする。Means for Solving the Problem] A lead frame for a semiconductor device according to the present invention is made of a copper alloy and includes a semiconductor element mounting area, a wire bonding area, and an external lead part. The device is characterized in that a copper plating film is deposited on the element mounting area and the wire bonding area.
［作用］
上記構成により、本発明の半導体装置用リードフレーム
は、めっき膜として高価な貴金属が不要であると共に、
銅線を熱圧着ボンディングする場合において、この銅線
との接合部に銅めっき膜が形成されているため、銅合金
の素材に含まれる各種異元素の影響を受けることがなく
、従って、接合強度が向上する。[Function] With the above structure, the lead frame for a semiconductor device of the present invention does not require an expensive noble metal as a plating film, and
When bonding copper wire by thermocompression, a copper plating film is formed at the joint with the copper wire, so it is not affected by various different elements contained in the copper alloy material, and therefore the joint strength is improved. will improve.
［実施例］
以下、添付の図面を参照して本発明の実施例について具
体的に説明する。[Example] Hereinafter, an example of the present invention will be specifically described with reference to the accompanying drawings.
第１図は本発明の実施例に係る１６ピンの半導体装置用
リードフレームを示す平面図、第２図は第１図のＸ−Ｘ
線に沿う断面図である。図中、１はテープ状のリードフ
レーム本体である。この本体１としては、例えば、厚さ
が０．２５ｍｍの４２合金が用いられる。２は半導体素
子搭載領域、３はワイヤボンディング領域であり、これ
らの領域には夫々厚さが４．０乃至１５．０μｍの銅め
っき膜４が被着形成されている。また、５は外部リード
部であり、この外部リード部５を含む他の領域には厚さ
が８．０乃至９．５μｍの錫めっき膜６が被着形成され
ている。FIG. 1 is a plan view showing a 16-pin semiconductor device lead frame according to an embodiment of the present invention, and FIG.
It is a sectional view along a line. In the figure, 1 is a tape-shaped lead frame main body. As this main body 1, for example, 42 alloy with a thickness of 0.25 mm is used. 2 is a semiconductor element mounting area, and 3 is a wire bonding area, each of which is coated with a copper plating film 4 having a thickness of 4.0 to 15.0 μm. Reference numeral 5 designates an external lead portion, and a tin plating film 6 having a thickness of 8.0 to 9.5 μm is deposited on other areas including the external lead portion 5.
上記リードフレームは、従来から使用されている４２合
金のリードフレーム本体１をエツチング加工で所定の形
状に製作した後に、通常行われているめっき前処理とし
てアルカリ脱脂又は溶剤脱脂及び酸洗浄を行い、本体１
の素材表面の金属酸化物を除去した後、半導体素子搭載
領域２とワイヤボンディング領域３に、青化銅等の青化
物を主成分とした銅めっき液により部分電気めっきを施
して銅めつき膜４を形成し、続いて外部リード部５を含
めた他の領域に硫酸錫めっき液により部分電気めっきを
施して半田付性の良好な錫めっき膜６を形成したもので
ある。The above-mentioned lead frame is manufactured by etching the lead frame main body 1 of conventionally used 42 alloy into a predetermined shape, and then performing alkaline degreasing or solvent degreasing and acid cleaning as the usual plating pretreatment. Main body 1
After removing metal oxides on the surface of the material, partial electroplating is applied to the semiconductor element mounting area 2 and wire bonding area 3 using a copper plating solution mainly composed of a cyanide such as copper cyanide to form a copper plating film. 4 is formed, and then partial electroplating is performed on other areas including the external lead portion 5 using a tin sulfate plating solution to form a tin plating film 6 with good solderability.
第３図及び第４図は本発明の他の実施例を示すもので、
第３図は平面図、第４図は第３図のＹ−Ｙ線に沿う断面
図である。3 and 4 show other embodiments of the present invention,
FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line Y--Y in FIG. 3.
本実施例においては、厚さが０．２０ａｍの銅合金材を
使用してプレス加工法で製作した１６ビンリ一ドフレー
ム用本体１に対し、半導体素子搭載領域２とワイヤボン
ディング領域３に、青化物を主成分とした銅めっき液に
より部分電気めっきを施して厚さが６．０乃至７．５μ
ｍの銅めっき膜７を形成した後に、外部リード部５を含
めた他の領域にホウ弗化錫及び鉛合金めっき浴の部分電
気めっきを施して錫及び鉛合金めっき膜８を形成したも
のである。In this example, the main body 1 for a 16-bin lead frame manufactured by a press processing method using a copper alloy material with a thickness of 0.20 am has a blue color applied to the semiconductor element mounting area 2 and the wire bonding area 3. Partially electroplated using a copper plating solution mainly composed of oxides to a thickness of 6.0 to 7.5μ
After forming the copper plating film 7 of m, the other areas including the external lead part 5 are subjected to partial electroplating using a borofluoride tin and lead alloy plating bath to form the tin and lead alloy plating film 8. be.
以上の実施例においては、いずれもめっき膜として貴金
属を使用していないため、安価なリードフレームが得ら
れる。In the above embodiments, since no noble metal is used as the plating film, an inexpensive lead frame can be obtained.
また、銅線を用いて熱圧着ボンディングする場合には、
ワイヤボンディング領域２に銅めっき膜４．７が形成さ
れているため、銅線との接合面に銅合金に含有されてい
る各種異元素（熱圧着面に生成する種々の酸化物）の影
響がなくなり、且つ、高純度な銅めっき膜４．７と銅線
との接合であるため、接合強度が強くなり、その結果半
導体装置の信頼性が向上する。 １更に
、銅めっきを青化浴中で行っているため、他のめっき浴
よりも浴管理が容易であり、高速部分めっきに最適であ
る。また、銅めっき膜４，７の厚さを４．０μｍ以上と
したので、ピンホールのないめっき膜を形成することが
できると共に、各種異元素の銅線との接合面への影響を
確実に防止することができる。In addition, when performing thermocompression bonding using copper wire,
Since the copper plating film 4.7 is formed in the wire bonding area 2, the bonding surface with the copper wire is not affected by various different elements contained in the copper alloy (various oxides generated on the thermocompression bonding surface). Since the copper wire is bonded to the high-purity copper plating film 4.7, the bonding strength is increased, and as a result, the reliability of the semiconductor device is improved. 1 Furthermore, since copper plating is performed in a bluing bath, bath management is easier than other plating baths, making it ideal for high-speed partial plating. In addition, since the thickness of the copper plating films 4 and 7 is set to 4.0 μm or more, it is possible to form a plating film without pinholes, and to ensure that various different elements do not affect the bonding surface with the copper wire. It can be prevented.
一方、銅めっき膜４．７の厚さの最大を１５゜０μｍと
したのは、それ以上の厚さであるとめっき時間が長くな
り作業性が悪く不経済であると共に、電気めっき法特有
の先端効果によってリード周辺のめっき膜が厚くなり、
外観性を損うからである。On the other hand, the reason why the maximum thickness of the copper plating film 4.7 is set to 15°0 μm is because if the thickness is larger than that, the plating time will be longer, the workability will be poor and it will be uneconomical, and the reason is that The plating film around the lead becomes thicker due to the tip effect.
This is because it impairs the appearance.
［発明の効果コ
以上説明したように本発明の半導体装置用リードフレー
ムによれば、リードフレーム本体の素材として銅合金を
使用すると共に、半導体素子搭載領域とワイヤボンディ
ング領域に銅めっき膜を被着形成するので、貴金属によ
るめっきが不要となり、安価になると共に、銅線を熱圧
着ボンディングする場合においては、ワイヤボンディン
グ領域に銅めっき膜が形成されているため、銅線との接
合面に対する銅合金素材に含有されている各種異元素の
影響がなくなり、且つ、高純度な銅めっき膜と銅線との
接合であるため接合強度も強くなる。[Effects of the Invention] As explained above, according to the lead frame for a semiconductor device of the present invention, a copper alloy is used as the material of the lead frame body, and a copper plating film is applied to the semiconductor element mounting area and the wire bonding area. This eliminates the need for precious metal plating, making it cheaper, and when bonding copper wires by thermocompression, since a copper plating film is formed in the wire bonding area, the copper alloy on the bonding surface with the copper wire is The influence of various different elements contained in the material is eliminated, and since the bond is between a high-purity copper plating film and a copper wire, the bond strength is also strong.
従って、本発明によれば、半導体装置の信頼性が著しく
向上する。Therefore, according to the present invention, the reliability of the semiconductor device is significantly improved.
第１図は本発明の実施例に係るリードフレームの平面図
、第２図は第１図のＸ−Ｘ線に沿う断面図、第３図は本
発明の他の実施例に係るリードフレームの平面図、第４
図は第３図のＹ−Ｙ線に沿う断面図、第５図は従来のリ
ードフレームの平面図、第６図は第５図のＺ−Ｚ線に沿
う断面図である。
１．１１；リードフレーム本体、２，１２；半導体素子
搭載領域、３，１４：ワイヤボンディング領域、４，７
；銅めっき膜、５．１：３．外部リード部、６；錫めっ
き膜、８；錫及び鉛合金めつき膜、１５；めっき膜（金
又は銀）FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line X-X in FIG. 1, and FIG. 3 is a plan view of a lead frame according to another embodiment of the present invention. Floor plan, 4th
These figures are a cross-sectional view taken along the Y-Y line in FIG. 3, FIG. 5 is a plan view of a conventional lead frame, and FIG. 6 is a cross-sectional view taken along the Z-Z line in FIG. 1.11; Lead frame body, 2, 12; Semiconductor element mounting area, 3, 14: Wire bonding area, 4, 7
; Copper plating film, 5.1:3. External lead part, 6; tin plating film, 8; tin and lead alloy plating film, 15; plating film (gold or silver)
Claims (1)
ボンディング領域及び外部リード部を備えた半導体装置
用リードフレームにおいて、前記半導体素子搭載領域及
び前記ワイヤボンディング領域に銅めっき膜を被着形成
したことを特徴とする半導体装置用リードフレーム。(1) In a lead frame for a semiconductor device made of a copper alloy and comprising a semiconductor element mounting area, a wire bonding area, and an external lead part, a copper plating film is deposited on the semiconductor element mounting area and the wire bonding area. A lead frame for semiconductor devices characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63077700A JPH01248651A (en) | 1988-03-30 | 1988-03-30 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63077700A JPH01248651A (en) | 1988-03-30 | 1988-03-30 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01248651A true JPH01248651A (en) | 1989-10-04 |
Family
ID=13641171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63077700A Pending JPH01248651A (en) | 1988-03-30 | 1988-03-30 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01248651A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017028152A (en) * | 2015-07-24 | 2017-02-02 | 株式会社三井ハイテック | Lead frame and manufacturing method therefor |
-
1988
- 1988-03-30 JP JP63077700A patent/JPH01248651A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017028152A (en) * | 2015-07-24 | 2017-02-02 | 株式会社三井ハイテック | Lead frame and manufacturing method therefor |
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