JPH012445A - Branch transmission method for multiplexed signals - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a main station including a digital time division multiplexing device connected to a high-speed digital line, and a branch connection device provided in the middle of the high-speed digital line. The present invention relates to a branch-relay transmission system in which digital time-division signals are transmitted and received between slave stations including digital time-division multiplexing equipment connected to a line via a line.

(Prior Art) A branch service is a high-speed digital line service provided by NTT (Nippon Telegraph and Telephone Corporation) and others.

, This branch service installs a branch connection device in the middle of the high-speed digital line, and connects the high-speed digital signal transmitting/receiving station M1.
The transmission signal from the station to the M3 station is branched to the M2 station located midway between the M1 and M3 stations. Alternatively, a new signal from the M2 station to the M1 station and the M3 station is inserted. This service, that is, the function of the branch connection device, includes one that performs only one-way branching and one that can perform bidirectional branching.

Figure 7 shows an example of this type of branching service, in which there are four high-speed digital signal transmitting/receiving stations M1 to M4, each equipped with a digital multiplexer 1 to 4, with the station having the function of managing the whole being the main station. Let's say Ml, and others (M2 to M4)
In the system in which M1 and H4 are slave stations, bidirectional branch connection devices 5 and 6 are installed in the middle of the transmission path 10 between M1 and H4. The bidirectional branch connection devices 5 and 6 will be explained.

FIG. 8 is a functional block diagram of the bidirectional branch connection devices 5 and 6 shown in FIG.

5 will be explained.

In the figure, 51.52 is the input and output terminal of A route, 53.5
4 indicates the input and output terminals of the B route, and 55 and 56 indicate the input and output terminals of the C route, respectively.

In this case, the A, B, and C answer routes are directions to the M1 station, respectively, for the bidirectional branch connection device 5 in FIG.

Represents H4 station direction and M2 station direction.

57 to 59 are AND gates. The operation of this bidirectional branch connection device 5 will be explained. The signal transmitted from the H1 station enters the A route input terminal IN-A31, is branched on the way, and is input to AND gates 57 and 59.

The signal from the direction of the H4 station is received at the B route input terminal IN-B53 and applied to the AND gate 59, so that it is “
1", the C route output terminal 0tJT-C56 outputs the A route input terminal lN-A31 human power as is, but "0
”, it becomes “0”.

The output of the B-route output terminal 0UT-854 is similarly controlled by the input signal of the C-route input terminal 1N-C55. Therefore, when such a bidirectional branch connection device is installed in the middle of a line, the channel allocation and transmission/reception status of transmission signals are said to be as follows.

Figure 9 (a) and (bl are the main station (Ml), slave station (H2)
This shows the channel allocation and transmission/reception status of signals between ゜H3 and H4). The number of signal paths required for each route is 4C2-6
Specifically, M1+M2°MISM3. Ml →
M4. H24-4M3. M2→M4. H31-H4. The arrow ← represents signal transmission in both upward and downward directions.

Therefore, the transmission signal sent and received between the master station and the slave station is a time division multiplexed signal of at least 6 channels, for example, channel 1 (
CHI) is connected to channel 2 (CH2) in the direction of M1+4M2.
) is in the direction of M1←M3, and channel 3 (CH3) is in the direction of M1←M3.
In the direction of l-4M4, channel 4 (CH4) is M2→
In the direction of M3, channel 5 (CH3) is M2? -M
Channel 6 (CH6) is assigned to route M3→M4. In this example, 1 each for each direction.
Only cH is used, but if the amount of data is large, 2C each
Of course, it can also be set to H.

Here, as shown in FIG. 9(a), data A-L is input to the assigned channel, all "1" is input to the hatched CI, and each station? If the marked CHs are ignored, reception is performed as shown in FIGS. 9(a) and 9(b).

A digital multiplexer capable of performing branch-relay transmission as shown in FIGS.
This can be achieved by controlling the transmission so that the signal is received, and controlling the reception so that the received signal is received or ignored.
A device as shown in Fig. 0 can be considered.

In FIG. 10, 100 is a multiplexing control circuit that controls the transmission frame configuration. 104 is an address control memory (
105 is a transmission line interface circuit, 106 is an address bus, 107 is a transmission bus for carrying transmission data, 10B is a reception bus for carrying reception data, 109 is a transmission control signal, and 110 is a reception control. Show signal. The transmission control signal 109 controls the transmission signal of the corresponding CH from the multiplexing control circuit, and when it is "0", the data from the terminal device is sent, and when it is "1", the corresponding CH is set to "albi1". The reception control signal 110 similarly controls the reception signal, and when it is "L", the reception is ignored, that is, it is not output, and it is "0".
”, the reception output is normally output.

111-1 to 111-n are O-order TDMs that multiplex low-speed data from terminal devices (not shown) and connect them to the transmission bus. Alternatively, it is assumed that a device is provided that corresponds to the number of CHs, and is a device that performs multiple notarization on data received from the reception bus and delivers the data to a terminal device.

The following explanation will be given using 111-1 as an example.

112-1 is an address decoder which determines whether or not its own device has been selected based on a signal on the address bus. When the address signal matches that of the device itself, it is output and the next stage 113-1 transmission gate and 114-1 reception gate are opened. 115-1
is a transmission speed conversion circuit, 116-1 is NAND, l 17
-1 is OR.

118-1 indicates an AND gate, and 119-1 indicates a NAND gate. 120-1 is a reception buffer memory, 121-1
1 is a multiplexing circuit that multiplexes bearer rate low-speed data from a terminal device (not shown) to a rate of 64 Kb;
Reference numeral 22-1 indicates a demultiplexing device, and 123-1 indicates an all “1” code generating device that generates all “1” codes for the CI.

FIG. 11 shows an example of a transmission signal of the apparatus shown in FIG. 10, and provides a detailed explanation of FIG. 9.

Next, referring to FIG. 11, the operation of the device shown in FIG. 1θ will be explained.

(a) Regarding M1 station TDM1, address decoder 1 in O-order TDM-1 (111-1)
12-1 receives the address data on the address bus 106, and when it matches the address of its own device, outputs it, thereby transmitting the data to the transmitting gate 113-1. Receiving gate 114-1
open.

(Transmission operation) Low-speed data from a terminal device (not shown) is multiplexed at a speed of 64 Kb/s by a multiplexing circuit 121-1 (this is data A), and then sent to a NAND gate 119-
1 is input.

Since the NAND gate 119-1 opens when the transmission control signal 109 from the multiplex control circuit 100 is "0", data A passes through the OR gate 117-1 to the transmission speed conversion circuit 11.
5-1. Here, the speed of 64 Kb/s is converted to the speed of high-speed digital line 10, and the transmission speed is
The signal is output to the transmission bus 107 via the transmission line interface circuit 105 through the transmission line 113-1 and sent to the line 10 mentioned above.

Next, the address moves to CH2, so the address decoder 11
2-2 matches its own device, and the zero-order TDM 111-2 sends data B to the transmission bus 107. Similarly, θth TD
MI 11-3 sends data C on CH3.

In the 0th order TDMI 11-4, the transmission control signal 109 from the multiplex control circuit 101 is set to "1", so the NAN
D gate 119-4 is closed, AND gate) 118-4 is opened, and the output of a111'' encoding circuit 123-4 is 0R11.
The signal is inputted to the transmission speed conversion circuit 115-4 via the transmission speed conversion circuit 115-4. Thereafter, albi1'' is placed on ClI4 and sent out in the same manner.The same goes for CH5 and CH6.

(Reception operation) O-th order TDM 111-1 reception gate) 114-1 opens and the reception data is transferred from the reception bus 108 to the NAND gate 116-1.
1 is input. Since the reception control signal 110 from the multiplexing control circuit 100 is 0'', the reception signal CHI (data G) that has passed through BO2 is taken in and input to the reception buffer memory 120-1.The data G of CHI is The demultiplexing circuit 122-1 separates the data into low-speed data and sends it to the terminal device.Similarly, in the θ-order TDMI 11-2, data H is sent to CH2, and in the O-order TDMI 11-3, data H is sent to the terminal device.
Data ■ is received at H3.

However, in the θ-th TDMIII-4, the reception control signal 110 from the multiplex control circuit 100 becomes "1", so the NAND gate 116-4 does not open and the CH4 reception signal is not received. In other words, the received signal is ignored. Similarly 0
In the next TDMI l4-5°114-6, the reception control signal 110 is "1", so the CH5 and CH6 reception signals are all ignored.

(B) Regarding M2 station TDM2 (transmission operation) Transmission control signal 109 of multiplex control circuit 100 of M2 station TDM2 is set to 0°1.1.0.0 corresponding to CHI to CH6.
．． If set to 1, 0th order TDM111-1 to 111
-6 data G corresponding to cr-tt~CH6 from each
, all"1", all"1", data D, data E, all"l" are sent to the line IO. When this signal passes through B U 1 (5), its AND gate 57.58 outputs the output terminal 54. This results in a signal as shown in 52 of the figure.

(Receiving operation) The reception control signal 110 of the multiplexing control circuit 100 of the M2 station TDM2 is changed to 0°1, l, 0 . . . corresponding to C111 to CH6.
If set to 1.1, 0th order TDM111-1 to 11
From each of 1-6, data A, ignored, ignored, data J, and data are received from the M1 station, ignored, data A from the M1 station, data J from the M3 station, and data K from the M4 station.

, hereinafter referred to as M3 station TDM3. Regarding the M4 station TDM4, transmit signals and receive signals are similarly transmitted or received according to the preset transmission control signal 109 and reception control signal 110. Transmission control signal 109 from multiplexing control circuit 100 of each TDM. Each reception control signal 110 has a fixed route.

The signals time-division multiplexed in this way are branched or inserted at each branch point, and data is sent to each slave station.
It can also receive data from slave stations.

[Problem that the invention seeks to solve]

The conventional branch transmission system is configured as described above, and one route is assigned to each channel, which is fixed. Therefore, the transmission capacity for each route is fixed, and for example at night, when viewed from each slave station, the transmission capacity is in the upward direction, that is, M2-
Ml, M3-Ml.

It was not possible to flexibly respond to requests to increase the amount of data in the direction of M4→M1.

This invention was made to solve the above problems, and while maintaining the principle of uniform speed branching in a branch connection device, it is possible to flexibly deal with the amount of data on a route that changes depending on the time or time zone. The purpose is to obtain a branch transmission system.

[Means for solving problems]

For this reason, the branch transmission system according to the present invention allocates all or part of the allocated channels between slave stations for each information route between a specific slave station and the master station,
- It is characterized in that the number of channels is increased over time and the number of channels is changed over time to send and receive multiplexed signals.

[Effect]

The number of channels allocated to each information route is changed over time. As a result, a plurality of channels can be assigned to one direction at a certain time (or time period), and data can be transmitted smoothly without congesting the amount of data in a certain direction.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, the same numbers as in FIG. 10 indicate the same contents. 10
1 is a multiplex control circuit, which includes a microprocessor 10;
2 and memory 103, transmitting control signals 109. The reception control signal 110 can be set over a wide range and made variable.

Figure 2 shows the TO3TI of each TDM1-4 of M1-M4 stations,
T2. T3 shows an example of a setting pattern at each time or time zone, where ■ indicates an output setting table for the transmission control signal 109, and 2 indicates an output setting table for the reception control signal 110.

TO to T3 are examples of set time (or time zone) patterns; for example, To is a constant state, and T1 uses more ICH than usual to concentrate data from the M2 station and send it to the Ml station. Time pattern: Similarly, T2 uses more ICH than usual and concentrates data from M3 station.
T3, the time pattern for transmitting data to the station, is a time pattern in which more ICHs are used than usual and data is concentrated from the M4 station and transmitted to the M1 station. The output setting tables for the transmission control signal 109 and reception control signal 110 shown in tables (1) and (2) in FIG. The microprocessor μp102 controls the memory outputs to be output simultaneously according to each setting table when the settings are made.

In this way, in the time pattern TI, the transmission signal is
It can be done as shown in the figure. Similarly, the time pattern T2 can be configured as shown in FIG. 4, and the time pattern T3 can be configured as shown in FIG. 5.

FIG. 6 (al represents all of these.

If we look at the number of CHs transmitted in the direction of H2-M1 stations, the number of CHs transmitted in the direction of M3-M1 stations, and the number of COs transmitted from M4 to M1 stations at each hour 1, the results are as shown in FIG. 6 (bl). That is, at time TI, data can be transmitted from M2 to M1 using 2 channels, CHI and CH4.At time T2, data can be transmitted from M2 to M1.
→Data can be transmitted to M1 station using 2 CHs, CH2 and CH4. At time T3, data can be transmitted from M4 to M1 station using CH3 and 2C11 of C116. In such a case, the time TO1TI,
T2. By changing the T3 interval, the amount of transmission can be increased for routes with a large amount of data.

In this embodiment, since the bidirectional branching and connecting device is constituted by an AND gate as shown in FIG. 8, all "1" is transmitted for the CHs with hatches as shown in FIG. In the 0th order TDMIII-1 to n in FIG. If it is composed of NAND gates, it will transmit all "1" (all "0"), and therefore 123-1 to 123-n become all "O" code generation circuits.

In FIGS. 2 and 3, the number of channels allocated to each station is one, but the same applies if a plurality of channels are allocated to each station depending on the amount of data.

FIG. 6(C) shows another pattern setting in which each CH assigned at constant time To (always) is
Time TI, T2. T3 indicates that it can be changed as shown here. That is, at time TI, M2→M1
In addition to CHI, 3 channels of C1 (5 and CH6) are assigned to the stations. At that time, CH2 is assigned to M3-M1 stations and M4→M1 stations.
, CH3 are assigned to each ICH. In this way, when the amount of transmission between slave stations is small, this C
H can be used to increase the transmission capacity between the master station and the slave station.

〔Effect of the invention〕

As explained above, this invention transmits and receives multiplexed signals by changing the number of channels assigned to each information route over time, making it possible to efficiently transmit and receive information according to the time zone. becomes.

[Brief explanation of drawings]

Figures 3 to 5 are status diagrams of channel assignment and transmission signal examples; Figure 6 (a), (1+), and (C) are channel assignment change diagrams and transmission/reception status diagrams; Figure 1θ is conventional multiplexing The apparatus configuration diagram, FIG. 11, is a diagram showing channel allocation and transmission/reception status according to the conventional system. Agent Masu Oiwa T& (and 2 others) - Mitsuto

Claims (1)

[Claims] When transmitting and receiving digital signals between a master station and multiple slave stations via a high-speed digital line, channels are provided according to the number of route combinations between the master station and slave stations, and between the slave stations, and these channels are time-division multiplexed. Configure a multiplexed signal, allocate information or control information for each destination to each channel,
In addition, in a branch transmission method for digital signals that is transmitted via a branch connection device installed in the middle of a high-speed digital line, all or part of the channels between slave stations are connected to a specific slave station and the master station at predetermined time slots. A branch transmission method for multiplexed signals, which is characterized in that data is intensively allocated for data transmission between stations, and data is collected from all or some of the slave stations by changing the specific stations.