KR0129607B1 - Atm multichannel switch with grouping - Google Patents

Abstract

An ATM multi-channel switching means enables to provide the service above an input port velocity as well as a super rate velocity due to be appointed an one port as an one group. The said switching means consist of a input processor(21) regulating the synchronism between the cells, a channel grouping means(22) grouping the output cells depending on the switch control data, a trap means(30) deciding to request the switching and feedbacking the channel to the input processor, and a routing means(24) routing the cell where output from the trap means.

Description

ATM Multichannel Switches with Grouping / Trap / Routing Architecture

1 is a functional block diagram of a general multichannel switch.

2 is a block diagram illustrating a configuration of a multichannel switch according to the present invention.

3 is a format configuration diagram of a control data cell used in the present invention.

4 is a detailed block diagram of the input processing unit of FIG.

5 is a detailed configuration diagram of the trap part of FIG.

6 is an explanatory diagram for explaining a conversion process between input data and output data cell formats in FIG.

7 is a diagram illustrating a Baynan network used as a routing unit of FIG.

8 is an explanatory diagram showing an application example of the present invention.

9 is an explanatory diagram showing another application example of the present invention.

* Explanation of symbols for main parts of the drawings

21: input processing unit 22: channel grouping unit

23: trap portion 24: routing portion

The present invention relates to an Asynchronous Transfer Mode (ATM) multichannel switch having a grouping / trap / routing structure, and more particularly, to an ATM multi-group having a grouping / trap / routing structure for grouping a plurality of ports and processing cells in groups. It is about a channel switch.

The conventional ATM cell switching method has a structure in which a cell is switched from one input port to a specific output port, that is, a one-to-one correspondence in terms of port.

In addition, a general multi-channel switch as shown in FIG. 1 groups a plurality of ports to correspond one-to-one between groups, and a cell input to any port in an arbitrary group can designate a group to be outputted. Output to a specific port was not possible, ie output to any port in the specified group. Therefore, the conventional multi-channel switch has a problem that can not accommodate the service more than the speed of the input port.

Accordingly, the present invention has been made to solve the above problems, and by designating one port as a group, it can accommodate not only the speed of the input port but also the service of the super-rate speed. It is an object of the present invention to provide an ATM multi-channel switch having a grouping / trap / routing structure.

In order to achieve the above object, the present invention, the input processing means for controlling the reading of the cell input from the outside, and adjusts the synchronization between the cell input from the outside and the cell is fed back; Channel grouping means for grouping cells output from the input processing means according to switch control data; A trap unit which determines whether the channels grouped by the channel grouping means require switching beyond a capacity of a corresponding channel, and feeds back channels that require switching above the channel capacity to the input processing means; And routing means for routing the cell output from the trap unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a configuration of a multichannel switch according to the present invention, and includes an input processing unit 21, a channel grouping unit 22, a trap unit 23, and a routing unit 24. .

The input processing unit 21 performs a read control of a cell input from the outside, a synchronization between the cell inputted from the outside and a cell that is blocked and fed back and performs a control of transferring control data to the channel grouping unit 22. .

The channel grouping unit 22 continuously outputs channels of the same group among the input switch control data to an M + 1, M + 2, ... port starting from an arbitrary output port M, and the trap unit 23 is grouped. It is determined whether the channels require switching above the capacity of the corresponding channel, and the channels requiring switching above the channel capacity feed back to the switch input simultaneously with the cell input from the outside at the next cell time. For example, if there are N ports in the group A and the number of input cells requesting switching to the group A is N + X, the trap unit 23 outputs N cells to the routing unit 24, and the remaining X The two cells feed back to the input of the channel grouping unit 12. Before entering the routing section 24, the number of the port to be actually output is assigned. In the present invention, the routing section 24 uses a banyan network which is a self-routing network.

In addition, the switch of the present invention separates the path of the switch control cell and the path of the data cell, first sets the data path to the switch through the switch control cell, and then switches the data. Therefore, the control cell and the data cell must be multiplexed internally, and the switching speed must be increased by the sum of the number of clocks required by the data cell control cell. This problem can be solved by configuring the switch in the bit slice method described later.

3 shows the structure of control data input for setting a path of a multichannel switch.

The CGN (Channel Group Number) field indicates the group number of the cell to be switched, the GC (Group Capacity) field indicates the maximum number of ports assigned to the group, and the GSP (Group Start Port) field indicates the port where the group starts. For example, if the group A has 4 ports, the group B has 3 ports, and the group C has 2 ports, the GSP value of the cell to be output to group A is 0 and the cell to be output to group B The GSP of is 4, and the GSP of the cell that you want to output to the C group is 7.

4 is a detailed configuration of the input processing unit. The control data shown in FIG. 3 is determined by the number of input ports. For example, if the number of input ports is 16, 4 bits are required because the total number of CGN is 16. However, when 5 bits are allocated to distinguish unallocated cells, K = 5.), The multiplexer 42 outputs the output of each D-flipflop. Multiplex After a bit of CGN is input, in order for the non-block group network (NBGN), the channel looping unit 22, to complete its operation, r (N = 2 exp r, N = number of external input ports + number of internal input ports) A clock is required and the NBGN's pass is set when the operation is complete. Therefore, the multiplexer control unit 42 outputs one bit of CGN, and after the r clock passes, controls the next GNC bit to go out so that the CGN value of the K bits can set the NBGN of the K stage. According to the output of the multiplexer 42, the next CGN bit is latched at the time each NBGN completes its operation.

5 shows a detailed configuration of the trap 23.

Grouped channels form a contiguous port group, and the SN (Sequence Number) generation unit 51 sequentially allocates SNs to the corresponding ports of channels belonging to the same group starting from 0, and compares the GC / SN and port assignment unit 52. ) Compares the values of the SN and GC fields to block cells if the channel exceeds the number of ports to be output, and classifies them as otherwise routed cells. For example, if the GC value is 3 and the SN value of any channel is 3 or more, all ports in the same group thereafter are blocked, and the non-blocked cells are assigned to the GC / SN comparison and output port assignment unit. At (52), the GSP value is output through the actual output port that adds the SN value. As shown in FIG. 6, the cells that are passed and the cells that are blocked are mixed in the output of the GC / SN comparison and port number assignment unit 52. If the pass / blocking bits are grouped using the trap NBGN 53, it is possible to distinguish the blocking cells from the non-blocking cells. The blocked cell is fed back to the input processing unit 21 while maintaining the original cell format, and repeats the above process at the next cell time. In addition, the feedback cell always has a higher priority than an external input cell in the multichannel switching structure.

FIG. 6 is a diagram illustrating a process of converting input data and output data cell formats in a trap part. PA bits are self-routing in the routing part 24, that is, in a Bannan router, when the bit after the P bit becomes the MSG. do.

Cells entered into the routing network have P (Passed) and PA (Port Assigned) bits in the format, set up a pass according to the self-routing method to the Banyan network of FIG. 7, and transmit data cells along the path. Let's do it.

However, outputting a data cell by setting a switch path to a control cell when a high-speed cell is input to a multichannel switch has many problems in current semiconductor technology. Therefore, in order to accommodate this at low speed, as shown in Fig. 8, the input data is serially converted into L bits, and then the control cell data is preceded and switched to switch the high speed input cell to the low speed clock. . In this case, however, the switch chip is increased to L as shown in FIG.

9 is a diagram illustrating a method for accommodating a super-rate service. The input cell is distributed to multiple ports of the same channel group using a demultiplexer, and then the distributed cells are switched and the switched cells are switched. Since the cell order within the group is multiplexed and outputted again, the input rate is faster than the switching speed of the switch.

As described above, the present invention can designate one port as a group, and can accommodate not only the speed of the input port but also the service of the super-rate speed.

Claims (5)

Input processing means (21) for controlling the reading of cells input from the outside and adjusting synchronization between cells input from the outside and cells blocked and fed back; Channel grouping means (22) for grouping cells output from said input processing means (21) according to switch control data; It is determined whether the channels grouped by the channel grouping means 22 require switching beyond the capacity of the corresponding channel, and the trap unit 30 for feeding back the channels that require switching above the channel capacity to the input processing means 21. ); And routing means (24) for routing the cells output from the trap section (30). The method according to claim 1, wherein the input processing means (21) comprises: a number of input port + one serially connected latch means (41) for receiving and relocating control data; Multiplexing means (42) for receiving and outputting each output of the latching means; And multiplexing control means (42) for controlling the operation of the latching means (41) and the multiplexing means (42). 3. The multiplexing control means (42) according to claim 2, wherein the multiplexing control means (42) outputs one bit of CGN and then the next GNC bit after r (N = 2 exp r, N = number of external input ports + number of internal input ports) clocks. Multi-channel switch having a grouping / trap / routing structure, characterized in that configured to control the output. 2. The apparatus of claim 1, wherein the trap means (23) comprises: SN generating means (51) for sequentially assigning a sequence number (SN) to a corresponding port of a channel belonging to the same group; GC / SN comparison and port assignment means (52) for classifying input cells into blocking cells and passing cells by comparing the SNs assigned by the SN generation means (51) and the values of the GC fields; And a trap NBGN means 53 for feeding back the blocking cell output from the GC / SN comparison and port assignment means 52 to the input processing means 21 and outputting a passing cell to the routing means 24. ATM multichannel switch having a grouping / trap / routing structure. 2. The ATM multi-channel switch as claimed in claim 1, wherein said routing means is a Banyan network.