JPH0124384B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal modulation device for including arbitrary frequency components in a digital signal sequence.

Conventionally, in digital relay transmission systems, in order to locate the fault location when a system failure occurs, a terminal station sends out a digital signal sequence that repeats a specific bit pattern as a repeater identification signal, and the repeater receives this digital signal. A bandpass filter extracts the fundamental frequency component corresponding to the repetition period of the series, and further controls control operations corresponding to the extracted fundamental frequency, such as a signal loop switch or a switch to switch to a backup circuit. A remote control method has been proposed. In this method, it is assumed that the bit frequency of the digital signal sequence is b (bits/second), the aforementioned fundamental frequency is m, and a specific bit pattern that is repeatedly sent out is composed of m bits. If the print period is expressed in m (bits), then m is expressed as _n = _b /m (1). As is clear from this equation, since m is an integer, frequencies between b/m and b/(m±1) cannot be used as signals for repeater identification or control operation identification as described above. There are restrictions.

This restriction is not a big problem in small-scale systems with few repeaters, but it becomes a big problem in long-distance systems, such as trans-Pacific submarine optical submarine cable systems.

In other words, if the system length is 10,000 km and the relay interval is
If the distance is 50km, the number of repeaters will be 200 in one direction and 400 in both directions, and 400 frequencies will be required just to identify the repeaters. Additionally, it can be used as a bandpass filter for frequency extraction installed inside the repeater.
If an MCF (monolithic crystal filter) is used, its stable operating range is
The frequency band that can be used as a repeater identification signal is 4 to 8 MHz if the frequency is 4 MHz or more, and if there is no double frequency relationship between the repeater identification signals.
Since the fractional band of MCF is about 1×10 ^-3 , 4~
At least 500 (8MHz
× (fractional band) = 8KHz, (8-4)MHz/8KHz = 500) frequencies can be arranged. However, when using a digital signal sequence, from equation (1), b is 300Mbps and m is 4Mbps.
If it is Hz, m is 75 bits, and if it is 8MHz, it is 37 or 38 bits, so it is at most suitable as a repeater identification signal.
This means that only about 37 waves (75-38) can be prepared.

Therefore, the present invention aims to improve the above-mentioned drawbacks of the conventional technology, and aims to provide a digital signal modulation device that can include a large number of frequency components in a digital signal sequence, and is characterized in that the repetition period is A first pseudo-random signal generator (PNG ₁ ) generates _a digital signal sequence according to a pattern of m bits; A second pseudo-random signal generator (PNG ₂ ) that generates a pseudo-random signal P _x at intervals
and a circuit for adding at least one bit after the first pattern of the output of the first pseudo-random signal generator when the pseudo-random signal P _x has a specific code, P _x
The digital signal modulator modulates the repetition period of the output of the first pseudo-random signal generator (PNG ₁ ) according to the occurrence of a specific code. Examples will be described in detail below.

FIG. 1 shows a pseudorandom signal generator having an arbitrary period of m bits necessary for constructing the present invention.
FIG. 2 is a diagram illustrating an example of PNG1, in which a shows a block diagram and b shows an output signal. In Figure 1a,
b ₀ , b ₁ to b _N are 1-bit delay elements, and b ₁ to b _N constitute an N-bit shift register S1. w ₁ and w ₂ are exclusive OR circuits, 1 is a word detector, CK1 is a clock input terminal, and 2 is an output terminal for a pseudorandom signal P1 having an arbitrary period of m bits and a mark rate of 1/2. Shift register S1 is a clock input terminal
A pseudo-random signal is generated by shifting according to the clock from CK1, but when the states of delay elements b ₁ to b _N forming the shift register S1 match a specific pattern preset in the word detector 1, a word is detected. The output from device 1 causes the device to return to its initial state. The number of output bits from this initial state to the specific pattern set in the word detector 1 can be calculated in advance from the circuit configuration, so by changing the pattern of the word detector 1, a pseudorandom signal with an arbitrary period m can be generated. P1 can be obtained.

FIG. 2 shows a pseudo-random signal generator PNG2 having a mark rate x necessary for configuring the present invention. The mark rate x is set at intervals of 1/16 to 1
An example is shown in which the value can be varied within the range of 5/16. In FIG. 2, PNG ₂₁ , PNG ₂₂ , PNG ₂₃ , and PNG ₂₄ are pseudorandom signal generators with a mark rate of 1/2, respectively, and have the same configuration as PNG 1 in FIG. 1a.
However, the repetition period of PNG _{21 to 24} is as shown in Figure 1 a.
It needs to be sufficiently longer than m bits, which is the period of PNG1. The reason for this will be explained later. A ₂ to _{A 4} are AND circuits, R ₁ to _{R 4} are OR circuits,
The mark rates at these outputs are (x ₁ × x ₂ ) and (x ₁ + x ₂ ), where the mark rates of the two inputs are x ₁ and x ₂
−x ₁ ×x ₂ ). _I2 to _I8 are inverter circuits, and the mark rate at the output is (1-x) where x is the mark rate of the input signal. b is a 1-bit delay circuit for reducing the correlation between signals. 21 to 35 are output terminals for pseudorandom signals having a mark rate of 1/16 to 15/16, and the desired output is actually selected by a rotary switch, etc., but the selection circuit for this can be easily configured. It is not shown because it can be done. Also, CK ₂ is a clock input terminal, and the input clock is PNG _{21 to 24} ,
It is distributed to A ₂ to _{A 4} , R ₁ to R ₄ , I ₂ to I ₈ and b, but the distribution circuit is omitted to simplify the diagram.
In Fig. 2, PNGs _{21 to 24} are separate pseudo-random signal generators, but it is also possible to use one pseudo-random generator and use a signal whose output is delayed one bit at a time, or use a shift register S. A signal from _one suitable delay element may be used. Also, if l pseudo-random generators are used, mark rate x
can be set at intervals of x = 1/2l.

FIG. 3 is a diagram showing an embodiment of the present invention.
PNG ₁ is the pseudo-random signal generator explained in FIG. 1a, and PNG ₂ is the pseudo-random signal generator explained in FIG. _A6 is an AND circuit, _I1 is an inverter, and _A6 and _I1 operate as an inhibit circuit for the system clock signal input from _CK3 .

Next, the operating principle of the embodiment will be explained. first,
The detection pulse 2 output when word detector 1 in PNG ₁ detects a preset specific bit pattern in shift register S ₁ is PNG _2.
is applied to clock input terminal 2 of . Therefore
Pseudo-random signal Q, which is the output of PNG ₁ , has a period m
If word detector 1 were set to have bits, PNG ₂ would generate a pseudo-random signal Px at intervals of m bits. When P _x is "1", the clock signal input from CK ₃ is blocked by A ₆ and I ₁ . Therefore, since PNG ₁ is reset, the pseudo random signal Q is “0”.
1 bit is added, and the period (m+
1) A bit pattern has been added.
When P _x is "0", the clock signal is not blocked, so PNG ₁ outputs a pattern with a period of m bits. Therefore, the pseudo-random signal Q has a period m
A pattern of bits and a pattern of period (m+1) bits coexist.
+1) is equal to the mark rate x of the pseudo-random signal P _x . In this case, the fundamental frequency component _ix of the pseudorandom signal Q is _n = _b / m.
The frequency is between _n+1 = _b /(m+1) and depending on the mark rate x, the frequency is given by _ix = _b /(m+x). However, if the appearance of a pattern with period (m+1) bits in pseudo-random signal Q has periodicity, a spectrum component corresponding to this period and its harmonic components will appear, so
1) The appearance of the bit pattern must be sufficiently random, and this is also the reason why it is necessary to lengthen the period of the pseudorandom signal P _x .

In the above explanation, a pseudo-random signal with a period of m bits was used as the output of PNG ₁ , but a pseudo-random signal with a period of 2 m bits, in which "0" and "1" are inverted for every m bits over one period, was used. May be used.

Furthermore, in the above explanation, when the _pseudo -random signal _P When a ``1'' appears at the output of _{CK 2} , the clock signal from CK ₃ may be blocked for k bits, and k bits may be added next to the m-bit periodic pattern. If we rephrase the (m+k) bit pattern at this time as a period n-bit pattern, we can say that the fundamental frequency of the pseudo-random signal Q is
_ix can be expressed by a general formula such as the following formula (2).

_ix = _b / [m-x (m-n)] (2) Figure 7 shows the fundamental frequency generated by the present invention.
FIG. 6 is a diagram showing an example of the spectral distribution of _ix . The horizontal axis shows _ix / _b , which is _ix normalized by _b , and the vertical axis shows the spectral distribution at a scale of 10 dB.

In this example, m = 35, x = 1/16, and 50,000 bits (corresponding to 167 μS when _b is 300 M _bps ) are used. However, if an even steeper spectrum distribution is desired, the number of bits used can be changed. In other words, the pattern sending time may be increased.

As explained above, according to the present invention, since any fundamental frequency component can be created using a digital signal sequence, the identification frequency for remote control in a digital transmission system can be arbitrarily set.
The effect is great.

Next, a digital repeater remote control system to which the present invention is applied will be described.

FIG. 4 is a diagram showing the outline of a digital relay transmission system, where M is a terminal station, R ₁₁ , R ₂₁ , ..., R ₁ , k-
1, R ₂ , k-1, R ₁ , k, R ₂ , k, R ₁ , k+
1, R ₂ , k+1,..., R ₁ , n, R ₂ , n is a regenerative repeater, l is an optical fiber, q ₁ ,..., q _k-1 , q _k ,
q _k+1 ,..., q _o are switch circuits, C ₁ ,..., C _k-1 ,
C _k , C _k+1 , ..., _Co are control signal detection circuits.
In explaining an application example of the present invention, a digital optical regenerative repeating system using an optical fiber will be explained as an example. FIG. 4 shows an example in which the remote control method using the digital signal modulation method according to the present invention is applied to the control of a switch circuit for turning back a transmission line code error rate measurement signal in fault search. A remote control signal (pseudo-random signal Q explained in Fig. 3) is sent from a specific repeater.
When the control signal detection circuit C _k of R _1k detects the fundamental frequency of the remote control signal mentioned above, it makes the switch circuit q _k conductive, returns the remote control signal itself, and sends the terminal station M
The terminal station M can measure the bit error rate of the transmission path from the received remote control signal, and by performing such loopback control for each relay section, it is possible to locate the degraded section of the transmission path.

FIG. 5 is a diagram illustrating the configuration of the control signal detection circuit C _k built into each repeater in FIG.
k ₁ is a bandpass filter, k ₂ is a rectifier circuit, k ₃ is an integration circuit, and k ₄ is a threshold circuit. Next, the operation will be explained. Remote control signal Q sent from terminal station M
When input to the control signal detection circuit C _k built in the specific repeater R ₁ , k, it first enters the band pass filter k ₁ , and if the fundamental wave component of the remote control signal is in the passband of k ₁ , , is rectified by rectifier circuit k ₂ , passes through integration circuit k ₃ having a predetermined time constant, and when an output exceeding a certain specified value is obtained, threshold circuit k ₄ is used to drive switch circuit q _k . A control signal is output. Therefore, during the time when this remote control signal Q is being transmitted from the terminal station, the switch circuit q _k
maintains conduction, and the remote control signal Q passes through the switch circuit q _k and is returned to the terminal station.

FIG. 6 is placed in the terminal station M in FIG.
This is a diagram showing the configuration of a transmission line code error rate measurement circuit, which receives a remote control signal Q that has been looped back at a specific repeater and returned to the terminal station M, and measures the transmission line code error rate. be. In FIG. 6, D ₁ ,
D ₂ is a synchronization circuit, F ₁ and F ₂ are RS flip-flop circuits, E ₁ and E ₂ are 1-bit delay circuits, and A ₂ to _{A 5} are
AND circuit, I ₂ to I ₄ are inverters, w ₃ to _{w 6} are exclusive OR circuits, Z is an error pulse counter, C _k is a clock input terminal, R is a reset input terminal, S is a set terminal, PNG ₁ , PNG ₂ is a pseudo-random signal generator, which is the same circuit as PNG ₁ and PNG _{2 explained in FIGS. 1 and 2} .

Next, the operation will be explained. The received remote control signal Q is connected to the exclusive OR circuit w ₃ along with the output Q′ of PNG ₁
The mismatch pulse is input to the synchronization circuit _D1 and the AND circuit _A4 . For synchronization, first synchronize to a certain number of m bits (first pattern) with a high probability of occurrence, and then synchronize to (m+1) bits (second pattern) whose probability of occurrence is equal to the mark rate x. By this, the remote control signal Q
Synchronize everything. In the synchronization circuit D ₁ ,
PNG ₁ output period m bits, or (m+1)
The number of mismatched pulses is counted for each bit, and when the number of mismatched pulses exceeds a certain specified value, it is assumed that the frame is out of synchronization, and "1" is sent as an output signal, and the inverter I ₄ ,
The signal is applied to the clock input terminal _Ck of PNG ₁ via the AND circuit _A3 , the clock disappears by one bit, and the output delayed by one bit is sent out as Q'.
The above operation is repeated until the frames of the remote control signals Q and Q' are synchronized, and when the count of mismatched pulses becomes less than the specified value, it is assumed that the frame synchronization has been achieved, and the output of the synchronization circuit _D1 is
Since “0” is sent out, it passes through the 1-bit delay circuit _E1 , and the output of the exclusive OR circuit _w5 becomes “1”.
Enter the set input of RS flip-flop _F1 . Therefore, the output of _F1 becomes "1" and makes AND circuit _A5 conductive. Therefore, the output from the synchronization circuit _D1 and the output from the pseudorandom signal generator _PNG2 are input to the exclusive OR circuit _w4 , and the mismatched pulse is
It passes through _w4 and is input to synchronization circuit _D2 . This synchronization circuit D ₂ is configured to be reset at every specified time, and when the number of mismatched pulses exceeds the specified value, it is considered that the synchronization is out of synchronization, and the clock loss signal is sent to the inverter I ₂ and the AND circuit. _A2 is applied to the clock input terminal of the pseudorandom signal generator _PNG2 . Therefore, the PNG ₂ clock erases only one bit and the PNG ₂ output produces an output signal delayed by one bit. The above operation is repeated until the PNG ₂ output signal and the D ₁ out-of-synchronization signal are synchronized, and when synchronization is achieved, the D ₂ output becomes “0”.
Therefore, when this signal and the 1-bit delay circuit _E2 are passed through the exclusive OR circuit _w6 , the output becomes "1", the output of the RS flip-flop _F2 also becomes "1", and the AND circuit _A4 becomes conductive. Make it. In other words, when the period is m, if PNG ₁ is delayed one bit at a time and synchronized with PNG ₁ on the transmitting side, the synchronization circuit D ₁
The output of F1 becomes 0, and flip-flop _F1 is set. In this state, when the period is (m+1), PNG ₂ is out of synchronization, so synchronization circuit D ₁ outputs out-of-sync signal 1 again, and synchronization circuit D ₂ also outputs an out-of-sync signal. , PNG ₂ to 1
Delay bit by bit. When PNG ₂ is synchronized with the transmitting side, the output of synchronization circuit D ₂ becomes 0 and flip-flop F ₂ is set. This operation is expressed as the period when (m+1) bits appear (mark rate x)
Repeat until it matches. This state is a state in which synchronization is achieved in both periods m and m+1. Therefore, by counting the error pulses that have passed through _w3 with an error pulse counter Z, the transmission line code error rate can be measured. In the above explanation, the period of the pseudo-random signal generated from the pseudo-random signal generator PNG ₂ is very long, and it takes a considerable amount of time to synchronize, which is equivalent to the round trip time to the repeater that should be remotely controlled. Since the delay time is known in advance, it is necessary to set the internal state of PNG ₂ so that the phase is slightly ahead of the delay time. In addition, although a pseudo-random signal with an m-bit period was used here, each m-bit is "1",
A pseudo-random signal with a period of 2 m bits, in which "0" is inverted over one period, may be used.

In the above explanation, the remote control method of the present invention was applied to remote control of a return switch for troubleshooting.
It is clear that the present invention can also be applied to remote control of redundant spare elements in repeaters and switches to spare circuits.

As explained above, according to the present invention, an economical and highly reliable digital repeater remote control method is provided without using intervening lines, and it can be used in large-scale systems such as long-distance optical submarine cable systems. The effect in this case is remarkable.

[Brief explanation of drawings]

Figure 1a is a block diagram of a circuit that generates a pattern with a mark rate of 1/2 with a period m, and Figure 1b is a block diagram of a circuit that generates a pattern with a mark rate of 1/2 with a period m.
Figure 2 is a block diagram of a circuit that generates a pattern with an arbitrary mark rate with a period n.
FIG. 3 is a block diagram of a digital signal modulation circuit according to the present invention, FIG. 4 is a schematic diagram of a digital relay transmission system to which the present invention is applied, FIG. 5 is a block diagram of the control signal detection circuit in FIG. 4, and FIG. This figure is a block diagram of the transmission line code error rate measuring circuit in FIG. 4, and FIG. 7 is a diagram showing the distribution of the fundamental frequency _ix generated according to the present invention. PNG ₁ , PNG ₂ , PNG ₂₁ to PNG ₂₄ ...pseudo random signal generator, _b0 , _b1 to _bN ...1 bit delay element, w1 _{, w2} ...exclusive OR circuit, 1...word Detector, A ₂ to A ₆ ...AND circuit, R ₁ to _{R 11} to OR circuit, I ₁ ... Inverter, C _k ... Clock input terminal, S ₁ ... Shift register, M ... Terminal, R ₁₁ ,
R ₂₁ ,..., R ₁ , k-1, R ₂ , k-1, R ₁ , k,
R ₂ , k, R ₁ , k+1, R ₂ , k+1,..., R _1o ,
R _2o ... regenerator, l ... optical fiber, q ₁ ,...,
q _k-1 , q _k , q _k+1 , ..., q _o ... switch circuit, C ₁ ,
..., C _k-1 , C _k , C _k+1 , ..., _Co ... control signal detection circuit, PNG ₁ , PNG ₂ ... pseudo random signal generator,
S ₁ ...Shift register, 1...Word detector,
b ₀ , E ₁ , E ₂ ... 1-bit delay circuit, w ₁ to w ₆ ...
Exclusive OR circuit, A ₁ ~ _{A 5} ...AND circuit, I ₁ ~ I ₄ ...
...Inverter, C _k ...Clock input terminal, Q...
...remote control signal, P _x ...pseudo-random signal with mark rate x, _k1 ...bandpass filter, _k2 ...rectifier circuit, _k3 ...integrator circuit, _k4 ...threshold circuit,
_D1 , _D2 ...Synchronization circuit, _F1 , _F2 ...RS flip-flop, Z...Error pulse counter.

Claims (1)

[Claims] 1. A first pseudo-random signal generator (PNG ₁ ) that generates a digital signal sequence in a pattern with a repetition period of m bits; and the first pseudo-random signal generator (PNG ₁ ).
a second pseudo-random signal generator (PNG ₂ ) that receives pulses of every m bits from the PNG 2 and generates a pseudo-random signal P _x at m-bit intervals; when the pseudo-random signal P _x has a specific code; a circuit for adding at least one bit after the first pattern of the output of the first pseudo-random signal generator, the pseudo-random signal P _x
A digital signal modulation device, characterized in that the repetition period of the output of the first pseudo-random signal generator (PNG ₁ ) is modulated according to the occurrence of a specific code.