SU1478357A1 - Digital radio relay transmission system - Google Patents

Abstract

This invention relates to a multi-channel radio relay. The purpose of the invention is to increase the capacity of the system. To achieve the goal, new blocks and links between them are introduced into the system. In addition, a balanced 4B6B alphabetic code is used to transmit information in the proposed system. At the outputs of the parallel register, there are simultaneously four signals in the time interval equal to two clock intervals of the original binary signals. In accordance with the table in the first converter, four symbols of the original signal and six symbols of the transmitted signal are converted. The use of this code also makes it possible to increase the reliability of operation of clock synchronization devices in regenerators. 3 ill., 1 tab.

Description

I

The invention relates to a multichannel radio relay communication and can be used in the construction of digital radio relay transmission systems.

The purpose of the invention is to increase the capacity of the system.

Figure 1 shows the structural diagram of a digital radio relay transmission system; 2 is a block diagram of a frequency switching unit; FIG. 3 is a block diagram of a second synchronization unit.

The digital radio relay transmission system comprises a compaction equipment 1, auxiliary compaction equipment 2, first, second, third and fourth receiving regenerators 3-6, first, second, third and fourth transmitting regenerators 7-10, frequency switching unit 11, first, second and third serial registers 12-14, first and second parallel registers 15 and 16, first and second converters of codes 17 and 18, first, second and third parallel-serial registers 19-21, first and second synchronization blocks 22 and 23, master oscillator 24 , phase the first detector 25, the first and second frequency dividers 26 and 27, the decoder 28, the cable line bus 29, the first and second input-cable blocks 30 and 31, the source of the 32 service signaling signals, the receiver 33 of the service signal, the first second and third filters 34-36, frequency

four

00 00

ate

a detector 37, a frequency-modulated oscillator 38, an intermediate frequency amplifier 39, an adder 40, a duplexer 41, a frequency converter 42 and an antenna 43.

The frequency switching unit contains a HE element 44, D-triggers 45 and 46, AND-NOT elements 47-50, integrating circuits 51-54, AND 55 and 56 elements, HE 57 element, AND 58 element, OR element 59.

The second synchronization unit contains a pulse shaper 60 and 61, an OR 62 element, accumulators 63-67, a narrow pulse shaper 68-72, an OR 73 element, an AND 74 element, D-triggers 75-80, a phase detector 81, a frequency divider 82, specifying generator 83 with a control element.

Digital radio relay system works as follows.

Digital signals from the outputs of equipment 1 and 2 of the seal, which can be used, for example, commercially available equipment PCM-15, are fed to the inputs of the fourth 6 and third 5 receiving regenerators, respectively. The compaction equipment 1 and 2 may be at a sufficient distance, which leads to a distortion of the transmitted signals. The regenerators 5 and 6 are designed to restore the form of the transmitted digital signals and extract the clock frequency signal. In the presence of a digital signal at the output of the compression equipment 1, the clock frequency signal from the output of the first receiving regenerator 3 is fed to the second input of the frequency switching unit 11. Since the output potential of the output element And 55 is resolving potential, this clock signal passes through the element And 56 and the element OR 59 and arrives at the output of the frequency switching unit 11. When the seal equipment 1 fails to function at the first output of the frequency switching unit 11, there is no clock frequency signal. In this connection, the inhibiting potential appears at the output of the And 55, and the permitting potential at the output of the HE 57. Therefore, the output of the frequency switching unit 11 passes the clock frequency signal from the output of the third receiving regenerator 5 through the element 58 and the element OR 59.

or 2 seals do not affect the transmission of information, respectively, of the apparatus 2 or 1 seals. The clock signals arriving at the first and second inputs of the frequency switching unit 11 are synchronous. This is due to the fact that the compaction equipment 1 and 2 is synchronized by fire of synchronous digital streams coming from the outputs of the third 9 and fourth 10 transmitting regenerators.

For information transmission in a digital radio relay transmission system, a balanced alphabetic code 4В6В is used, the code table of which is as follows.

Source Signal Code Groups

0

About 0. About About 0001 0010 0011 5 0100

About About About About About

1011

1 1 1 1

O 1 1 o

LTD

oh oh oh

O 0 1

1 o

eleven

About 1

eleven

oh oh

011100

0

five

1000 O 0 1 O 1 O O 1 1

1 1 1

10001

one

oh oh

01

1O

t 1

0010

oh oh

oh oh

01100 10001 10010 1 0 1

O 1 o

1 about o

0

five

0

five

Signals reconstructed in the fourth 6 and third 5 receiver regenerators are recorded accordingly. In the first 12 and second 14 successive registers, the clock signal from the output of the frequency switching unit 11 and the clock frequency signal divided into two in the first frequency dividers 26 are recorded in the first parallel register 15. Thus, the outputs of the first parallel register 15 are present simultaneously four signals on a time interval equal to two clock intervals of the original binary signals.

In accordance with the table in the first converter 17, four symbols of the original signal and six symbols of the transmitted signal are converted.

Presented at the output of the first converter 17 in parallel form, the six symbols of the code group are converted in a parallel-serial register into a serial signal, which arrives at the transmitting regenerator 7 and then through the first input-cable unit 30 into the cable communication line. The operation of the first parallel-serial register 21 is controlled by the signals from the outputs of the synchronization unit 22, made in the form of a phase locked loop (PLL), namely from the output of the master oscillator 24 and the frequency divider 27 by six. The synchronization in the PLL is performed by a divided frequency, namely, the clock frequency of the original digital signal is divided into two in the first frequency divider, and the frequency of the master oscillator 24 is divided into six in the second frequency divider 27.

The coded signal, passed through the cable communication bus 29 and through the second lead-in block 31, is fed to the recovery regenerator 3 for recovery and then to the adder 40, to the second input of which service signals are transmitted, passed from the output of the service communication signal source 32 zy chain: the first input-cable unit 30, the cable line bus 29 and the second input-cable unit 31. The total signal at the output of the adder 40 is modulating for the frequency-modulated generator 38. The frequency-modulated signal "through the third filter 36 and duplexer (waveguide coupler) 41 are fed to antenna 43.

The received frequency-modulated signal (at a different carrier frequency) comes from antenna 43 through duplexer 41, frequency converter 42 and amplifier 39 to the input of frequency detector 37. In filter 35, service signals are extracted from the total signal through the second input-cable the block 31, the cable line bus 29 and the first lead-in block 30 are fed to the input of the service signal receiver 33. The digital signals allocated by the filter 34 and reconstructed in the second transmitting regenerator 8 are fed through the second lead-in block 31, the cable line bus 29 and the first lead-in

five

0

five

0

five

0

five

0

five

Beln unit 30 n-and the input of the second receiving regenerator 4.

The output signal from the second receiving regenerator 4 is written to the second serial register 13 and then to the second parallel register 16. At the outputs of the second parallel register 16, six characters in code form are represented in parallel form, which are converted in the second converter 18 into four characters in accordance with the table . The signals from the outputs of the second converter 18 are converted into serial signals at the outputs of the first 19 and second 20 parallel-serial registers and, respectively, through the third 9 and fourth 10 transmitting regenerators arrive at the inputs of the compaction equipment 1 and 2.

The operation of the second parallel register 16 and the first 19 and second 20 parallel-serial registers is controlled by signals from the first, second and third outputs of the synchronization unit 23, respectively.

The principle of operation of the synchronization unit 23 is based on the detection of combinations of symbols 0000 and 1111, which, as follows from the table, can appear with error-free operation only at the boundaries of code groups. If there are errors, the indicated combinations of characters may appear on other bits in the code groups. However, the probability of their occurrence is proportional to the error rate in the transmission system and much less (by many orders of magnitude) the probability of their occurrence at the boundaries of code groups.

The decoder 28 performs a sequential analysis of the received digital signal and the detection of combinations 0000 and 1111. The pulses of responses from the outputs of the decoder 28 are fed to the second and third inputs of the synchronization unit 23. In imaging unit 60 and, 61, pulses of half the clock interval of the received signal are generated. From the outputs of the formers 60 and 61, the impulses of responses to the combinations 0000 and 1111 are transmitted through the element OR 62 to the clock inputs of the accumulators 63-67, which can be executed, for example, in the form of successive registers. When one of the accumulators 63-67 is filled, a narrow pulse is formed in the corresponding shaper 68-72, which phases the pulse distributor through D-flip-flops 75-80 and AND 74 through the element OR 73.

Claims (1)

The PLL used on the phase detector 81, the frequency divider 82 into two, and the master oscillator 83 is used to form the clock frequency of the original digital signal. A digital radio relay transmission system comprising a serially connected first serial register, a first parallel register and a first code converter, serially connected a first transmitting regenerator, a first input-cable unit, a cable line bus, a second input-cable unit, a first receiving regenerator and adder, serially connected second receiving regenerator, second serial register, second parallel register1, second code converter and first parallel-by sequential register, serially connected first filter and second transmitting regenerator, serially connected first frequency divider and first synchronization unit, compaction equipment, second synchronization unit, the output of which is connected to the synchronization input of the second parallel register, service signal source, the output of which is connected to the second the input of the first input-cable unit, the receiver of the service communication signals connected to the second output of the input-cable unit, the third input of which is dinene with the input of the second receiving regenerator, the second filter, the output of which is connected to the second input of the second input-cable block antenna, the output of the second transmitting regenerator connected to the third input of the second input-cable unit, the second output of which is connected to the second input of the adder, the output of the first divider frequency is connected to the synchronization input of the first parallel register, the clock output of the second receiving regenerator is connected to the clock input 0 five 0 five 0 five 0 five 0 five A second sequential register, characterized in that, in order to increase the system capacity, a series of additional compaction equipment, a third receiving regenerator, a frequency switching unit and a third serial register, a third transmitting regenerator, and a second parallel serial serial register are entered. fourth transmit regenerator, serially connected frequency modulated oscillator, third filter and duplexer, serially connected frequency converter, intermediate frequency amplifier and frequency detector, the fourth when a second regenerator, a third parallel-serial register and a decoder, and the first synchronization unit is designed as a serially connected master oscillator, a second frequency divider and a phase detector, the input of the master oscillator connected to the output of the phase detector, the second input of which is the input of the first synchronization unit, the outputs of the master oscillator and the frequency divider of the first synchronization unit are connected respectively to the clock input and the recording input of the third parallel-to-serial the register whose output is connected to the input of the first transmitting regenerator, the output of the compression equipment is connected to the input of the fourth receiving regenerator, whose information output is connected to the information input of the first serial register, the clock output of the fourth receiving regenerator is connected to the second input of the frequency switching unit, the output of which is connected to the clock the input of the first serial register and the input of the first frequency divider, the output of which is connected to the synchronization input of the first -parallel registers receiving third information output of the regenerator is connected to the serial data input of the third register, the outputs of which are connected to a second bus input of the first parallel register, the outputs of the first transducer sub code key to data inputs of the third parallel-posledovatel91 the second register, the output of the adder is connected to the input of the frequency-modulated oscillator, the first output of the duplexer is connected to the antenna, the second output of the duplexer is connected to the input of the frequency converter, the output of the frequency detector is connected to the inputs of the first and second filters, the clock output of the second receiving regenerator is connected to the input the second synchronization unit, the second and third outputs of which are connected respectively to the clock inputs and recording inputs of the first and second parallel-serial registers, the output of the second n consecutive re 78357Y the hyste is connected to the input of the decoder, the first and second outputs of which are connected respectively to the second and third inputs of the second synchronization unit, the second output of the second code converter is connected by bus with informational inputs of the second i parallel-serial register, the outputs of the third and fourth transmitting regenerators are connected respectively to the input of the compaction equipment and to the input of additional compaction equipment, the output of the first 15 parallel-serial register is connected to the input of the third transmitting regenerator. Phage. 2 Phag.z