JPH01243640A - Communication control equipment - Google Patents

Abstract

PURPOSE:To store lines different in a data transfer speed by making an internal bus to be occupied for a time corresponding to the data transfer speed of the data lines by means of setting addresses in a number corresponding to respective data transfer speed of the data lines in an address holding means. CONSTITUTION:The addresses which the address registers 8a and 8b hold and those on an address bus 9 are compared. When they coincide, the internal bus 1 and the input output port are connected. Consequently, the internal bus 1 is occupied for the time corresponding to respective data transfer speed of the data line by setting the addresses in the number corresponding to the data transfer speed of the data line in the address registers 8a and 8b. Thus, the data lines different in the data transfer speed can be stored.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a communication control device capable of accommodating data lines having different data transfer speeds.

BACKGROUND ART FIG. 2 shows a functional block diagram of a conventional communication control device. Reference numeral 11 denotes an internal bus 12m for time-divisionally transmitting data to and from an external line 15.

12b and 12a are ports through which data is input/output between the internal bus 11 and the data lines 13m, 13b, and 13o, respectively, and 14 is an interface with the external line 15.

Further, reference numeral 16 denotes an access control unit 17m, 17b, 17a which sequentially generates and circulates access control signals for each port 12m, 12b, 12a at an equal and fixed rate in synchronization with the data frame on the external line 15.
are respectively connected to the internal bus 11 according to the above access control signals.
and each port 12a.

This is a bus switching block that connects with 12b and 12c.

Next, the operation of the above conventional example will be explained.

In FIG. 2, the access control unit 16 synchronizes with the data frame on the external line 15 and connects each port 12m, 12.
When access control signals for bus switching blocks 17m and 17c are sequentially generated and circulated,
b, 17o are connected to the internal bus 11 and ports 12m, 12b, and 12b, respectively, only when input to this access control signal.
Connect 12c.

Therefore, on the internal bus 11 there are data lines 13m, 1
3b, 13o and the external line 150 are transmitted in a time-division manner, and the data lines 131, 13b, 13a are accommodated in the external line 15.

Problems to be Solved by the Invention However, in the above-mentioned conventional communication control device, the access control section 16 has problems with each of the ports 12m and 12b.

In order to allocate access to the internal bus 11 of the 12c evenly and at a fixed rate, there is a problem in that it is not possible to accommodate data lines having different data transfer speeds.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a communication control device that can accommodate data lines with different data transfer speeds.

Means for Solving the Problems In order to achieve the above object, the present invention synchronizes with the data frame of the external line and creates a time-division address pattern for each frame of the internal bus according to the data transfer rate of each data line. An address pattern generating means for generating and transmitting the address pattern to the address bus, and a plurality of address holding means each holding a number of addresses corresponding to the data transfer speed of the data line, as well as addresses held by the address holding means and the address bus. The above addresses are compared, and if they match, the internal bus and the corresponding input/output port are connected.

Effect: The present invention sets a number of addresses corresponding to the data transfer speeds of the data lines in the address holding means, so that the internal bus is occupied for a period of time corresponding to the data transfer speeds of the respective data lines. ,therefore,
Data lines with different data transfer speeds can be accommodated.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a functional block diagram showing an embodiment of a communication control device according to the present invention.

In FIG. 1, reference numeral 1 denotes an internal bus 2a for time-divisionally transmitting data to and from an external line 5.

2b are internal bus 1 and data line 3 respectively.

A port 4 through which data is input/output to/from 3b is an interface with an external line 5.

Further, 6 synchronizes with the data frame of the external line 5, and generates a time-division address pattern for each frame of the internal bus 1 according to the data transfer speed of each of the data lines 3a and 3b, and generates a circulating address pattern. Block 7 is an address bus for transmitting the address pattern from address pattern/generation block 6.

Address registers 9a hold addresses of ports 2m and 2b, the number of which corresponds to the data transmission speed of the data lines 3m and 3b, respectively.

Decode blocks 10m and 9b compare the address pattern held by the address registers 8m and 8b with the address on the address bus 7, and generate an access control signal for the internal bus 1 of the ports 2m and 2b when they match, respectively; 10b are decode blocks 9, respectively.
Due to the access control signal from m,9b, port 2m,
2b and the internal bus 1.

Next, the operation of the above embodiment will be explained.

In FIG. 1, the address pattern generation block 6 synchronizes with the data frame of the external line 5 and generates a time-division address pattern for each frame of the internal bus 1 according to the data transfer speed of each of the data lines 3m and 3b. , and when it is transmitted to the address bus 6, the decode block 9 is sent.

Ports 9b compare the addresses held in address registers 8m and 8b with the address pattern on address bus 6, and when they match, generate an access control signal for internal bus 1 of ports 2m and 2b.

Gate blocks 10m and 10b respectively connect ports 2a and 2b to internal bus 1 only when this access control signal is input, and data lines 3a and 3a are connected to internal bus 1 on internal path 1.
3b and the external line 5 are transmitted in a time-division manner.

Therefore, by setting in advance the addresses of ports 2m and 2b in the address registers 8m and 8b according to the data transmission speed of the data lines 3m and 3b, the internal bus 1
is occupied for a time corresponding to the data transmission speed of the data lines 3a and 3b, and the data lines 3m having different data transmission speeds are
, 3b can be accommodated.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention generates a frame-by-frame time-sharing address pattern of the internal bus in accordance with the data transfer rate of each of the data lines while synchronizing with data frames of an external line; An address pattern generating means for transmitting to the address bus and a plurality of address holding means each holding a number of addresses corresponding to the data transfer speed of the data line are provided, and the addresses held by this address holding means and the addresses on the address bus are provided. If they match, the internal bus and the input/output boat are connected. Therefore, by setting the number of addresses corresponding to the data transfer speed of each data line in the address holding means, , the internal bus is occupied for a period of time depending on the data rate of each of the data lines, thus being able to accommodate data lines with different data rates.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment of a communication control device according to the present invention, and FIG. 2 is a functional block diagram showing a conventional communication control device. 1...Internal bus, 2m, 2b...I/O port, 3m, 3b...data line, 4...
...External line interface, 5...External line, 6...Address pattern generation block,
7...Address bus, 8a. 8b...address register, 9m, 9b...
...Decode block, 10m, 10b...
Gate block. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure

Claims (1)

[Claims] an internal bus for transmitting data to and from external lines;
A plurality of input/output ports through which data is input/output to and from each data line, and a time frame unit of the internal bus that is synchronized with the data frame of the external line and that corresponds to the data transfer rate of each of the data lines. address pattern generating means for generating a divided address pattern and transmitting it to the address bus; a plurality of address holding means each having a number of addresses corresponding to the data transfer speed of the data line; and address holding means held by the address holding means. A communication control device comprising means for comparing an address with an address on the address bus and connecting the internal bus and the input/output port when they match.