JPH01243101A - Digital controller - Google Patents

Digital controller

Info

Publication number
JPH01243101A
JPH01243101A JP6960688A JP6960688A JPH01243101A JP H01243101 A JPH01243101 A JP H01243101A JP 6960688 A JP6960688 A JP 6960688A JP 6960688 A JP6960688 A JP 6960688A JP H01243101 A JPH01243101 A JP H01243101A
Authority
JP
Japan
Prior art keywords
gain
deviation
value
absolute value
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6960688A
Other languages
Japanese (ja)
Inventor
Teruyoshi Shimizu
清水 照喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6960688A priority Critical patent/JPH01243101A/en
Publication of JPH01243101A publication Critical patent/JPH01243101A/en
Pending legal-status Critical Current

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  • Feedback Control In General (AREA)

Abstract

PURPOSE:To obtain a control system to quickly respond and not to overshoot by linearly changing the gain of the control system according to the quantity of a deviation. CONSTITUTION:When a set gain is made into G and a deviation signal is made into epsilon, for the gain of a digital controller equipped with an absolute value converter 8 and a gain arithmetic device 9, the deviation signal is made into ¦epsilon¦by the absolute value converter 8, the gain computing element 9 function- converts the output value of the absolute value converter 8 to 1+DELTA, and GX(1+DELTA) is obtained with the set gain G. By the arithmetic gain of the gain computing element 9, when the deviation is large, the gain is made high, and a response is made quick, and as the deviation is made small, the gain is made low, and the response is slow. Thus, the system can be obtained which responds quickly and does not overshoot.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、フィードバック制御系を有するデジタル制御
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital control device having a feedback control system.

(従来の技術) 従来のフィードバック制御系を有する制御装置の一例を
して第V図を用いて説明する。この従来例では、制御対
象1に接続された検出器2にて制御対象1の実際値を検
出する。基準回路3は制御対象1の制御目標値である基
準値を出力する。偏差検出器4は基準回路3の基準値と
、検出器2の検出値とをある一定期間毎に読み込み、基
準値と対象1を制御するのに適した系を比例演算、積分
演算、微分演算等にて構成し、ゲイン設定器5の出力を
掛けたものを出力する。エネルギー制御変換器7は、制
御系6の出力信号により制御されたエネルギーを制御対
象1に与えるものである。
(Prior Art) An example of a control device having a conventional feedback control system will be described with reference to FIG. In this conventional example, a detector 2 connected to the controlled object 1 detects the actual value of the controlled object 1. The reference circuit 3 outputs a reference value that is a control target value of the controlled object 1. The deviation detector 4 reads the reference value of the reference circuit 3 and the detected value of the detector 2 at regular intervals, and calculates a system suitable for controlling the reference value and the object 1 by proportional calculation, integral calculation, and differential calculation. etc., and outputs the product multiplied by the output of the gain setter 5. The energy control converter 7 provides energy controlled by the output signal of the control system 6 to the controlled object 1.

(発明が解決しようとする課題) しかし、上記従来の制御装置においては、サンプリング
制御の場合、応答時間とサンプリング回数の関係により
、ゲインを高くして応答時間を短くしようとすると、応
答時間内に基準値及び検出値をサンプリングできる回数
が少なくなり、ステップ応答波形が、第3図(a)に示
すようにオーバ−シュートする波形となる。また、オー
バーシュートを除去するには、第3図(b)に示すよう
に、ゲインを低げて応答時間の長い波形としなければな
らない。
(Problem to be Solved by the Invention) However, in the conventional control device described above, in the case of sampling control, when trying to shorten the response time by increasing the gain, due to the relationship between the response time and the number of samplings, The number of times the reference value and the detected value can be sampled decreases, and the step response waveform becomes an overshoot waveform as shown in FIG. 3(a). Furthermore, in order to eliminate overshoot, the gain must be lowered to create a waveform with a longer response time, as shown in FIG. 3(b).

そこで1本発明は、上記問題点を鑑み、応答時間を短く
してもオーバーシュートが発生しない制御装置を提供す
ることを目的とする。
SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a control device that does not cause overshoot even if the response time is shortened.

〔発明の構成〕[Structure of the invention]

(711題を解決するための手段) したがって、上記目的を達成するために、本発明は、制
御対象の制御目標値である基準値を設定する基準設定手
段と、制御対象の実際値を検出する検出手段と、基準値
と実際値との偏差を算出する偏差算出手段と、偏差を基
に任意の係数を設定する係数設定手段と、偏差を絶対値
変換する変換手段と、この変換手段からの出力値を関数
変換し、この関数変換した値に、係数設定手段からの係
数を乗算する係数設定手段と、前記偏差を絶対値変換す
る変換手段とを備えたデジタル制御装置を提供する。
(Means for Solving Problem 711) Therefore, in order to achieve the above object, the present invention provides a reference setting means for setting a reference value that is a control target value of a controlled object, and a method for detecting an actual value of the controlled object. a detection means, a deviation calculation means for calculating the deviation between a reference value and an actual value, a coefficient setting means for setting an arbitrary coefficient based on the deviation, a conversion means for converting the deviation into an absolute value, and a conversion means for converting the deviation into an absolute value; A digital control device is provided that includes a coefficient setting means for performing a function conversion on an output value and multiplying the function-converted value by a coefficient from a coefficient setting means, and a conversion means for converting the deviation into an absolute value.

(作 用) 上記のように構成されたデジタル制御装置においては、
基準値と検出手段の出力値との差が大きいとき、すなわ
ち偏差算出手段の出力値が大のときは、ゲインが大きく
なり、応答が早くなる。また、制御対象の実際値が目標
値に近づき、基準値と検出手段の出力値との差が小さく
なってくると、だんだんゲインが小さくなって応答が遅
くなる。
(Function) In the digital control device configured as above,
When the difference between the reference value and the output value of the detection means is large, that is, when the output value of the deviation calculation means is large, the gain becomes large and the response becomes fast. Further, as the actual value of the controlled object approaches the target value and the difference between the reference value and the output value of the detection means becomes smaller, the gain gradually becomes smaller and the response becomes slower.

このように、偏差算出手段の出力値、すなわち基準検出
値の偏差の量に応じて、ゲインが直線的に変化し、偏差
が犬のときは、ゲインが高くなって早く目標値に近づく
ように動作し、目標値に近づいてくるとゲインが低くな
ってオーバーシュートしないように動作する。
In this way, the gain changes linearly according to the output value of the deviation calculation means, that is, the amount of deviation from the reference detected value, and when the deviation is large, the gain increases and approaches the target value quickly. When the gain approaches the target value, the gain is lowered to prevent overshoot.

(実施例) 以下、本発明の一実施例を図面に基づいて説明の制御装
置と同一の構成部分については、同一符号を付すことに
より、その説明を省略する。
(Embodiment) Hereinafter, the same components as those of the control device in which an embodiment of the present invention will be described based on the drawings will be denoted by the same reference numerals, and the explanation thereof will be omitted.

第1図に示すように、絶対値変換器8は、偏差検出器4
の出力値を絶対値変換する。ゲイン演算器9は、絶対値
変換器8の出力を関数変換し、関数変換した値と、ゲイ
ン設定器5の出力値とを乗算し、さらに、その結果を偏
差検出器4の出力に乗算する。これら絶対値変換器8、
ゲイン演算器9を備えたデジタル制御装置のゲインは、
設定ゲインをG偏差信号をεとすると、偏差信号は、絶
対値変換器8にて1ε1となる。ゲイン演算器9は、絶
対値変換器8の出力値h」を1+Δに関数変換し、設定
ゲインGとより、GX (1+Δ)を求める。基準値、
検出値、偏差、制御ゲインの関係を第5図に示す。ゲイ
ン演算器9の演算ゲインにより、偏差が大きい時はゲイ
ンが高くなって、応答が早くなり、偏差が小さくなるに
したがってゲインが低くなって応答が遅くなり、第3図
(c)に示すように応答が早くてオーバーシュートしな
い系とすることができる。
As shown in FIG. 1, the absolute value converter 8 is connected to the deviation detector 4.
Convert the output value of to absolute value. The gain calculator 9 performs a function conversion on the output of the absolute value converter 8, multiplies the function-converted value by the output value of the gain setter 5, and further multiplies the result by the output of the deviation detector 4. . These absolute value converters 8,
The gain of the digital control device equipped with the gain calculator 9 is:
Assuming that the set gain is ε for the G deviation signal, the deviation signal at the absolute value converter 8 becomes 1ε1. The gain calculator 9 converts the output value "h" of the absolute value converter 8 into 1+Δ, and calculates GX (1+Δ) from the set gain G. Reference value,
FIG. 5 shows the relationship among the detected value, deviation, and control gain. Due to the calculation gain of the gain calculator 9, when the deviation is large, the gain becomes high and the response becomes fast, and as the deviation becomes small, the gain becomes low and the response becomes slow, as shown in Fig. 3(c). It is possible to create a system that has a quick response and does not overshoot.

〔発明の効果〕〔Effect of the invention〕

以」二述べたように、本発明によれば、偏差の量に応じ
て制御系のゲインを直線的に変化させる。
As described above, according to the present invention, the gain of the control system is changed linearly according to the amount of deviation.

=4− このことにより、偏差の大きい時は、ゲインが高く、偏
差が小さくなってくるとゲインが低くなり、応答が早く
てオーバーシュー1〜しない制御系を実現できる。
=4- As a result, when the deviation is large, the gain is high, and as the deviation becomes small, the gain is low, so that a control system with quick response and no overshoot can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示す回路構成図、第2図
は、第1図に示したデジタル制御装置の各信号を示す波
形図、第3図(a)は、従来の制御装置におけるゲイン
の高い場合のステップ応答を示す波形図、第3図(b)
は、従来の制御装置におけるゲインの低い場合のステッ
プ応答を示す波形図、第3図(C)は、第1図に示した
デジタル制御装置におけるステップ応答を示す波形図、
第4図は、従来の制御装置を示す回路構成図である。 1・・制御対象     2・・・検出器3・・基準回
路     4・・・偏差検出器5・・ゲイン設定器 
  8・・・絶対値変換器9・・・ゲイン演算器 代理人 弁理士 則 近 憲 佑 同    第子丸   健 第2図 第3図
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing each signal of the digital control device shown in FIG. 1, and FIG. 3(a) is a conventional control diagram. Waveform diagram showing the step response when the gain in the device is high, Figure 3(b)
is a waveform diagram showing the step response when the gain is low in the conventional control device, and FIG. 3(C) is a waveform diagram showing the step response in the digital control device shown in FIG.
FIG. 4 is a circuit configuration diagram showing a conventional control device. 1... Controlled object 2... Detector 3... Reference circuit 4... Deviation detector 5... Gain setting device
8...Absolute value converter 9...Gain calculator agent Patent attorney Rule Ken Chika Yudo Ken Daishimaru Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims]  制御対象の制御目標値である基準値を設定する基準設
定手段と、前記制御対象の実際値を検出する検出手段と
、前記基準値と前記実際値との偏差を算出する偏差算出
手段と、前記偏差を基に任意の係数を設定する係数設定
手段と、前記偏差を絶対値変換する変換手段と、この変
換手段からの出力値を関数変換し、この関数変換した値
に前記係数を乗算する係数演算手段とを具備したことを
特徴とするデジタル制御装置。
a reference setting means for setting a reference value that is a control target value of a controlled object; a detection means for detecting an actual value of the controlled object; a deviation calculating means for calculating a deviation between the reference value and the actual value; a coefficient setting means for setting an arbitrary coefficient based on the deviation; a conversion means for converting the deviation into an absolute value; and a coefficient for converting the output value from the conversion means into a function and multiplying the value converted by the function by the coefficient. A digital control device characterized by comprising a calculation means.
JP6960688A 1988-03-25 1988-03-25 Digital controller Pending JPH01243101A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6960688A JPH01243101A (en) 1988-03-25 1988-03-25 Digital controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6960688A JPH01243101A (en) 1988-03-25 1988-03-25 Digital controller

Publications (1)

Publication Number Publication Date
JPH01243101A true JPH01243101A (en) 1989-09-27

Family

ID=13407673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6960688A Pending JPH01243101A (en) 1988-03-25 1988-03-25 Digital controller

Country Status (1)

Country Link
JP (1) JPH01243101A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017110645A (en) * 2015-12-16 2017-06-22 ゼネラル・エレクトリック・カンパニイ Machine-specific combined probabilistic control in gas turbine tuning for power output-emissions parameters with scaling factor, and related control systems, computer program products and methods

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5580119A (en) * 1978-12-13 1980-06-17 Nippon Sanso Kk Temperature control method
JPS60176104A (en) * 1984-02-23 1985-09-10 Mitsubishi Heavy Ind Ltd Process controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5580119A (en) * 1978-12-13 1980-06-17 Nippon Sanso Kk Temperature control method
JPS60176104A (en) * 1984-02-23 1985-09-10 Mitsubishi Heavy Ind Ltd Process controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017110645A (en) * 2015-12-16 2017-06-22 ゼネラル・エレクトリック・カンパニイ Machine-specific combined probabilistic control in gas turbine tuning for power output-emissions parameters with scaling factor, and related control systems, computer program products and methods

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