JPH01242768A - Mask vapor deposition method - Google Patents
Mask vapor deposition methodInfo
- Publication number
- JPH01242768A JPH01242768A JP7031488A JP7031488A JPH01242768A JP H01242768 A JPH01242768 A JP H01242768A JP 7031488 A JP7031488 A JP 7031488A JP 7031488 A JP7031488 A JP 7031488A JP H01242768 A JPH01242768 A JP H01242768A
- Authority
- JP
- Japan
- Prior art keywords
- vapor deposition
- metal mask
- mask
- magnet
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007740 vapor deposition Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract 2
- 238000001704 evaporation Methods 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 11
- 238000007738 vacuum evaporation Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- BYFGZMCJNACEKR-UHFFFAOYSA-N Al2O Inorganic materials [Al]O[Al] BYFGZMCJNACEKR-UHFFFAOYSA-N 0.000 description 1
- 241000885593 Geisha Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000004753 textile Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
真空蒸着に使用するメタルマスクに関し、メタルマスク
の撓みによる蒸着粒子の回り込みを無くすることを目的
とし、
メタルマスクを磁性金属板を用いて形成し、被処理基板
の背後に板状の磁石を置き、この磁石によりメタルマス
クを磁気吸引させた状態で真空蒸着を行い、マスク蒸着
方法を構成する。[Detailed Description of the Invention] [Summary] With respect to a metal mask used for vacuum evaporation, the purpose of this invention is to eliminate the wraparound of evaporation particles due to the bending of the metal mask. A plate-shaped magnet is placed behind the substrate, and vacuum evaporation is performed while the metal mask is magnetically attracted by the magnet, forming a mask evaporation method.
本発明は微細パターンの形成に使用するマスク蒸着方法
に関する。The present invention relates to a mask deposition method used for forming fine patterns.
大量の情報を迅速に処理する必要性から情報処理装置は
高密度実装が行われており、使用部品の小形化が推進さ
れている。BACKGROUND OF THE INVENTION Due to the need to quickly process large amounts of information, information processing devices are being packaged with high density, and components used are becoming smaller.
こ＼で、導体線路や電極などの微細パターンの形成法と
してはマスク蒸着法と写真蝕刻技術（フォトリソグラフ
ィ）とがある。There are two methods for forming fine patterns such as conductor lines and electrodes: mask vapor deposition and photolithography.
すなわち、前者は真空蒸着或いはスパッタによる薄膜形
成に際し、被処理基板の上に予めパターンの六開けが行
われているマスクを密着することにより薄膜パターンの
形成を行うものである。That is, in the former method, when forming a thin film by vacuum evaporation or sputtering, a thin film pattern is formed by closely contacting a mask in which a pattern has been cut in advance on a substrate to be processed.
また、後者は被処理基板の上に真空蒸着やスパッタなど
の物理的方法或いは化学気相成長法（ＣｈｅｌＩｌｉｃ
ａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ略称ＣＶＤ）
などの方法で薄膜を作り、感光性レジストを被覆した後
、マスクを通して紫外線を照射して後に現像し、レジス
トパターンを作り、湿式エツチング或いは乾式エツチン
グを行って蒸着薄膜を選択エツチングして微細な薄膜パ
ターンを形成するものである。The latter method is performed using physical methods such as vacuum evaporation or sputtering, or chemical vapor deposition method (Chemical vapor deposition method) on the substrate to be processed.
al Vapor Deposition (abbreviation CVD)
After making a thin film using a method such as the above, and covering it with a photosensitive resist, it is irradiated with ultraviolet rays through a mask and then developed to create a resist pattern, and the deposited thin film is selectively etched by wet etching or dry etching to form a fine thin film. It forms a pattern.
こ−で、前者のマスク蒸着法は後者に較べるとパターン
精度において遜色があるもの＼、筒便であり、また厚い
パターンも形成できることから広く使用されている。Therefore, the former mask vapor deposition method is inferior to the latter in terms of pattern accuracy, is more convenient, and is widely used because it can form thick patterns.
マスク蒸着によるパターン形成は電子部品に限らず装飾
や織物の部門などあらゆる用途に互って行われているが
、こ＼ではフリップチップタイプの半導体ＩＣ（略して
フリップチップＩＣ）を例として説明する。Pattern formation by mask vapor deposition is used not only for electronic components but also for various applications such as decoration and textiles, but here we will explain it using a flip-chip type semiconductor IC (abbreviated as flip-chip IC) as an example. .
フリップチップＩＣは半導体ＩＣの集積回路形成面の上
に、マトリックス状に、或いはチップの周辺に沿って半
田からなる電極端子（半田バンプ）を設けたものである
。A flip chip IC is a semiconductor IC in which electrode terminals (solder bumps) made of solder are provided in a matrix or along the periphery of the chip on the integrated circuit forming surface of the semiconductor IC.
そして、これを予めアルミナ（α−Ａｌ２Ｏいなどから
なる耐熱性の多層基板の上に形成されている電極パッド
に位置合わせ、基板加熱を行ちて半田を融着させ回路接
続を行うことにより装着が行われている。This is then aligned in advance with the electrode pads formed on a heat-resistant multilayer board made of alumina (α-Al2O, etc.), and the board is heated to fuse the solder and connect the circuit. is being carried out.
こ＼で、半田バンプの形成にはマスク蒸着法が使用され
ており、半田を５０〜６０μｍの厚さに形成している。Here, a mask vapor deposition method is used to form the solder bumps, and the solder is formed to a thickness of 50 to 60 μm.
すなわち、集積回路の形成の終わった半導体基板（ウェ
ハ）の上に半田バンプ形成位置を除いて二酸化硅素（Ｓ
ｉｎｇ）、酸窒化硅素（ＳｉＯＮ）、窒化硅素（ＳｔＪ
４）などの耐湿保ｒＦＬ層を形成した後、メタルマスク
を密着させて蒸着源の上に置き、半田蒸着を行って半田
バンプを形成している。In other words, silicon dioxide (S
ing), silicon oxynitride (SiON), silicon nitride (StJ
After forming a moisture-resistant rFL layer such as 4), a metal mask is placed in close contact with the vapor deposition source, and solder vapor deposition is performed to form solder bumps.
こ＼で、メタルマスクとしては厚さが１００〜２００
μｍでモリブデン（Ｍｏ）、コバール（Ｎｉ−Ｃｏ−Ｆ
ｅ合金）、４２７０イ（４２％Ｎｉ−Ｆｅ合金）などが
使用されている。This is a metal mask with a thickness of 100 to 200 mm.
Molybdenum (Mo), Kovar (Ni-Co-F) in μm
e alloy), 4270i (42% Ni-Fe alloy), etc. are used.
然し、半田バンプの高さが数１０μｍの厚さになるまで
真空蒸着を行うと、加熱によってメタルマスク自体が膨
張すること＼、メタルマスクの重量の増加とによって下
方に向いてのメタルマスクの撓みが生じる。However, if vacuum deposition is performed until the height of the solder bumps reaches a thickness of several tens of micrometers, the metal mask itself expands due to heating, and the metal mask bends downward due to the increase in weight of the metal mask. occurs.
第３図はこの状態を示す断面図であって、半導体ウェハ
１の下面に基板ホルダ２により固定されているメタルマ
スク３は、中央に近づくに従って半導体ウェハ１との隙
間が増大してくる。FIG. 3 is a sectional view showing this state, and the gap between the metal mask 3, which is fixed to the lower surface of the semiconductor wafer 1 by the substrate holder 2, and the semiconductor wafer 1 increases as it approaches the center.
その結果、メタルマスク３を通っての蒸発粒子の廻り込
みが増加してパターン精度の低下が生じ、隣接パターン
の距離が短い場合には絶縁不良や短絡などの障害が起こ
る。As a result, the circulation of evaporated particles through the metal mask 3 increases, resulting in a decrease in pattern accuracy, and when the distance between adjacent patterns is short, problems such as poor insulation and short circuits occur.
第４図は半導体チップ４の上に形成された半田バンプ５
とメタルマスク３との関係を示すもので、半田バンプ５
は半導体チップ４の導体線路の先端に設けられているパ
ッド６の上にのみ形成されなければならないが、メタル
マスク３の裏側まで廻り込む結果として短絡が生じた状
態を示している。FIG. 4 shows solder bumps 5 formed on a semiconductor chip 4.
This shows the relationship between the solder bump 5 and the metal mask 3.
should be formed only on the pad 6 provided at the tip of the conductor line of the semiconductor chip 4, but it shows a state in which a short circuit has occurred as a result of it going around to the back side of the metal mask 3.
以上記したようにメタルマスクを用いて数１０μｍの膜
厚の蒸着を行うと、自重の増加とメタルマスクの熱膨張
によって撓みを生じ、これにより蒸着パターンの精度が
低下することが問題である。As described above, when a metal mask is used to deposit a film with a thickness of several tens of micrometers, there is a problem that the metal mask becomes warped due to an increase in its own weight and thermal expansion of the metal mask, which reduces the accuracy of the deposition pattern.
上記の課題はメタルマスクを磁性金属板を用いて形成し
、被処理基板の背後に板状の磁石を置き、この磁石によ
りメタルマスクを磁気吸引させた状態で真空蒸着を行う
方法をとることにより解決することができる。The above problem can be solved by forming the metal mask using a magnetic metal plate, placing a plate-shaped magnet behind the substrate to be processed, and performing vacuum evaporation while the metal mask is magnetically attracted by this magnet. It can be solved.
本発明はメタルマスクが熱膨張と自重の増加により撓む
のを防止する方法としてメタルマスクを磁性金属を用い
て形成すると共に、蒸着によりパターンを形成する被処
理基板の背後に永久磁石を備え、常にメタルマスクを磁
気吸引する構成をとるものである。The present invention is a method for preventing a metal mask from being bent due to thermal expansion and an increase in its own weight, in which a metal mask is formed using a magnetic metal, and a permanent magnet is provided behind a substrate to be processed on which a pattern is formed by vapor deposition. The structure is such that the metal mask is always magnetically attracted.
このようにすると、熱膨張や自重増によっても被処理Ｗ
板との密着は変わらず、これにより高いパターン精度を
維持することができる。In this way, the W to be processed can be
The close contact with the plate remains unchanged, which allows high pattern accuracy to be maintained.
第１図は本発明の実施に使用したメタルマスクと４５１
石との配置奇示す一実施例の断面図である。Figure 1 shows the metal mask and 451 used to implement the present invention.
It is a cross-sectional view of an example showing an odd arrangement with stones.
すなわち、非磁性金属である銅（Ｃｕ）を用いて磁石７
のホルダ８を作り、４２７０イからなるメタルマスク９
をシリコン（ＳＲ） ウェハ１０に密着させて磁石７に
吸引させた。That is, the magnet 7 is made of copper (Cu), which is a non-magnetic metal.
Make a holder 8 and make a metal mask 9 consisting of 4270 pieces.
was brought into close contact with a silicon (SR) wafer 10 and attracted by the magnet 7.
具体的には、磁石７としては直径が１００ ｍ＋ｎで厚
さが１５１１ｍのフェライト磁石を用い、Ｓｔウェハ１
０としては径３インチ（７６，２＋ｕ）、厚さが５００
１１ｍのものを用い、またメタルマスクは厚さが１００
μｍのものを使用した。Specifically, a ferrite magnet with a diameter of 100 m+n and a thickness of 1511 m was used as the magnet 7, and the St wafer 1
0 has a diameter of 3 inches (76,2+u) and a thickness of 500 mm.
A metal mask with a thickness of 11m was used, and the thickness of the metal mask was 100m.
μm ones were used.
そして、真空蒸着機にセ・ツトし、蒸着源としてはイン
ジウム（Ｉｎ）を坩堝に入れ、これを抵抗加熱法により
加熱溶融して真空蒸着させた。Then, it was set in a vacuum evaporation machine, and indium (In) was put into the crucible as a evaporation source, and this was heated and melted by a resistance heating method to perform vacuum evaporation.
第２図はこのようにしてＳｔチップ１１の上に６０μｍ
の厚さに形成した半田バンプ１２の断面図であって、０
．１ μｍの厚さに予め形成しであるバッド６の」−に
精度よくパターン形成することができた。FIG. 2 shows that a 60 μm thick
2 is a cross-sectional view of a solder bump 12 formed to a thickness of 0.
．． It was possible to accurately form a pattern on the pad 6, which had been previously formed to a thickness of 1 μm.
本発明の実施により、半導体チップのバンプ形成のよう
に蒸２膜からなる厚いパターンを形成する場合でもマス
クの撓みを無くすることができ、これにより製造歩留ま
りの向上による価格低減が可能となる。By implementing the present invention, even when forming a thick pattern made of two vaporized films, such as when forming bumps on a semiconductor chip, it is possible to eliminate mask deflection, thereby making it possible to reduce costs by improving manufacturing yield.
第１図はメタルマスクと磁石との配置を示す断面図、
第２図はＳｉチップ上に形成した半田バンプの断面図、
第３図は芸者中のメタルマスクの撓み発生を示す断面図
、
第４図は短絡の発生状態を示す断面図、である。
図において、
■は半導体ウェハ、 ３，９はメタルマスク、４
は半導体チップ、 ５，１２は半田バンプ、６は
バッド、 ７は磁石、８はホルダ、
１０はＳｉウェハ、１１はＳｉデツプ、
である。Fig. 1 is a cross-sectional view showing the arrangement of the metal mask and magnet, Fig. 2 is a cross-sectional view of solder bumps formed on a Si chip, Fig. 3 is a cross-sectional view showing the occurrence of deflection of the metal mask during a geisha, FIG. 4 is a sectional view showing a state in which a short circuit occurs. In the figure, ■ is a semiconductor wafer, 3 and 9 are metal masks, and 4 is a semiconductor wafer.
is a semiconductor chip, 5 and 12 are solder bumps, 6 is a pad, 7 is a magnet, 8 is a holder,
10 is a Si wafer, and 11 is a Si deep.
Claims (1)
して蒸着源中の材料を真空蒸発せしめ、前記被処理基板
上に選択的に蒸着パターンの形成を行うメタルマスクが
磁性金属板を用いて形成されており、前記被処理基板の
背後に板状の磁石を置き、該磁石により前記メタルマス
クを磁気吸引させた状態で真空蒸着を行うことを特徴と
するマスク蒸着方法。A metal mask is a magnetic metal mask that is placed on an evaporation source in contact with a substrate to be processed, heats the evaporation source to vacuum evaporate the material in the evaporation source, and selectively forms an evaporation pattern on the substrate to be processed. A mask vapor deposition method, characterized in that a plate-shaped magnet is placed behind the substrate to be processed, and vacuum vapor deposition is performed in a state where the metal mask is magnetically attracted by the magnet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7031488A JPH01242768A (en) | 1988-03-24 | 1988-03-24 | Mask vapor deposition method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7031488A JPH01242768A (en) | 1988-03-24 | 1988-03-24 | Mask vapor deposition method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01242768A true JPH01242768A (en) | 1989-09-27 |
Family
ID=13427869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7031488A Pending JPH01242768A (en) | 1988-03-24 | 1988-03-24 | Mask vapor deposition method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01242768A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0413858A (en) * | 1990-05-08 | 1992-01-17 | Mitsumura Insatsu Kk | Masking device |
| FR2855530A3 (en) * | 2003-05-28 | 2004-12-03 | Tecmachine | Masking by stencil for vacuum deposition during micro-battery manufacture, treats substrate to cause mask attraction, flattening it into perfect contact |
| US11024488B2 (en) * | 2017-03-08 | 2021-06-01 | The Japan Steel Works, Ltd. | Film-forming method, manufacturing method of electronic device, and plasma atomic layer deposition apparatus |
-
1988
- 1988-03-24 JP JP7031488A patent/JPH01242768A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0413858A (en) * | 1990-05-08 | 1992-01-17 | Mitsumura Insatsu Kk | Masking device |
| FR2855530A3 (en) * | 2003-05-28 | 2004-12-03 | Tecmachine | Masking by stencil for vacuum deposition during micro-battery manufacture, treats substrate to cause mask attraction, flattening it into perfect contact |
| US11024488B2 (en) * | 2017-03-08 | 2021-06-01 | The Japan Steel Works, Ltd. | Film-forming method, manufacturing method of electronic device, and plasma atomic layer deposition apparatus |
| US12009183B2 (en) | 2017-03-08 | 2024-06-11 | The Japan Steel Works, Ltd. | Film-forming method, manufacturing method of electronic device, and plasma atomic layer deposition apparatus |
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