JPH01239973A - Semiconductor photodetector - Google Patents
Semiconductor photodetectorInfo
- Publication number
- JPH01239973A JPH01239973A JP63068959A JP6895988A JPH01239973A JP H01239973 A JPH01239973 A JP H01239973A JP 63068959 A JP63068959 A JP 63068959A JP 6895988 A JP6895988 A JP 6895988A JP H01239973 A JPH01239973 A JP H01239973A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- mesa
- substrate
- matched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012212 insulator Substances 0.000 claims abstract description 3
- 230000031700 light absorption Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 150000002222 fluorine compounds Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910001632 barium fluoride Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- AHLBNYSZXLDEJQ-FWEHEUNISA-N orlistat Chemical compound CCCCCCCCCCC[C@H](OC(=O)[C@H](CC(C)C)NC=O)C[C@@H]1OC(=O)[C@H]1CCCCCC AHLBNYSZXLDEJQ-FWEHEUNISA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910001637 strontium fluoride Inorganic materials 0.000 description 1
- FVRNDBHWWSPNOM-UHFFFAOYSA-L strontium fluoride Chemical compound [F-].[F-].[Sr+2] FVRNDBHWWSPNOM-UHFFFAOYSA-L 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は高速大容量の光通信システム等で用いて好適な
半導体受光素子に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor light-receiving element suitable for use in high-speed, large-capacity optical communication systems and the like.
（従来の技術）
高速・大容量光通信システムを可能にするには、２０Ｇ
ｂ ／ Ｓ程度の超高速で応答する半導体受光素子が
必要であり、近年、シリカファイバの低損失波長域１〜
１．６ｕＩｎに適応できるＩ ｎＧａＡｓ／ＩｎＰ系ｐ
ｉｎ型フォ）・タイオードの高速化か活発となっている
。ウェイタ（Ｄ、Ｗａｋｅ）等は、エレクトロニクス・
レター（Ｅｌｅｃｔｒｏｎ。(Conventional technology) To enable high-speed, large-capacity optical communication systems, 20G
Semiconductor photodetectors that respond at ultra-high speeds of b/s are required, and in recent years, silica fibers have been developed in the low-loss wavelength range 1 to 1.
InGaAs/InP system p applicable to 1.6uIn
In-type diodes are becoming increasingly faster. Waiter (D, Wake) etc. are electronics/
Letter (Electron.
Ｌｅｔｔ、）第２３巻、４１５〜４１６ページ（１９８
７年）において、１〜１．６ｇｍ帯、ＩｎＧａＡｓ／Ｉ
ｎＰ系高速ｐｉｎ型フォトダイオードを発表している。Lett,) Volume 23, pages 415-416 (198
7 years), 1-1.6 gm band, InGaAs/I
We have announced an nP-based high-speed pin type photodiode.
その典型的構造を第２図に示す。半絶縁性ＩｎＰ基板１
の上にｎ＋導伝型ＩｎＰバッファ層２、ｎ−型１ ｎｏ
、５３Ｇａｏ、ａ７Ａｓ光吸１［ｉ、層３、ｐ十導伝型
キャップ層４を順次に成長した陸、受光部５をメサ状に
形成し、ｎ側電極６及びエアブリッジ型Ｐ ！ｌＦＩ電
１ｆＩ ７を設けている。この４Ｍ ｍでは、受光部の
メサ径を〜３０１ＪＩｎΦに縮少することで接合容量Ｃ
ｊを削除し、また、半絶縁性基板とエアブリ・ソジ配線
を用いることで配線容量Ｃを削除し、ＣＲ時定数制限を
改善している。Its typical structure is shown in FIG. Semi-insulating InP substrate 1
n+ conductivity type InP buffer layer 2, n- type 1 no
, 53Gao, a7As light absorption 1[i, layer 3, p10 conduction type cap layer 4 is sequentially grown, light receiving part 5 is formed in a mesa shape, n side electrode 6 and air bridge type P! 1FI 7 is provided. With this 4Mm, the junction capacitance C can be reduced by reducing the mesa diameter of the light receiving part to ~301JInΦ.
By eliminating j and using a semi-insulating substrate and air-bridging wiring, the wiring capacitance C is eliminated and the CR time constant limit is improved.
（発明か解決しようとする課題）
しかし、前述の従来のｐｉｎ型フォトダイオードではメ
サ形成による表面リークｔ＝、暗電流の増加、エアブリ
ッジ配線による不安定性増加、（、ａ ｌｌｉ性低下か
問題となる。(Problem to be solved by the invention) However, in the conventional pin-type photodiode described above, there are problems such as surface leakage t= due to mesa formation, increase in dark current, increase in instability due to air bridge wiring, (, decrease in alli property, etc.) Become.
本発明は、上述の欠点を解決し、高速に応答ししから信
頼性に代れた半導体受光素子を実現することを目的とす
る。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to realize a semiconductor light-receiving element that responds at high speed and has improved reliability.
（課題を解決するだめの手段）
本発明の、半導体受光素子は、受光領域の周囲か、半導
体基板と格子整合する誘電体絶縁物層によって埋込まれ
ていることを特徴とする。(Means for Solving the Problems) The semiconductor light-receiving element of the present invention is characterized in that the light-receiving region is surrounded by a dielectric insulator layer that is lattice-matched to the semiconductor substrate.
（作用）
本発明は、上述の手段により従来の欠点を克服した。第
２図は後に詳しく説明する本発明の半導体受光素子の一
実施例を示す断面図である。図において、■はｎ４型半
導体基板、２はｎ型バッファー層、３は光吸収層、４は
ｐ十型キャップ層、５は半導体基板と格子整合する誘電
体絶縁物理込み層、６は無反射コーテイング膜、７はｐ
側電極、８はｎ側室（５，９はリング電極（ｐ側室優の
一部分）である。受光領域はメザ状に基板までエンチン
グされており、この受光領域の直径を微小化することで
接合容量を削減している。５の部分が本発明の特徴であ
り、半導体基板と格子整合する誘電体絶縁物理込み層で
ある。この誘電体層は格子整合しているのでメサ側面と
の界面にも界面準位は発生ぜず、このなめ界面リーク電
流による暗電流は極めて小さい。また誘電体層の厚さは
メサの高さ程度と厚いので、十分な耐圧があり、またＭ
ＩＳ配線容量は無視しうる程度となり、かつ、プレーナ
埋込みであるから、電極のパターニングが容易で、段差
部で生じやすい配線切れも生じない。(Operation) The present invention overcomes the conventional drawbacks by the above-mentioned means. FIG. 2 is a sectional view showing an embodiment of the semiconductor light receiving element of the present invention, which will be explained in detail later. In the figure, ■ is an n4-type semiconductor substrate, 2 is an n-type buffer layer, 3 is a light absorption layer, 4 is a p-type cap layer, 5 is a dielectric insulating physical layer that is lattice matched to the semiconductor substrate, and 6 is a non-reflective layer. Coating film, 7 is p
side electrode, 8 is the n-side chamber (5 and 9 are ring electrodes (part of the p-side chamber) Part 5 is a feature of the present invention, and is a dielectric insulating physical layer that is lattice-matched to the semiconductor substrate.Since this dielectric layer is lattice-matched, the interface with the mesa side surface is also reduced. No interface states are generated, and the dark current caused by this smooth interface leakage current is extremely small.Also, the dielectric layer is as thick as the mesa height, so it has sufficient withstand voltage, and M
IS wiring capacitance is negligible, and since it is planar embedded, patterning of electrodes is easy, and wire breaks that tend to occur at stepped portions do not occur.
（実施例）
第１図は前述のとおり本発明の一実施例を示す断面図で
ある。この実施例はＩｎＧａＡｓ／１ｎＰｐｉｎフオト
ダイオードであるか、本発明は曲の半導体系例えばＡ
４ Ｇ ａ Ａ ｓ ／ Ｇ ａ Ａ ｓ系、Ｉ ｎＧ
ａＡｓ系／ＡｕＩｎＡｓ系等にも全く同じ様に適用でき
る。(Embodiment) As described above, FIG. 1 is a sectional view showing an embodiment of the present invention. This embodiment may be an InGaAs/1nP pin photodiode, or the present invention may be applied to a semiconductor system such as an InGaAs/1nP pin photodiode.
4 G a As / G a As system, InG
It can be applied in exactly the same way to aAs-based/AuInAs-based, etc.
第１図に示ず半導１水受光素子は以下の工程によって作
成した。：ｉず、ｎ＋型１ｎＰ基［１上に、ｎ＋型１ｎ
Ｐバッファ層２を１”ｐｍ厚に、キャリア濃度〜２ Ｘ
１０” ａｍ−’のｎ−型１ ｎ ｏ、 ｓ３Ｇ ａ
０．４７Ａ、ｓ層３を１μｍ厚に〜キャリア濃度０．
５〜１×１０＋９０づのρ−ＩｎＰ層４を〜１μ凱厚に
順次に有機金属気相成長法を用いて成長した後、３０μ
ｍΦの受光領域を残して、基板に達するまでエツチング
し、高さ〜３μｍのメサを形成した０次に３Ｘ１０−’
Ｐａ以下の高真空で５ｒＦｔ （格子定数５．８０人
）、ＢａＦ２ （格子定数６．２０人）を分子ビーム成
長法により蒸着した。（ネ）この成長方法は、浅野らが
、Ｊ、Ｊ、Ａ、Ｐ ２２ ｐ、１４７４ （１９８３
年）で、Ｓ１系においてＣａＦ２、ＳｒＦ２、Ｂ−ａＦ
ｚの成長をすでに行っている。ＩｎＰの格子定数は５．
８６人であり、これら３結晶とも立方晶型であることか
ら、両フッ化物の混晶（Ｓｒ、Ｂａ）Ｆ２はＩｎＰに格
子整合することが可能である。このため、メサ側面の埋
込み界面に界面準位は発生しない。成長に際しては、予
め受光領域メサ上部だけに、プラズマＣＶＤで堆積させ
たアモルファスＳｉＮ膜のマスクを形成しておき、メサ
部以外のｆｌＪｔ域に（Ｓｒ、Ｂａ）Ｆ２を選択的にエ
ピタキシャル成長し、その厚みを〜３μｍとメサの高さ
と同じにすることで一プレーナ埋込みを実現した。最後
にＰ、ｎ両＋１ＩＩＪ ｔ Ｋを各々、ＡｕＺｎ、Ａｕ
Ｇｅ で形成した。A semiconductor single-water photodetector, not shown in FIG. 1, was fabricated by the following steps. : izu, n+ type 1nP group [on 1, n+ type 1n
The P buffer layer 2 has a thickness of 1”pm, and the carrier concentration is ~2×
10” am-' n-type 1 no, s3G a
0.47A, S layer 3 1 μm thick ~ carrier concentration 0.
5 to 1×10+90 ρ-InP layers 4 were sequentially grown to a thickness of ~1 μm using metal organic vapor phase epitaxy, and then 30 μm thick.
A 0-order 3X10-' mesa with a height of ~3 μm was formed by etching until it reached the substrate, leaving a light-receiving area of mΦ.
5 rFt (lattice constant: 5.80 m) and BaF2 (lattice constant: 6.20 m) were deposited by molecular beam growth in a high vacuum of Pa or less. (ne) This growth method was described by Asano et al., J, J, A, P 22 p, 1474 (1983
), CaF2, SrF2, B-aF in S1 system
We are already growing z. The lattice constant of InP is 5.
Since these three crystals are all cubic crystals, the mixed crystal (Sr, Ba) of both fluorides (F2) can be lattice matched to InP. Therefore, no interface states are generated at the buried interface on the side surface of the mesa. During growth, a mask of an amorphous SiN film deposited by plasma CVD is formed in advance only on the upper part of the mesa in the light receiving area, and (Sr, Ba)F2 is selectively epitaxially grown in the flJt region other than the mesa. One planar embedment was achieved by making the thickness ~3 μm, which is the same as the mesa height. Finally, P, n + 1IIJ t K, AuZn, Au
It was formed from Ge.
この実施例において、メサ径３０μｍΦ、１０Ｖバイア
ス時接合容量Ｃｊ ＝０．１５ｐ Ｆ以下に対して（ポ
ンディングパッド５０ｕｍΦにおいて）配線容量Ｃｐａ
ｄ ＝０．０４ｐ Ｆ以下であり、配線容量は無視しう
′る値となった。このため、５０Ω負荷抵抗時のＣＲ時
定数によるカットオフ周波数は２１ＧＨｚとなる。一方
、キャリアの空乏層走行時間制限によるカットオフ周波
数が３０ＧＨｚであることから、本素子は接合容量によ
るＣＲ時定数制限を受けており、本構造においてメサ径
をさらに微小化することだけでさらに高速化できる。ま
た、暗電流は、１０Ｖバイアス時において７０ｐＡ以下
と、従来のプレーナ型素子と較べても低い値であった。In this example, when the mesa diameter is 30 μmΦ and the junction capacitance at 10 V bias is less than Cj = 0.15 pF (at the bonding pad of 50 μmΦ), the wiring capacitance Cpa
d = 0.04 pF or less, and the wiring capacitance was a negligible value. Therefore, the cutoff frequency due to the CR time constant when the load resistance is 50Ω is 21GHz. On the other hand, since the cutoff frequency is 30 GHz due to the carrier depletion layer transit time limit, this device is subject to the CR time constant limit due to the junction capacitance. can be converted into Further, the dark current was 70 pA or less at a bias of 10 V, which was a low value even compared to conventional planar elements.
（発明の効果）
以上に実施例を挙げて詳し・く説明したように、本発明
によれば、高速に応答し、暗電流が小さく、１言１“ｎ
性に優れた半導体受光素子を得ることかでき、その価値
は大きい。(Effects of the Invention) As described above in detail with reference to embodiments, the present invention provides high-speed response, small dark current, and
It is possible to obtain a semiconductor light-receiving element with excellent properties, which is of great value.
第１図は本発明の一実施例のＪｔ４造を示す断面図、第
２図は従来の半導体受光素子の構造を示す断面図である
。
図において、１はｎ＋型半導体基板、２はｎ型パンファ
ー層、３は光吸収層、４はｐ十型キャップ層、５は半導
体基板と格子整合する誘電体絶縁物理込み層、６は無反
射コーテイング膜、７はＰ ！ｐＩＪ電、（支）、８は
ｎ側電極、９はリング電極（ｐ側電極の一部）、１１は
半絶縁性ＩｎＰ基板、１２はｎ＋型ＩｎＰバッファ層、
１３はｎ−型Ｉｎａ、ｓｓＧ ａ Ｏ４７Ａ Ｓ光吸収
層、１４はｐ＋型キャップ層、１５は受光部、１６はｎ
側室優、１７はエアブリッジ型９１則電極て゛ある。FIG. 1 is a sectional view showing a Jt4 structure according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of a conventional semiconductor light receiving element. In the figure, 1 is an n+ type semiconductor substrate, 2 is an n-type breadth layer, 3 is a light absorption layer, 4 is a p-type cap layer, 5 is a dielectric insulating physically embedded layer that is lattice matched to the semiconductor substrate, and 6 is a non-reflective layer. Coating film, 7 is P! pIJ electrode (support), 8 is an n-side electrode, 9 is a ring electrode (part of the p-side electrode), 11 is a semi-insulating InP substrate, 12 is an n + type InP buffer layer,
13 is an n-type Ina, ssG a O47A S light absorption layer, 14 is a p+ type cap layer, 15 is a light receiving part, and 16 is an n
Concubine Yu, 17 is an air bridge type 91 rule electrode.
Claims (1)
絶縁物層によって埋込まれていることを特徴とする半導
体受光素子。1. A semiconductor light-receiving element characterized in that the periphery of a light-receiving region is embedded with a dielectric insulator layer that is lattice-matched to a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068959A JPH01239973A (en) | 1988-03-22 | 1988-03-22 | Semiconductor photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068959A JPH01239973A (en) | 1988-03-22 | 1988-03-22 | Semiconductor photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01239973A true JPH01239973A (en) | 1989-09-25 |
Family
ID=13388720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63068959A Pending JPH01239973A (en) | 1988-03-22 | 1988-03-22 | Semiconductor photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01239973A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224460A (en) * | 1993-01-26 | 1994-08-12 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor photodetector and its manufacture |
| KR20010094513A (en) * | 2000-03-31 | 2001-11-01 | 윤종용 | Method for fabricating waveguide photodetectors based on selective area growth technology |
| US7307250B2 (en) | 2003-02-06 | 2007-12-11 | Seiko Epson Corporation | Light-receiving element and manufacturing method of the same, optical module and optical transmitting device |
| US8035187B2 (en) | 2008-02-06 | 2011-10-11 | Sony Corporation | Semiconductor light receiving element and optical communication system |
| JP2012124404A (en) * | 2010-12-10 | 2012-06-28 | Nippon Telegr & Teleph Corp <Ntt> | Photodiode and manufacturing method therefor |
-
1988
- 1988-03-22 JP JP63068959A patent/JPH01239973A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224460A (en) * | 1993-01-26 | 1994-08-12 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor photodetector and its manufacture |
| KR20010094513A (en) * | 2000-03-31 | 2001-11-01 | 윤종용 | Method for fabricating waveguide photodetectors based on selective area growth technology |
| US7307250B2 (en) | 2003-02-06 | 2007-12-11 | Seiko Epson Corporation | Light-receiving element and manufacturing method of the same, optical module and optical transmitting device |
| US8035187B2 (en) | 2008-02-06 | 2011-10-11 | Sony Corporation | Semiconductor light receiving element and optical communication system |
| JP2012124404A (en) * | 2010-12-10 | 2012-06-28 | Nippon Telegr & Teleph Corp <Ntt> | Photodiode and manufacturing method therefor |
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