JPH01239438A - Flaw inspecting device - Google Patents

Flaw inspecting device

Info

Publication number
JPH01239438A
JPH01239438A JP6369988A JP6369988A JPH01239438A JP H01239438 A JPH01239438 A JP H01239438A JP 6369988 A JP6369988 A JP 6369988A JP 6369988 A JP6369988 A JP 6369988A JP H01239438 A JPH01239438 A JP H01239438A
Authority
JP
Japan
Prior art keywords
circuit
flaw
signals
line sensors
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6369988A
Other languages
Japanese (ja)
Other versions
JP2583563B2 (en
Inventor
Noriko Osada
典子 長田
Mitsuhito Kamei
光仁 亀井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63063699A priority Critical patent/JP2583563B2/en
Publication of JPH01239438A publication Critical patent/JPH01239438A/en
Application granted granted Critical
Publication of JP2583563B2 publication Critical patent/JP2583563B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)

Abstract

PURPOSE:To improve the reliability of detection accuracy by performing flaw detection by deciding the outputs of two circuits which calculate the signal differences between two couples of line sensors and a circuit which ORs comparator outputs of two line sensors. CONSTITUTION:The difference between the signals of the lines sensors 1A and 1B is detected by a difference circuit 3A by analog arithmetic operation and a waveform shaping circuit 4A performs detection processing to separate flaws 18A and 18C. Then the signals of the line sensors 1B and 1C are processed similarly to separate flaws 18B and 18D. The signals of the sensors 1A and 1B are converted by comparing circuits 5A and 5B into binary signals, which are ORed by an OR arithmetic circuit 6 to separate a flaw 18E straddling a scanning area. Then flaw signals separated by circuits 4A, 4B, and 6 are decided by a decision circuit 7 and outputted. Consequently, the reliability of the flaw detection accuracy is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、製造工程にある物品の被検査面におけるき
すを高精度で検出するきず検査装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flaw inspection device that detects flaws on the inspected surface of an article in the manufacturing process with high precision.

〔従来の技術〕[Conventional technology]

第4図は例えば実公昭47−6397号公報に示された
従来のきず検査装置を示すブロック接続図であり、図に
おいて、1は撮像素子としてのラインセンサ、5はライ
ンセンサ1からの出力信号を適当なスライスレベル(R
ef)で2値化する比較回路、7は比較回路5の出力信
号からきすがあるか否かを判定する判定回路である。ま
た、第5図(a)において、14は被検査面、16はラ
イン停正時におけるラインセンサ1の視野(図中、斜線
で示す)である。被検査面14が矢印15方向へ走行す
るとき、ラインセンサ1の視野を被検査面換算すると、
1走査時間に被検査面14が移動する距離により、例え
ば第5図(b)のように、幅W。
FIG. 4 is a block connection diagram showing a conventional flaw inspection device disclosed in, for example, Japanese Utility Model Publication No. 47-6397. In the figure, 1 is a line sensor as an image pickup device, and 5 is an output signal from the line sensor 1. to an appropriate slice level (R
ef) is a comparison circuit that performs binarization, and 7 is a determination circuit that determines whether or not there is a scratch from the output signal of the comparison circuit 5. Further, in FIG. 5(a), 14 is the surface to be inspected, and 16 is the field of view of the line sensor 1 when the line is stopped (indicated by diagonal lines in the figure). When the surface to be inspected 14 travels in the direction of the arrow 15, the field of view of the line sensor 1 is converted to the surface to be inspected.
The width W is determined by the distance that the surface to be inspected 14 moves in one scanning time, for example, as shown in FIG. 5(b).

長さしの有効視野を形成する。以下、ラインセンサ1の
有効視野は被検査表面換算した視野とする。
Forms a long effective field of view. Hereinafter, the effective field of view of the line sensor 1 is defined as the field of view converted to the surface to be inspected.

次に動作について説明する。いま、有効視野17内にき
ず18が存在すると、ラインセンサ1から出力される信
号波形は第5図(b)に示すとおりとなる。この信号に
対して比較回路5において2値化処理を行うと、出力信
号は“1”または“0”となり、さらに判定回路7にお
いてその出力信号からきすの有無を判別する。この検査
方法は、有効視野内にきすが存在した場合の反射光が正
常な表面からの反射光に比較して弱くなることを利用し
たものであり、きず検出の分解能は1つのラインセンサ
1の有効視野17の面積に占めるきす部分の面積率に依
存する。
Next, the operation will be explained. Now, if a flaw 18 exists within the effective field of view 17, the signal waveform output from the line sensor 1 will be as shown in FIG. 5(b). When this signal is subjected to binarization processing in the comparator circuit 5, the output signal becomes "1" or "0", and the determination circuit 7 further determines the presence or absence of scratches from the output signal. This inspection method utilizes the fact that the reflected light when a scratch exists within the effective field of view is weaker than the reflected light from a normal surface, and the resolution of flaw detection is the same as that of one line sensor 1. It depends on the area ratio of the scratched portion to the area of the effective field of view 17.

〔発明が解決しようとする課題] 従来のきず検査装置は以上のように構成されているので
、有効視野17における一定以上の面積を持つきずしか
きすと決定できず、小さなきずを単発性のノイズと弁別
することが難しいなどの問題点があった。また、第5図
(c)に示すようにきずがラインセンサ1の隣りあう2
有効視野17a。
[Problems to be Solved by the Invention] Since the conventional flaw inspection device is configured as described above, it is not possible to determine that a flaw with an area larger than a certain level in the effective field of view 17 is a flaw, and it is possible to treat small flaws as single-shot noise. There were problems such as difficulty in distinguishing between Furthermore, as shown in FIG.
Effective field of view 17a.

17bの双方に含まれるように走査された場合には、1
有効視野17aまたは17bに占めるきす部分の面積率
が下がり、その結果、本来検出されるべき面積をもつき
ずの分離が困難になるなどの問題点があった。
17b, then 1
The area ratio of the gap in the effective field of view 17a or 17b decreases, resulting in problems such as difficulty in separation without the area that should be detected.

この発明は上記のような問題点を解消するためになされ
たもので、ラインセンサの持つ分解能により決定される
最小の面積以下のきずパターンの変化を高信頼度をもっ
て検出できるとともに、ラインセンサの走査領域によら
ず被検査面上のきすを高精度で検出できるきず検査装置
を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and is capable of highly reliable detection of changes in flaw patterns smaller than the minimum area determined by the resolution of the line sensor. It is an object of the present invention to provide a flaw inspection device that can detect flaws on a surface to be inspected with high precision regardless of the area.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るきず検査装置は、3台のラインセンサが
移動する被検査面上の少くとも1つの領域を重複してそ
の前後の領域とともに有効視野におき、これらのライン
センサから出力される3系列の信号のうち2系列の信号
を各1の比較回路にて2値化し、論理和演算回路によっ
てこれら2系列の比較回路出力の論理和をとり、一方、
上記3系列の信号のうち2系列を1対として、2対の2
系列の信号の差を差分回路によって求め、この差分回路
と上記論理和演算回路の各出力信号にもとづいて、判定
回路が上記被検査面上のきずの有無を検出するようにし
たものである。
The flaw inspection device according to the present invention overlaps at least one area on the surface to be inspected on which the three line sensors are moving, and places them in the effective field of view together with the areas before and after the area, and the three line sensors output from these line sensors overlap. Two series of signals among the series of signals are binarized by one comparison circuit each, and the outputs of these two series of comparison circuits are logically summed by an OR operation circuit, and on the other hand,
Two of the above three series of signals are considered as one pair, and two pairs of 2
The difference between the signals of the series is determined by a difference circuit, and a determination circuit detects the presence or absence of a flaw on the surface to be inspected based on each output signal of the difference circuit and the OR circuit.

また、この発明の別の発明に係るきず検査装置は、ライ
ンセンサを2台・とじ、これの一方には差分回路を、他
方には加算回路をそれぞれ接続し、これらの各出力を論
理和演算回路の出力とともに、判定回路に入力するよう
に構成したものである。
In addition, a flaw inspection device according to another invention of the present invention combines two line sensors, connects a differential circuit to one of them, and an adder circuit to the other, and performs a logical OR operation on each of these outputs. It is configured to be input to the determination circuit together with the output of the circuit.

〔作用〕[Effect]

この発明における2台の比較回路は、被検査面にライン
センサの分解能以上の大きさのきすが1つの有効視野の
2つの領域にまたがって存在するとき、そのいずれかか
らそのきずの全部を確実に検出し、これをきず信号とし
て判定回路に出力するので、きず検出の信頬性を高める
ことができるとともに、一方、差分回路が3系統のライ
ンセンサの出力のうち2系列を1対として、2対の2系
列の信号の差をとることにより、きず信号の分離を、単
発的なノイズ信号を相殺しながら、確実に行えるように
する。
The two comparison circuits of the present invention ensure that when a scratch larger than the resolution of the line sensor exists on the surface to be inspected across two areas of one effective field of view, all of the scratches can be detected from one of them. Since this is detected as a flaw signal and outputted to the determination circuit, the reliability of flaw detection can be increased.On the other hand, the differential circuit uses two lines out of the three lines of line sensor output as one pair. By taking the difference between two pairs of two series signals, it is possible to reliably separate flaw signals while canceling out isolated noise signals.

また、この発明の別の発明における加算回路は、2系統
のラインセンサの出力の和をとるため、2つの有効視野
内にあって互いに重なり合う領域ではきず信号を2倍と
するも、ノイズ信号は 2倍と小さく抑え、これにより
きず信号の分離を高分解能にて実現できるようにする。
Furthermore, since the adder circuit in another aspect of the present invention sums the outputs of the two lines of line sensors, the flaw signal is doubled in the overlapping area within the two effective fields of view, but the noise signal is This makes it possible to separate flaw signals with high resolution.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。第1
図において、IA、IB、IC,は有効視野が一部で重
複するラインセンサ、2A、2B。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, IA, IB, and IC are line sensors 2A and 2B whose effective fields of view partially overlap.

2Cはハソファアンプ、3Aは2台のラインセンサIA
、IBにより得られた2系列の信号の差をとる差分回路
、3Bは同じ(2台のラインセンサIB、ICから得た
2系列の信号の差をとる差分回路、4A、4Bは差分回
路3A、3Bからの出力信号の波形整形を行う波形整形
回路、5A、5Bは2台のラインセンサIA、IBから
の出力信号をそれぞれ2値化する比較回路、6はこの比
較回路5A、5Bから出力される2値信号の論理和演算
を行なう論理和演算回路、7は波形整形回路4A、4B
および論理和演算回路6から得られる信号を処理して、
きず1の有無を判別し、出力モード設定部8によって設
定された出力モードによって出力すべき判別結果を選択
および出力する判定回路である。
2C is a Hasofa amplifier, 3A is two line sensors IA
, a difference circuit that takes the difference between two series of signals obtained by IB, 3B is the same (a difference circuit that takes the difference between two series of signals obtained from two line sensors IB and IC, 4A, 4B is a difference circuit 3A) , a waveform shaping circuit that shapes the waveform of the output signal from 3B, 5A and 5B are comparison circuits that binarize the output signals from the two line sensors IA and IB, respectively, and 6 is an output from this comparison circuit 5A and 5B. 7 is a waveform shaping circuit 4A, 4B.
and processing the signals obtained from the OR circuit 6,
This is a determination circuit that determines the presence or absence of a flaw 1, and selects and outputs the determination result to be output according to the output mode set by the output mode setting section 8.

また、3台のラインセンサIA、IB、ICは、第2図
(a)に示すように、それぞれ、有効視野17A、17
B、17Cが172ずつオーバーランプするように並列
設置されており、従ってラインセンサIA、IB、IC
は領域(a+b)領域(b十c)。
In addition, the three line sensors IA, IB, and IC have effective fields of view 17A and 17, respectively, as shown in FIG. 2(a).
B, 17C are installed in parallel so that each 172 overlaps, so line sensors IA, IB, IC
is the area (a+b) and the area (b + c).

領域(c+d)をその有効視野17A、17B、17C
とする。また、第2図(b)に示すように、3台のライ
ンセンサIA、IB、ICによって矢印15方向に移動
する被検査面14のきず18A、18B、18C,18
Dが走査されると、バッファアンプ2A、2B、2Cを
介して得られる信号は第2図(c)に示すe I+82
+effとなる。
Area (c+d) is its effective field of view 17A, 17B, 17C
shall be. In addition, as shown in FIG. 2(b), flaws 18A, 18B, 18C, 18 on the surface to be inspected 14 moving in the direction of arrow 15 are detected by three line sensors IA, IB, and IC.
When D is scanned, the signal obtained via the buffer amplifiers 2A, 2B, and 2C is e I+82 as shown in FIG. 2(c).
+eff.

次に動作について説明する。Next, the operation will be explained.

まず、被検査面14に、ラインセンサIA、IB。First, line sensors IA and IB are placed on the surface to be inspected 14.

ICのそれぞれの分解能以下の大きさを持つきず18A
、18B、18C,18Dが存在する場合について説明
する。
18A flaw with a size less than the resolution of each IC
, 18B, 18C, and 18D are present.

ラインセンサIA、IBを介して得られる2系列の信号
el+eZの差を差分回路3Aによりアナログ演算する
と、その出力信号は第2図(c)に示すe4のようにな
る。このとき、信号e4は領域(a+b)−領域(b十
c)によって、領域(a+c)から得られる信号と等価
であり、領域すに相当する信号が消去される。また、場
合等のノイズ信号が(a−c)の演算により相殺される
ので、第2図(b)に示す領域aあるいは領域Cに存在
するきず18Aあるいはきず18Cに対応する信号が波
形整形回路4Aにて分離される。一方、ラインセンサI
B、ICを介して得られる別の2系列の信号e2+83
の差を差分回路3Bによりアナログ演算し、波形整形回
路4Bにて検出処理を行うことによって、領域すあるい
は領域dに存在するきず18Bあるいはきず18Dの分
離が可能になる。すなわち、きず検出の高分解能が実現
できる。しかも、ラインセンサIAの次回の走査領域は
領域(c+d)であることから、同一領域を2回ずつ検
査することになり、高信頼性が得られる。
When the difference between the two series of signals el+eZ obtained via the line sensors IA and IB is subjected to analog calculation by the difference circuit 3A, the output signal becomes e4 shown in FIG. 2(c). At this time, the signal e4 is equivalent to the signal obtained from the area (a+c) due to the area (a+b)-area (b+c), and the signal corresponding to the area is erased. In addition, since the noise signal in case etc. is canceled by the calculation of (a-c), the signal corresponding to the flaw 18A or flaw 18C existing in the area a or area C shown in FIG. Separated at 4A. On the other hand, line sensor I
B, another two series of signals e2+83 obtained via IC
By performing an analog calculation on the difference between the two by the difference circuit 3B and performing detection processing by the waveform shaping circuit 4B, it becomes possible to separate the flaw 18B or the flaw 18D existing in the area or the area d. In other words, high resolution flaw detection can be achieved. Furthermore, since the next scanning area of the line sensor IA is area (c+d), the same area is inspected twice, resulting in high reliability.

次に、被検査面14にラインセンサIA、IBの分解能
以上の大きさを持つキズ18Eが、領域すおよび領域C
にまたがって存在する場合について説明する。このとき
、第1図のラインセンサlAはキズ18Eの一部分のみ
しかとらえておらず、検出できる信号が小さいため、第
1図の比較回路5Aでは分離できない。しかし、ライン
センサIBはきず18Eの全面をその走査領域内に含む
ので、比較回路5Bにてきず信号の分離が可能となる。
Next, a flaw 18E having a size larger than the resolution of the line sensors IA and IB is found on the inspection surface 14 in areas C and C.
We will explain the case where it exists across . At this time, the line sensor 1A in FIG. 1 detects only a portion of the flaw 18E, and the signal it can detect is small, so the comparison circuit 5A in FIG. 1 cannot separate it. However, since the line sensor IB includes the entire surface of the flaw 18E within its scanning area, it becomes possible for the comparison circuit 5B to separate the flaw signals.

そして、比較回路5A、5Bからの出力信号について第
1図の論理和演算回路6にて論理和をとれば、走査領域
にまたがって存在するきすを見逃さず確実に分離できる
。すなわち、きず検出の高信頼性が実現できることにな
る。
If the output signals from the comparison circuits 5A and 5B are logically summed by the logical sum operation circuit 6 of FIG. 1, it is possible to reliably separate the flaws existing across the scanning area without missing them. In other words, high reliability in flaw detection can be achieved.

さらに、第1図において、波形整形回路4A。Furthermore, in FIG. 1, a waveform shaping circuit 4A.

4Bおよび論理和演算回路6にて分離されたきず信号に
ついて、判定回路7で判定を行い、その判定結果の信号
を出力する。この場合において、出力モード設定部8に
おいて、上記2種類のきすを検出分離する機能の機能選
択を、モード設定によって行う。
4B and the flaw signal separated by the OR operation circuit 6, a determination circuit 7 makes a determination and outputs a signal representing the determination result. In this case, in the output mode setting section 8, the function for detecting and separating the two types of scratches is selected by mode setting.

第3図はこの発明の他の実施例を示すものであり、図に
おいて、9はバッファアンプ2A、2Bに接続した加算
回路である。また、第2図に比べてラインセンサIC,
バッファアンプ2Cが省略された以外は、同一である。
FIG. 3 shows another embodiment of the present invention, and in the figure, 9 is an adder circuit connected to buffer amplifiers 2A and 2B. Also, compared to Fig. 2, the line sensor IC,
The configuration is the same except that the buffer amplifier 2C is omitted.

この実施例では、バッファアンプ2A、2Bからの出力
信号を、差分回路3Aにて演算する一方、加算回路9に
おいてもアナログ演算を行う。第2図(b)に示すきず
18A、18Bが存在するとき、加算回路9からの出力
信号は第2図(c)に示す信号e5のようになる。これ
は領域(a+b)十領域(b+c)として得られる領域
(a+2b+c)分の信号であり、演算によって領域す
に存在するきず18Bを示す信号は2倍となる。一方ノ
イズ信号は2倍にしかならないので、結果としてS/N
比が向上したことになり、高分解能を実現できることに
なる。また、差分回路3Aの演算によって、領域aに存
在するきず18Aの分離が可能であるから、結局−回の
走査で領域aおよびbについて高分解能をもって被検査
面上のきずの検査を行うことができる。
In this embodiment, the difference circuit 3A calculates the output signals from the buffer amplifiers 2A and 2B, while the adder circuit 9 also performs analog calculations. When the flaws 18A and 18B shown in FIG. 2(b) are present, the output signal from the adder circuit 9 becomes a signal e5 shown in FIG. 2(c). This is a signal for the area (a+2b+c) obtained as the area (a+b) and the area (b+c), and the signal indicating the flaw 18B existing in the area is doubled by the calculation. On the other hand, since the noise signal only doubles, the resulting S/N
This means that the ratio has been improved, and high resolution can be achieved. Furthermore, since the flaw 18A existing in area a can be separated by the calculation of the difference circuit 3A, it is possible to inspect the flaws on the surface to be inspected with high resolution in areas a and b in - times of scanning. can.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば被検査面上の少くとも
1つの領域を重複して、その前後の領域とともに有効視
野内におく3台のラインセンサと、このうち2台のライ
ンセンサの信号に2値化処理を施す2台の比較回路と、
これらの比較回路の出力の論理和演算回路と、上記3台
のラインセンサのうち2台を1対として2対ずつの各信
号の差をとる2台の差分回路とを備えて、これらの差分
回路および上記論理和演算回路の各出力信号にもとづい
て、判定回路により上記被検査面上のきすを検出するよ
うにしたので、等測的に検査領域を小さくして、きず検
出の分解能を向上できるとともに、有効視野の重複によ
り複数の領域にわたるきず信号の分断による検出不能を
回避でき、検出精度の信頼性を向上できるものが得られ
る効果がある。
As described above, according to the present invention, three line sensors overlap at least one area on the surface to be inspected and are placed within the effective field of view along with the areas before and after the area, and two of these line sensors overlap. Two comparison circuits that perform binarization processing on the signal,
It is equipped with an OR operation circuit for the outputs of these comparison circuits, and two difference circuits that calculate the difference between each pair of signals, with two of the three line sensors as a pair. Based on the output signals of the circuit and the OR circuit, the judgment circuit detects scratches on the surface to be inspected, which reduces the inspection area isometrically and improves the resolution of flaw detection. In addition, it is possible to avoid failure to detect due to division of flaw signals over a plurality of regions due to overlapping effective fields of view, and to improve reliability of detection accuracy.

また、この発明の別の発明によれば、ラインセンサを2
台とし、このうち1台に加算回路を接続したので、きず
信号とノイズ信号とのレベルの違いが明確となり、きず
信号をノイズ信号とは分離して高分解能で検出できるほ
か、回路構成の簡素化並びにローコスト化を図れるもの
が得られる効果がある。
According to another invention of the present invention, the line sensor is
Since the adder circuit is connected to one of these units, the difference in level between the flaw signal and the noise signal is clear, and the flaw signal can be separated from the noise signal and detected with high resolution. This has the effect of providing a product that can be made more efficient and cost-effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例によるきず検査装置を示す
ブロック接続図、第2図はラインセンサの有効視野、被
検査面上のきずパターンおよびブロック接続図各部の信
号波形を示す説明図、第3図はこの発明の他の実施例に
よるきず検査装置を示すブロック接続図、第4図は、従
来のきず検査装置を示すブロック接続図、第5図は従来
のラインセンサの視野、ブロック接続図各部の信号波形
および2つの領域にかかるきすを示す説明図である。 IA、IB、ICはラインセンサ、3A、3Bは差分回
路、5A、5Bは比較回路、6は論理和演算回路、7は
判定回路、9は加算回路。 なお、図中、同一符号は同一、又は相当部分を示す。 (外Z名〕 ロ    ク ト    ケ 手続補正書(自発) 享3.67 昭和     月  日
FIG. 1 is a block connection diagram showing a flaw inspection device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the effective field of view of the line sensor, a flaw pattern on the surface to be inspected, and signal waveforms at each part of the block connection diagram. Fig. 3 is a block connection diagram showing a flaw inspection device according to another embodiment of the present invention, Fig. 4 is a block connection diagram showing a conventional flaw inspection device, and Fig. 5 is a field of view and block connection of a conventional line sensor. FIG. 2 is an explanatory diagram showing signal waveforms in each part of the figure and scratches in two areas. IA, IB, and IC are line sensors, 3A, 3B are differential circuits, 5A, 5B are comparison circuits, 6 is an OR operation circuit, 7 is a determination circuit, and 9 is an addition circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. (Foreign Z name) Procedural amendment (voluntary) Kyo 3.67 Showa Month Day

Claims (2)

【特許請求の範囲】[Claims] (1)移動する被検査面上の少くとも1つの領域を重複
してその前後の領域とともに有効視野内におく3台のラ
インセンサと、これらのラインセンサのそれぞれから出
力される3系列の信号のうち2系列の信号に2値化を施
す2台の比較回路と、これらの比較回路の出力信号の論
理和をとる論理和演算回路と、上記3系列の信号のうち
2系列を1対として、2対の2系列の信号の差をとる2
台の差分回路と、これらの差分回路および上記論理和演
算回路の各出力信号から上記被検査面上のきずの有無を
判定する判定回路とを備えたきず検査装置。
(1) Three line sensors that overlap at least one area on the moving surface to be inspected, together with the areas before and after it, within the effective field of view, and three series of signals output from each of these line sensors. Two comparison circuits that binarize two of the signal series, an OR operation circuit that takes the logical sum of the output signals of these comparison circuits, and two of the above three series of signals as a pair. , take the difference between two pairs of two series signals 2
A flaw inspection device comprising: a differential circuit; and a determination circuit that determines the presence or absence of a flaw on the surface to be inspected from each output signal of the differential circuit and the OR circuit.
(2)移動する被検査面上の少くとも1つの領域を重複
してその前後の領域とともに有効視野内におく2台のラ
インセンサと、これらのラインセンサのそれぞれから出
力される2系列の信号に2値化を施す2台の比較回路と
、これらの比較回路の論理和をとる論理和演算回路と、
上記2系列の信号の差および和をとる差分回路および加
算回路と、これらの差分回路、加算回路および上記論理
和演算回路の各出力信号から上記被検査面上のきずの有
無を判定する判定回路とを備えたきず検査装置。
(2) Two line sensors that overlap at least one area on the moving surface to be inspected, together with the areas before and after it, within the effective field of view, and two series of signals output from each of these line sensors. two comparison circuits that binarize the data, an OR operation circuit that takes the logical sum of these comparison circuits,
A difference circuit and an adder circuit that calculate the difference and sum of the two series of signals, and a determination circuit that determines the presence or absence of a flaw on the surface to be inspected from each output signal of the difference circuit, the adder circuit, and the OR circuit. A flaw inspection device equipped with
JP63063699A 1988-03-18 1988-03-18 Flaw inspection equipment Expired - Fee Related JP2583563B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63063699A JP2583563B2 (en) 1988-03-18 1988-03-18 Flaw inspection equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63063699A JP2583563B2 (en) 1988-03-18 1988-03-18 Flaw inspection equipment

Publications (2)

Publication Number Publication Date
JPH01239438A true JPH01239438A (en) 1989-09-25
JP2583563B2 JP2583563B2 (en) 1997-02-19

Family

ID=13236885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63063699A Expired - Fee Related JP2583563B2 (en) 1988-03-18 1988-03-18 Flaw inspection equipment

Country Status (1)

Country Link
JP (1) JP2583563B2 (en)

Also Published As

Publication number Publication date
JP2583563B2 (en) 1997-02-19

Similar Documents

Publication Publication Date Title
KR940012410A (en) Non-contact surface defect detection method and apparatus
JPH10148619A (en) Method and device for inspecting face defect of substrate under inspection
US6614918B1 (en) Apparatus for inspecting light-and-shade portions and method thereof
JP2003329601A (en) Apparatus and method for inspecting defect
JPS63126242A (en) Appearance inspection and device therefor
JPH01239438A (en) Flaw inspecting device
JPH01134238A (en) Surface flaw inspecting device for steel plate
JPH04143608A (en) Device for measuring flatness of steel plate
JP2000298101A (en) Detecting device for paper sheet
JP2686053B2 (en) Defect inspection method by visual inspection
JP4474006B2 (en) Inspection device
JPS6319793Y2 (en)
JP2508662Y2 (en) Flaw detection device
JP3339128B2 (en) Defect inspection method and apparatus used for its implementation
JPS6199846A (en) Method of detecting defect of strip side end part
JP2758550B2 (en) Appearance inspection device
JPS6055474A (en) Detector for difference between images
JPH04237383A (en) Method for approximating to circular arc in two-dimensional image processing
JPH02171640A (en) Inspection of container
JP2514727B2 (en) Defect inspection method by visual inspection
JPS6311652Y2 (en)
JPH06273348A (en) Surface flaw detection method for steel plate
JPH0558482B2 (en)
JPH04148850A (en) Optical fringe-intensification detecting method
JPS6375545A (en) Appearance inspection device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees