JPH01237993A - Time division switch - Google Patents

Abstract

PURPOSE:To prevent the collision of the data from a RAM and the output data of a buffer by lengthening the ON time of an ON/OFF control signal given to first and second buffer means compared with the reading time of a reading/writing control signal given to the first and second memory means of a time division switch. CONSTITUTION:Input data DAT are inputted to 3-state buffers 102 and 103 and a timing control signal CONT1 is inputted to a delay element 111, an inverter 115 and an OR gate 117. An ON/OFF control signal CONT5 from the gate 117 is added to a buffer 102 and the output of an OR gate 118 to input the output from the inverter 115 is added to a buffer 103. Respective buffers 102 and 103 become ON in the condition of the low level of the ON/OFF control signals CONT5 and CONT6 and become OFF in the condition of the high level. RAM108 and 109 are selected by the address given from address signal lines 123 and 124 and the collision of the output of the RAM108 and 109 and the output of the buffers 102 and 103 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention provides two memory means (RAM) f? The present invention relates to a time division switch provided with the present invention, and particularly relates to read control when reading data from a RAM.

[Conventional technology]

Conventionally, a time division switch is known that includes first and second RAMs that share a data input terminal and a data output terminal, and reading/writing data to and from the first and second RAMs is performed by the first RAM, respectively. and second read/
Controlled by write control signals. by the way,
Generally, during this read/write, it is necessary to control the input data input from the 7'-event terminal to the first and second RAMs.
between the M and the data input terminal, respectively.
first and second on/off controls that provide state buffers and turn off (open) the first and second 3-state buffers f''LL when reading data from the first and second RAMs; signals in first and second three-state buffers, i.e., the first and second on/off control signals are in an inverse relationship with the first and second read/write control signals, respectively. .

[Problem to be solved by the invention]

As mentioned above, in the conventional time division switch, the first and second
Read/write control to RAM.

Since the on/off control of the first and second 3-state buffers that control input data is performed at the same timing, depending on the implementation design of the time division switch, the
When switching between RAMs, there is a risk that data will be output from the first and second RAMs at the same time, and in some cases, data may be output from the first and second RAMs.
This will cause damage to M and 3-state buffers. Furthermore, when the data cycle is short (when the data bit rate is high), there is a risk that the data will be disturbed due to collision of output data from the first and second RAMs, resulting in data errors. .

[Means to solve the problem]

According to the present invention, the first ff1lJ shares the data input terminal and the data output terminal, and is controlled by the first and second read/write control signals, respectively.
and a time division switch having a second memory means, the first panorama being controlled on/off by a first on/off control signal to control input of data to the first memory means. a second buffer means controlled on/off by a second on/off control signal to control input of data to the second memory means; a selection means for selecting one of the output data, and an off region of the first and second on/off control signals each longer than a read region of the first and second read/write control signals by a predetermined period of time; Therefore, a time division switch characterized in that it has a signal adjustment means for adjusting the first and second on/off control signals is obtained.

[For production]

In the time division switch of the present invention, the readout time α of the read/write control signals applied to the first and second memory means (RAM) is compared to the extended area Y.

Since the off time (non-conducting state) of the on/off control signal given to the first and second buffer means (3-state buffer) is lengthened, that is, the first and second RAM, the first and This creates a moment when no data is output from the 3-state buffer. For this one festival, time slots in which no data is output are not used as information bits.

〔Example〕

The present invention will be explained below with reference to Examples.

Referring to FIGS. 1 and 2, a control signal C0NT1 having a frame period of 10 bits is input to a delay element 111 having a delay tt - the length of the data period, and is delayed by 10 bits here. The control signal C0NT2 is output as the control signal C0NT2. This control signal C0NT2 is used as a read/write signal to the memory element (RAM) 108 and a selection control signal to the output selection circuit 106, as will be described later. Further, the control signal C0NT2 is input to the inverter circuit 121.

Here, it is inverted and output as a control signal C0NT3.

This control signal C0NT3 is used as a read/write signal to the RAM 109.

On the other hand, this control signal C0NT2 is input to the delay element 113, where it is further delayed by almost all bits and the control signal C0NT
It is output as a control signal C0NT4 delayed by one pit from NT1. This control signal C0NT4 is input to an inverter circuit 116 and an OR circuit 117. Furthermore, the control signal C0NT1 is applied to the inverter circuit 116.
and is input to the OR circuit 117, and the inverter circuit 115
The outputs of 116 and 116 are input to an OR circuit 118. As shown in FIG. 2, the OR circuit 117 outputs an on/off control signal C0NT5, and the OR circuit 117 outputs an on/off control signal C0NT6.

Data DAT is input to three-state buffers 102 and 103 via input data line 101, as shown in FIG. On the other hand, as described above, the control signal C0NT1 is input at the timing shown in FIG.

As a result, the on/off control signal C0NT5 from the OR circuit 117 is applied to the 3-state buffer 102,
On/off control signal C0NT 6 from OR circuit 118
is added to the 3-state buffer 103.

3-state buffers 102 and 103 are on/off, respectively.
Low (l) of off control signals C0NT5 and C0NT6
It is in the on state when it is at the ow) level, and it is in the off state when it is at the high (formerly gh) level. Therefore, the 3-state buffer 1
02 to part of the data DAT (lW
O3~IWO'9. and lW2O to lW27) are output. Output data D from 3-state buffer 102
AT1 is a read/write signal C according to the address given to the RAM 108 from the address signal line 123.
It is written to RAM I O8 at a low level of 0NT2. Similarly, a portion of the data DAT (2W10 to 2WI
9) is output. And 3 state buffer 103
Output data DAT 2 from RAM 1 is output from RAM 1 at the low level of read/write signal C0NT3 in accordance with the address given to RAM 109 from address signal line 124.
Written in 09.

Read/write signals C0NT 2 and C0NT 3
When becomes high level, RAM 108 and 1 respectively
Data DAT 1 and DAT 2 written in 09 are read out. At this time (when reading data from RAMs 108 and 109), three-state buffers 108 and 109 are rendered non-conductive by on/off control signals C0NT5 and C0NT6, respectively, as shown in FIG. On the other hand, the output selection circuit 106 is supplied with the control signal C0NT2 as a selection control signal, and when the selection control signal C0NT2 is at a high level, the output selection circuit 106 selects the RAM 108 and outputs the 2 selection control signal C.
When 0NT2 is low level, RAM109'z is selected. Therefore, output data DAT3 shown in FIG. 2 is obtained from the output selection circuit 106.

Note that the output data DAT 1 of the 3-state buffer 102
and 1 because the output data of the 3-state delta buffer 103 is
The Oth and 9th data of the 10-bit frame are not used, and as a result, the frame period is 10 bits, but the data capacity is 8 bits. That is, 8 out of 10 bits
Bits are used as data.

〔Effect of the invention〕

As explained above, in the present invention, the first and second RAM
The read area of the first and second read/write control signals applied to the first and second memory means respectively is set to a predetermined time longer than the off area of the first and second on/off control signals applied to the first and second memory means, respectively. Since the output data from the first and second RAM and the first
Collision of data from the second 3-state buffer can also be prevented. Note that, at this time, time slots for data that are not output are not used, and as a result, the time division switch can operate without error 1.

Margin below

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the time division switch according to the present invention, and FIG. 2 is a time chart for explaining the operation of the time division switch shown in FIG. 102...3 state buffer + 103...3 state buffer, 104...input/output line, 105...
Input/output line, 106... Output data selection circuit, 108.
...RAM, 109...RAM, 111...
- Delay element, 113... Delay element, 115... Inverter, 116... Inverter, 117... OR goo), 118... OR &''-), 121... Inverter.

Claims (1)

[Claims] 1. A time division switch having first and second memory means sharing a data input terminal and a data output terminal and whose read/write is controlled by first and second read/write control signals, respectively, a first buffer means controlled on/off by a first on/off control signal to control input of data to the first memory means; and a first buffer means controlled on/off by a second on/off control signal. a second buffer means for controlling input of data to the second memory means; and a selection means for selecting one of the output data from the first and second memory means;
the first and second on/off control signals such that off regions of the first and second on/off control signals are longer than read regions of the first and second read/write control signals by a predetermined time;
and signal adjustment means for adjusting the second on/off control signal.