JPH01236671A - Manufacture of semiconductor laser - Google Patents

Manufacture of semiconductor laser

Info

Publication number
JPH01236671A
JPH01236671A JP6418588A JP6418588A JPH01236671A JP H01236671 A JPH01236671 A JP H01236671A JP 6418588 A JP6418588 A JP 6418588A JP 6418588 A JP6418588 A JP 6418588A JP H01236671 A JPH01236671 A JP H01236671A
Authority
JP
Japan
Prior art keywords
mask
semiconductor
thin film
compound semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6418588A
Other languages
Japanese (ja)
Other versions
JP2819556B2 (en
Inventor
Koji Yamazaki
康二 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63064185A priority Critical patent/JP2819556B2/en
Publication of JPH01236671A publication Critical patent/JPH01236671A/en
Application granted granted Critical
Publication of JP2819556B2 publication Critical patent/JP2819556B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To simplify the manufacturing process by a method wherein a semiconductor wafer is subjected to etching through a mask and the mask is used for the selective formation of a II-VI compound semiconductor thin film on the substrate surface. CONSTITUTION:A clad layer 2, active layer 3, clad layer 4, contact layer 5, and an SiO2 film 6 are formed on a semiconductor substrate 1 and, using photolithography, unnecessary SiO2 film is removed for the formation of an SiO2 mask. The contact layer 5 and upper clad layer 4 are then removed by etching through the intermediary of the SiO2 mask, and the mask is further utilized for the selective formation of an II-VI compound semiconductor thin film on the semiconductor surface. This technique dispenses with the process of removing deposits from on the mask.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はII−VI族化合物半導体の埋め込み層を有す
る半導体レーザの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor laser having a buried layer of a II-VI compound semiconductor.

〔従来の技術〕[Conventional technology]

従来のII−VI族化合物半導体薄膜の形成法では、第
3図(d)に示した様にマスク上にI[−VI族化合物
半導体の堆積か行われる為、これを除去する第3図(d
)から第3図(e)への工程が必要であった。従来行わ
れていた、マスク上のII−VI族化合物半導体の除去
する2つの方法を以下に述べる。
In the conventional method of forming a II-VI group compound semiconductor thin film, the I[-VI group compound semiconductor is deposited on a mask as shown in FIG. d
) to FIG. 3(e) were necessary. Two conventional methods for removing Group II-VI compound semiconductors on a mask will be described below.

1.7第1・リングラフィ技術により、半導体ウェハー
表面上にエピタキシャル成長したn −VI族化合物半
導体薄膜だけを残し、マスク上に堆積したIt −VI
族化会物半導体のみをエツチングにより除去する。
1.7 First, by phosphorography technology, only the n-VI group compound semiconductor thin film epitaxially grown on the semiconductor wafer surface is left behind, and It-VI deposited on the mask.
Only the compound semiconductor is removed by etching.

2、半導体ウェハー表面にエピタキシャル成長した単結
晶n −VI族化合物半導体と、マスク上に堆積した多
結晶のn−vr族化合物半導体とのエツチングレートの
違いにより、マスク上にff1mした■−■族化合物半
導体のみを選択的に除去する。
2. Due to the difference in etching rate between the single crystal n-VI group compound semiconductor epitaxially grown on the semiconductor wafer surface and the polycrystalline n-vr group compound semiconductor deposited on the mask, the Selectively remove only semiconductors.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

しかし、前述の従来技術ではマスク上に堆積したn−v
i族化合物半導体を除去する工程が必要となる為、歩留
りが低下するという問題点を有する。
However, in the prior art described above, the n-v deposited on the mask
Since a process for removing the i-group compound semiconductor is required, there is a problem in that the yield is reduced.

そこで本発明は、この様な問題点を解決するもので、そ
の目的とするところは、マスク上に全く堆積物のない■
−■族化合物半導体薄膜のエピタキシャル成長法により
埋め込み層を形成する半導体レーザの製造方法を提供す
るところにある。
Therefore, the present invention is intended to solve these problems, and its purpose is to completely eliminate deposits on the mask.
Another object of the present invention is to provide a method for manufacturing a semiconductor laser in which a buried layer is formed by an epitaxial growth method of a group compound semiconductor thin film.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体レーザの製造方法は、半導体基板上にク
ラッド層、活性層、クラッド層を積層する工程と、前記
半導体ウェハーにマスクを形成する工程と、前記マスク
を介して半導体ウェハーをエツチングする工程と、前記
マスクを用いて半導体表面に選択的に■−■族化合物半
導体薄膜を形成する工程を少なくとも含むことを特徴と
する。
The method for manufacturing a semiconductor laser of the present invention includes the steps of stacking a cladding layer, an active layer, and a cladding layer on a semiconductor substrate, forming a mask on the semiconductor wafer, and etching the semiconductor wafer through the mask. The method is characterized in that it includes at least the step of selectively forming a thin film of a 1-2 group compound semiconductor on a semiconductor surface using the mask.

〔実 施 例〕〔Example〕

第1図(a)〜(b)は本発明の実施例における半導体
レーザの製造工程を示す断面図であって、以下に半導体
レーザの製造工程を順に述べる。
FIGS. 1(a) and 1(b) are cross-sectional views showing the manufacturing process of a semiconductor laser in an embodiment of the present invention, and the manufacturing process of the semiconductor laser will be described below in order.

rt型の伝導型を有するGaAs基板1上に、n型A、
G O,4Gao、* Asより成る下部クラッド層2
、ノンドープA 1 olsG a o、 ssA s
より成る活性′J:層3、P型のAj O,4G ao
6A sより成る上部コンタクト層4、P型のGaAs
より成るコンタクト層5をMOCVD法によりエピタキ
シャル成長し、該ウェハー上面にS i H4を原料と
する熱CVD法により5i02膜6を形成する。この状
態が第1図(a)である0次にフォトリングラフィ技術
により、不要な5102Mを沸酸系のエッチャントによ
り除去し、5in2マスクを第1図(b)の様に形成す
る。該5i02マスクを介して硫酸系のエッチャントに
よりコンタクト層及び上部クラッド層の一部をエツチン
グ除去し、第1図(c)の様にする。この状態で第2図
に示したM OCV D装置によりSiO2膜によりマ
スクされていない部分にZn5e薄膜7を選択的にエピ
タキシャル成長し第1図(d)の様にする。
On a GaAs substrate 1 having rt-type conductivity, n-type A,
Lower cladding layer 2 made of G O, 4Gao, *As
, non-doped A 1 olsG ao, ssA s
Active 'J: layer 3, P-type Aj O, 4G ao
Upper contact layer 4 made of 6A s, P-type GaAs
A contact layer 5 is epitaxially grown by MOCVD, and a 5i02 film 6 is formed on the upper surface of the wafer by thermal CVD using SiH4 as a raw material. In this state, as shown in FIG. 1(a), unnecessary 5102M is removed by 0-order photolithography technique using a hydrofluoric acid-based etchant, and a 5in2 mask is formed as shown in FIG. 1(b). The contact layer and a portion of the upper cladding layer are etched away using a sulfuric acid-based etchant through the 5i02 mask, as shown in FIG. 1(c). In this state, a Zn5e thin film 7 is selectively epitaxially grown on the portions not masked by the SiO2 film using the MOCVD apparatus shown in FIG. 2, as shown in FIG. 1(d).

第2図に示したMOCVD装置の各部の説明は以下の様
である。
The description of each part of the MOCVD apparatus shown in FIG. 2 is as follows.

石英製横型反応管10の内部にはグラファイト製サセプ
ター11が置かれ、該サセプター上に基板12が置かれ
る。前記石英製横型反応管の側面に配置されたコイル1
3に高周波を印加することにより、前記グラファイト製
サセプターを誘導加熱され基板の加熱が行われる。
A graphite susceptor 11 is placed inside the quartz horizontal reaction tube 10, and a substrate 12 is placed on the susceptor. Coil 1 arranged on the side surface of the quartz horizontal reaction tube
By applying high frequency to 3, the graphite susceptor is heated by induction, and the substrate is heated.

基板温度のalす定は、グラファイト製サセプター中に
埋め込まれた熱電対14により行う0石英製横型反応管
は排気ポンプ15及び廃ガス処理系16とバルブ17及
び18を介して接続されており、減圧及び常圧での成長
か可能となっている。■族原料としてのジメチル亜鉛1
つ及び■族原料であるジメチルセレン20は、室温付近
で液体である為バブラー21.22の中に入っており、
水素ボンベ23よつ水素′J?I製器24を通してマス
フローコントローラ25により流量を正確に制御された
水素をキャリアガスとして石英製横型反応管へ導入され
る。又、原料の供給量を一定に保つ為、前記バブラーは
恒温槽26内に入っており、水素キャリアガスによるバ
ブリング時の温度を一定に閑っている。水素キャリアガ
スによりバブリングレジメチル亜鉛及びジメチルセレン
を含む原料ガスは、希釈の為の水素ガスと合流した後、
三方バルブ27により石英製横型反応管内への導入或い
は廃ガス処理系への切り換えが行われる。第2図には横
型反応管を用いたMOCVD装置の構成を示したが、縦
型反応管を用いた場合も基本的構成は同じである6但し
縦型反応管の場合基板の回転機構を設けることにより、
得られる膜の膜厚及び膜質の均一性を確保する必要があ
る。
The substrate temperature is controlled by a thermocouple 14 embedded in a graphite susceptor.The quartz horizontal reaction tube is connected to an exhaust pump 15 and a waste gas treatment system 16 via valves 17 and 18. Growth under reduced pressure or normal pressure is possible. ■Dimethylzinc 1 as a group raw material
Dimethyl selenium 20, which is a raw material for Groups 2 and 2, is in a bubbler 21.22 because it is liquid at around room temperature.
Hydrogen cylinder 23 hydrogen'J? Hydrogen, the flow rate of which is accurately controlled by a mass flow controller 25, is introduced as a carrier gas into a quartz horizontal reaction tube through an I-manufacturer 24. Further, in order to keep the supply amount of the raw material constant, the bubbler is placed in a constant temperature bath 26 to keep the temperature constant during bubbling with the hydrogen carrier gas. After bubbling with hydrogen carrier gas, the raw material gas containing dimethylzinc and dimethylselenium is combined with hydrogen gas for dilution.
A three-way valve 27 allows the gas to be introduced into the quartz horizontal reaction tube or switched to the waste gas treatment system. Figure 2 shows the configuration of an MOCVD apparatus using a horizontal reaction tube, but the basic configuration is the same even when a vertical reaction tube is used.6 However, in the case of a vertical reaction tube, a substrate rotation mechanism is provided. By this,
It is necessary to ensure uniformity in the thickness and quality of the resulting film.

次に上記MOCVD装置を用いたZn5e薄膜の成長手
HITを以下に説明する。第1図(c)の様になった基
板をサセプター上に置き、排気ポンプにより反応管内を
排気する。次に水素精製器を通した水素ガスを反応管内
に導入する。その後コイルに高周波電圧を印加し1.基
板を成長温度まで昇温する。温度が安定したら、■族及
びVI族原料であるジメチル亜鉛及びジメチルセレンを
反応管内に導入しZn5e薄膜の成長を開始する。成長
条件は以下に示す通りである。
Next, HIT for growing a Zn5e thin film using the above MOCVD apparatus will be described below. The substrate as shown in FIG. 1(c) is placed on a susceptor, and the inside of the reaction tube is evacuated using an exhaust pump. Next, hydrogen gas that has passed through a hydrogen purifier is introduced into the reaction tube. After that, apply a high frequency voltage to the coil.1. The substrate is heated to the growth temperature. Once the temperature is stabilized, dimethylzinc and dimethylselenium, which are Group Ⅰ and Group VI raw materials, are introduced into the reaction tube to start growing a Zn5e thin film. The growth conditions are as shown below.

成長温度      ;550°C 成長圧力      ; 40Torrジメチル亜j9
供給M  ; 1 x 10−51ol /minジメ
チルセレン供給m ; 4 x 10−’rQol /
n+1nVI/n比     ;4 水素ガス流量    ; lj /lin上記の成長条
件で、Zn5e薄膜の成長速度は約1μn/hであった
。Zn5e薄膜の厚さが、コンタクト層上面の高さと等
し7くなる様にZn5e薄膜7の成長を行う。
Growth temperature: 550°C Growth pressure: 40 Torr dimethyl chloride
Supply M; 1 x 10-51 ol/minDimethylselenium supply m; 4 x 10-'rQol/
n+1nVI/n ratio; 4 Hydrogen gas flow rate; lj/lin Under the above growth conditions, the growth rate of the Zn5e thin film was about 1 μn/h. The Zn5e thin film 7 is grown so that the thickness of the Zn5e thin film is 7, which is equal to the height of the upper surface of the contact layer.

この時、5i02マスク上にはZn5eの堆積物は全く
ない、この時の状態を示したのが第1図(d)である。
At this time, there was no deposit of Zn5e on the 5i02 mask, and FIG. 1(d) shows the state at this time.

その後5i02膜を沸酸系の工・ンチング液にて除去し
金属電極8を蒸着してレーザの構造ができる。この状態
が第1図(e)である。
Thereafter, the 5i02 film is removed using a hydrochloric acid-based etching solution, and a metal electrode 8 is deposited to form a laser structure. This state is shown in FIG. 1(e).

尚、前記したZn5e薄膜の成長条件以外でも、例えば
成長温度が500°C以上600℃以下、成長圧力がl
 Q Q Torr以下、VI/II比が6以下、又原
料としてジエチル亜鉛及びジエチルセレンを用いた場合
、或いはこれらの原料を組み合わせた場合においてもZ
n5eの選択エピタキシャル成長する。又、■族原料と
してジメチル硫黄、ジエチル硫黄、ジメチルテルル、ジ
エチルテルル及び■族原料としてジメチルカドミウム等
を用いることによりZ n S 、 Z n 1’ e
 、 Cd S 、Cd S e 、 Cd T e等
のII−VI族化合物半導体薄膜の選択エピタキシャル
成長も可能である。
In addition, there are conditions other than the growth conditions for the Zn5e thin film described above, such as a growth temperature of 500°C or more and 600°C or less, and a growth pressure of l.
Q Q Torr or less, VI/II ratio is 6 or less, and Z
Selective epitaxial growth of n5e. In addition, by using dimethyl sulfur, diethyl sulfur, dimethyl tellurium, diethyl tellurium, etc. as group Ⅰ raw materials and dimethyl cadmium as group Ⅰ raw materials, Z n S , Z n 1' e
It is also possible to selectively epitaxially grow II-VI group compound semiconductor thin films such as , CdS, CdSe, and CdTe.

〔発明の効果〕〔Effect of the invention〕

以上述べた様に本発明の半導体レーザの製造方法によれ
ばn−VI族化合物半導体薄膜層か自己整合的に形成で
きる為以下の様な効果を有する。
As described above, according to the method of manufacturing a semiconductor laser of the present invention, since the n-VI group compound semiconductor thin film layer can be formed in a self-aligned manner, it has the following effects.

(a)マスク上にII−VI族化合物半導体の堆積物が
全くない為、従来技術では必要であったマスク上の堆積
物を除去する工程が省略できる。
(a) Since there is no deposit of the II-VI group compound semiconductor on the mask, the step of removing the deposit on the mask, which was necessary in the prior art, can be omitted.

(b)(a)と関連し、工程が簡略化された分、歩留り
が大riに向上する。
(b) In relation to (a), the yield is greatly improved due to the simplified process.

(C)(a)と関連し、従来技術においてマスク上の堆
積物をエツチング除去する際、エツチングされる必要の
ないZ n S e rtjJ或いはコンタク)・層が
エツチングされることがあったが、本発明においては不
要なエツチングは行われない為デバイスとしての性能及
び信顆性が向上する。
(C) Related to (a), when removing deposits on a mask by etching in the prior art, a layer that does not need to be etched is sometimes etched. In the present invention, since unnecessary etching is not performed, the performance and reliability of the device are improved.

(d)フォi・リソグラフィ技術を用いてパターン形成
がII−VI族化合物半導体よりも容易なマスク材を選
ぶことにより、微細加工が可能となる。
(d) Fine processing becomes possible by selecting a mask material whose pattern formation is easier than that of II-VI group compound semiconductors using photolithography technology.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)・〜(e)は本発明における半導体レーザ
の製造工程を示す断面図。 第2図は本発明におけるII−VI族化合物半導体薄膜
を形成する為のM OCV D装置の構成概略断面図。 第3図(a)〜(f)は従来技術における半導体レーザ
の製造工程を示す断面図。 1・・・n型GaAs基板 2−−−n型A、I!0.4 Gao6As(下部クラ
ッド層) 3 ・・・AN o、+5Gao、asAs4−−− 
P型AJ o4Gao6As(上部クラッド層) 5・・・P型G5As (コンタクト層)6・・・5i
02膜 7 ・ ・ ・ Zn5e 薄j摸 8・・・金属電極 9・・・Zn5e堆積物 10・・・石英製横型反応管 11・・・グラファイト製サセプター 12・・・基板 13・・・コイル 14・・・熱電対 15・・・排気ポンプ 16・・・廃ガス処理系 17・・・バルブ 18・・・バルブ 1つ・・・ジメチル亜鉛 20・・・ジメチルセレン 21・・・バブラー 22・・・バブラー 23・・・水素ボンベ 24・・・水素精製器 25・・・マスフローコントローラー 26・・・恒温槽 27・・・三方バルブ 28・・・バルブ 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 最 上  務(他1名)()11) 
          (e/)(C,) (久)(り (ト〕              じ)(0)   
                       (チ
)/ =、))6: B !I ]I−1:)L ”j
F 狭多う困
FIGS. 1(a) to 1(e) are cross-sectional views showing the manufacturing process of a semiconductor laser according to the present invention. FIG. 2 is a schematic cross-sectional view of the configuration of an MOCVD apparatus for forming a II-VI group compound semiconductor thin film in the present invention. FIGS. 3(a) to 3(f) are cross-sectional views showing the manufacturing process of a semiconductor laser in the prior art. 1... n-type GaAs substrate 2---n-type A, I! 0.4 Gao6As (lower cladding layer) 3...AN o, +5Gao, asAs4---
P-type AJ o4Gao6As (upper cladding layer) 5...P-type G5As (contact layer) 6...5i
02 membrane 7 ・ ・ ・ Zn5e thin j model 8...Metal electrode 9...Zn5e deposit 10...Quartz horizontal reaction tube 11...Graphite susceptor 12...Substrate 13...Coil 14 ... Thermocouple 15 ... Exhaust pump 16 ... Waste gas treatment system 17 ... Valve 18 ... One valve ... Dimethyl zinc 20 ... Dimethyl selenium 21 ... Bubbler 22 ...・Bubbler 23...Hydrogen cylinder 24...Hydrogen purifier 25...Mass flow controller 26...Thermostatic chamber 27...Three-way valve 28...Valve and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Senior Executive (1 other person) ()11)
(e/) (C,) (ku) (ri (to) ji) (0)
(chi)/=,))6: B! I ] I-1:) L ”j
F cramped and troubled

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上にクラッド層、活性層、クラッド層を積
層する工程と、前記半導体ウェハーにマスクを形成する
工程と、前記マスクを介して半導体ウェハーをエッチン
グする工程と、前記マスクを用いて半導体表面に選択的
にII−VI族化合物半導体薄膜を形成する工程を少なくと
も含むことを特徴とする半導体レーザの製造方法。
A step of laminating a cladding layer, an active layer, and a cladding layer on a semiconductor substrate, a step of forming a mask on the semiconductor wafer, a step of etching the semiconductor wafer through the mask, and a step of etching the semiconductor surface using the mask. 1. A method for manufacturing a semiconductor laser, the method comprising at least the step of selectively forming a II-VI group compound semiconductor thin film.
JP63064185A 1988-03-17 1988-03-17 Manufacturing method of semiconductor laser Expired - Lifetime JP2819556B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63064185A JP2819556B2 (en) 1988-03-17 1988-03-17 Manufacturing method of semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63064185A JP2819556B2 (en) 1988-03-17 1988-03-17 Manufacturing method of semiconductor laser

Publications (2)

Publication Number Publication Date
JPH01236671A true JPH01236671A (en) 1989-09-21
JP2819556B2 JP2819556B2 (en) 1998-10-30

Family

ID=13250749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63064185A Expired - Lifetime JP2819556B2 (en) 1988-03-17 1988-03-17 Manufacturing method of semiconductor laser

Country Status (1)

Country Link
JP (1) JP2819556B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6284581A (en) * 1985-10-08 1987-04-18 Fujitsu Ltd Semiconductor light-emitting device
JPS6316689A (en) * 1986-07-09 1988-01-23 Fujitsu Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6284581A (en) * 1985-10-08 1987-04-18 Fujitsu Ltd Semiconductor light-emitting device
JPS6316689A (en) * 1986-07-09 1988-01-23 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date
JP2819556B2 (en) 1998-10-30

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